#include #include #pragma config PLLDIV = 1 #pragma config CPUDIV = OSC3_PLL4 #pragma config USBDIV = 2 #pragma config FOSC = XTPLL_XT #pragma config FCMEM = OFF #pragma config IESO = OFF #pragma config PWRT = OFF #pragma config BOR = ON #pragma config BORV = 21 #pragma config VREGEN = ON #pragma config WDT = OFF #pragma config WDTPS = 32768 #pragma config MCLRE = ON #pragma config LPT1OSC = OFF #pragma config PBADEN = OFF #pragma config CCP2MX = ON #pragma config STVREN = ON #pragma config LVP = OFF #pragma config ICPRT = OFF #pragma config XINST = OFF #pragma config DEBUG = ON #pragma config CP0 = OFF #pragma config CP1 = OFF #pragma config CP2 = OFF #pragma config CP3 = OFF #pragma config CPB = OFF #pragma config CPD = OFF #pragma config WRT0 = OFF #pragma config WRT1 = OFF #pragma config WRT2 = OFF #pragma config WRT3 = OFF #pragma config WRTB = OFF #pragma config WRTC = OFF #pragma config WRTD = OFF #pragma config EBTR0 = OFF #pragma config EBTR1 = OFF #pragma config EBTR2 = OFF #pragma config EBTR3 = OFF #pragma config EBTRB = OFF unsigned char POT_VALUE, delay; void main(void) { PORTA = 0x00; // clear all PORTA pins TRISA = 0x05; // set up RA0/AN0 and RA2 as inputs and set up RA1 and RA3..RA5 as outputs ADCON0 = 0x01; // select AN0, enable A/D module ADCON1 = 0x0E; // set up RA0/AN0 as an analog input and set up RA1..RA5 as digital I/Os ADCON2 = 0x2E; // configure A/D module result to left justified, acquisition time to 32 us, and clock period to 2.67 us ADCON0 = 0x03; // select AN0 and set GO_DONE bit to start A/D conversion while (ADCON0bits.GO_DONE); // do nothing until the A/D conversion is done POT_VALUE = ADRESH; // move the 8 most significant bits of the result into POT_VALUE while (1) { Delay1KTCYx(72); // 12 ms if (PORTAbits.RA2) { // if button pushed ... ADCON0 = 0x03; // update POT_VALUE while (ADCON0bits.GO_DONE); POT_VALUE = ADRESH; } PORTAbits.RA1 = 1; // control signal high Delay100TCYx(54); // .9 ms for (delay=0; delay