/*
 Main Control
 */
 module projectmaint(rawclk, speaker, keys, hex1, hex2); 
 
 input rawclk; 	//50Mhz clock signal
 input [0:7]keys;	//array of key inputs. keys default high
 
 output speaker;	//audio output, block form signal, add capacitor on output to transform to sine wave
 
 output [0:6]hex1;	//seven segment display outputs
 output [0:6]hex2;
 
 wire [3:0]statevalue;
 wire [7:0]gkeys;
 
 //invert buttons
 assign gkeys = ~keys;
 
  //module calls
 tonemaker     					tonemakerinst1(rawclk, statevalue, speaker);  	//makes requested note
 keyboard							keyinstance1(gkeys, statevalue);						//handles inputs
 sevsegdisplaynote				disnoteinstance1(hex2, hex1, statevalue);			//displays current note
 
 endmodule
 
 /*
 ##############################################################################################################
 This module turns a clock signal into a series of niece clock signals
 This module makes an array of clock values on an exponential scale.
 For use with the tone generator.
 pll currently outputs 8.388Mhz clock
 Qq[0]  is 50 Mhz
 Qq[32] is 50 Mhz * 1/(2^32)
*/

 module clockschemearray(rawclk, clkarray0, clkarray1, clkarray2, clkarray3, clkarray4, clkarray5);

 parameter n = 32;
 input rawclk;
 //each clkarry will give a given note over an array of different octives
 output [n-1:0]clkarray0;
 output [n-1:0]clkarray1;
 output [n-1:0]clkarray2;
 output [n-1:0]clkarray3;
 output [n-1:0]clkarray4;
 output [n-1:0]clkarray5;

 wire slwclk0, slwclk1, slwclk2, slwclk3, slwclk4, slwclk5;
 wire plllocked;//output from pll module thats not needed
 
 
 //function calls
 //the upcounters are counters that are being used as clock dividers.
 upcounter32 					counterinstance0(slwclk0, clkarray0);
 upcounter32 					counterinstance1(slwclk1, clkarray1);
 upcounter32 					counterinstance2(slwclk2, clkarray2);
 //Pll calls a phase lock loop function from the library that comes with quartus 2 15.0.
 //The phase lock loop takes in a 50mH clock signal and alters it to a slightly slower clock signal
 //that when diveded by powers of two gives a precise frequecy.  This way the output signal can be put throught 
 //a clock divider and will come out with the exact frequecy required for a certain note.
 pll 							pllinstance1(0, rawclk, slwclk0, slwclk1, slwclk2, plllocked);
 
 upcounter32 					counterinstance3(slwclk3, clkarray3);
 upcounter32 					counterinstance4(slwclk4, clkarray4);
 upcounter32 					counterinstance5(slwclk5, clkarray5);
 pll2 							pllinstance2(rawclk, slwclk3, slwclk4, slwclk5);
 endmodule
 
/*
##############################################################################################################
This module plays a given tone
*/

module tonemaker(rawclk, statevalue, speaker);
input rawclk;
input [3:0]statevalue;
output reg speaker;

wire [31:0]clkarray0;
wire [31:0]clkarray1;
wire [31:0]clkarray2;
wire [31:0]clkarray3;
wire [31:0]clkarray4;
wire [31:0]clkarray5;

//decide what tone to play
always @(statevalue, clkarray0, clkarray1, clkarray2, clkarray3, clkarray4, clkarray5)
begin
	if (statevalue == 0)				//Dflat
		speaker = clkarray0[15];	
	else if (statevalue == 1)		//E
		speaker = clkarray1[15];
	else if (statevalue == 2)		//Gflat
		speaker = clkarray2[15];
	else if (statevalue == 3)		//G
		speaker = clkarray3[15];
	else if (statevalue == 4)		//Aflat
		speaker = clkarray4[15];
	else if (statevalue == 5)		//B
		speaker = clkarray5[15];
	else if (statevalue == 6)		//Dflat
		speaker = clkarray0[14];
	else if (statevalue == 7)		//E
		speaker = clkarray1[14];
	else if (statevalue == 8)		//Gflat also not used
		speaker = clkarray2[14];
	else
		speaker = 0;					//defaults to speaker off
end

//function calls
clockschemearray clkarrayinstance1(rawclk, clkarray0, clkarray1, clkarray2, clkarray3, clkarray4, clkarray5);

endmodule

 /*
  ##############################################################################################################
 This module counts upwards
 */
 module upcounter32(ww, Qq);
 
 parameter n = 32;		//number of registers in the counter
 input ww;					//the input that will be counted
 output reg [n-1:0]Qq;	//an array with each being a signal with half the frequency of the last signal
 
 always@(posedge ww)
 begin
 Qq <= Qq + 1;
 end 
 endmodule

 /*
  ##############################################################################################################
 keyboard using the keys on the expansion board
 takes in an input from an 8 key keyboard and returns the value of the highest pressed key in binary
 defaults to high
 */
 module keyboard(key, out);
 input [7:0]key;
 output reg [3:0]out;
 
 always@(key)
 begin
	casex(key)
		8'b1xxxxxxx: out = 4'b0000;  //Dflat
		8'b01xxxxxx: out = 4'b0001;  //E
		8'b001xxxxx: out = 4'b0010;  //G flat
		8'b0001xxxx: out = 4'b0011;  //g
		8'b00001xxx: out = 4'b0100;  //A flat
		8'b000001xx: out = 4'b0101;  //b
		8'b0000001x: out = 4'b0110;  //dflat up
		8'b00000001: out = 4'b0111;  //E     up
		default : 	 out = 4'b1111;
	endcase
 end
 endmodule
 
 /*
 ##############################################################################################################
 displays which notes are currently being played
 This module takes in a binary signal that represents notes and outputs two se
 */
 module sevsegdisplaynote(out1, out2, note);
 input [3:0]note;
 output reg [6:0]out1;  //note letter i.e.(b, c, d, e)
 output reg [6:0]out2;  //accidental i.e. (b)
 
 always@(note)
 begin
	case(note)
		4'b0000: begin
					out1 = 7'b0000001; // Dflat
					out2 = 7'b1100000;
					end
		4'b0001: begin
					out1 = 7'b0110000; //E
					out2 = 7'b1111111;
					end
		4'b0010: begin
					out1 = 7'b0100001; //G flat
					out2 = 7'b1100000;
					end
		4'b0011: begin
					out1 = 7'b0100001; //G
					out2 = 7'b1111111;
					end
		4'b0100: begin
					out1 = 7'b0001000; //A flat
					out2 = 7'b1100000;
					end
		4'b0101: begin
					out1 = 7'b0000000; //B
					out2 = 7'b1111111;
					end
		4'b0110: begin
					out1 = 7'b0000001; // Dflat
					out2 = 7'b1100000;
					end
		4'b0111: begin
					out1 = 7'b0110000; //E
					out2 = 7'b1111111;
					end
		default  begin
				   out1 = 7'b1111111; //all on for debugging
				   out2 = 7'b1111111;
					end
	endcase
end
endmodule