LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use ieee.std_logic_unsigned.all;

ENTITY nlc_tb IS
END nlc_tb;
 
ARCHITECTURE behavior OF nlc_tb IS 
 
    COMPONENT nolightcounter
    PORT(
         CLK : IN  std_logic;
         RST : IN  std_logic;
         NLC_EN : IN  std_logic;
         CAHAYA : IN  std_logic_vector(9 downto 0);
         ROTATE : OUT  std_logic
        );
    END COMPONENT;
    

   --Inputs
   signal CLK : std_logic := '0';
   signal RST : std_logic := '0';
   signal NLC_EN : std_logic := '0';
   signal CAHAYA : std_logic_vector(9 downto 0) := "0000000000";

 	--Outputs
   signal ROTATE : std_logic;

 
BEGIN
 
	-- Instantiate the Unit Under Test (UUT)
   uut: nolightcounter PORT MAP (
          CLK => CLK,
          RST => RST,
          NLC_EN => NLC_EN,
          CAHAYA => CAHAYA,
          ROTATE => ROTATE
        );
 

   -- Stimulus process CLK
   stim_procrclk: process
   begin		
		wait for 1 ns;
		CLK <= not CLK;
   end process;

   -- Stimulus process RST
   stim_procrst: process
   begin		
		wait for 10 ns;
		RST <= '1';
		wait for 10 ns;
		RST <= '0';
		wait;
   end process;
	
	-- Stimulus process NLC_EN
   stim_procnlcen: process
   begin		
		wait for 10 ns;
		NLC_EN <= '0';
		wait for 10 ns;
		NLC_EN <= '1';
		wait;
   end process;
	
	stim_procchy: process
   begin		
		wait for 50 ns;
		CAHAYA <= CAHAYA + 1;
   end process;
	
END;