/***********
 * Functions for working with the block rams present in Oscope design
 * GPIO #1 : Trigger Buffer read/write
 * 	Channel 1 = 12 bits wide, output
 * 		Bits 11 = RST
 * 		Bits 10:0 = Trigger Buffer BRAM Read Address
 *  Channel 2 = 24 bits wide, input
 *		Bits 23 = Done
 *		Bits 22:12 = Circular Buffer's Starting Address
 *		Bits 11:0 = Trigger Buffer BRAM Data Out
 *
 *
 * GPIO #2 : Trigger Settings
 *  23 Bits Wide, Output
 *  	Bits 22:11 = trigger threshold
 *  	Bits 10:0 = subsample count (every x sample is used)
 *
 * GPIO #3 : Screen Buffer
 *  Channel 1 = 22 bit wide, output
 *  	Bits 21 = BRAM Write Enable
 *  	Bits 20:18 = BRAM Data In
 *  	Bits 17:0 = BRAM Address (row : column)
 *  Channel 2 = 1 bit wide, input
 *  	Bits 1 = Write ACK
 *
 * GPIO #4 : Encoder
 *  Channel 1 = 20 bit wide,  input
 *  	Bits 19 = 	Button2
 *  	Bits 18 = 	Button1
 *  	Bits 17:12 = Encoder 3 count
 *  	Bits 11:6 = Encoder 2 count
 *  	Bits 5:0 = Encoder 1 count
 *
 */

#include "mem_control.h"
#include "xgpio.h"
#include "FreeRTOS.h"
#include "task.h"

static u16 trig_buff_reg_out = 0;
static u32 trig_buff_settings_out = 0;


static XGpio gpio_trig_read;
static XGpio gpio_trig_buff_settings;
static XGpio gpio_screen_buff;
static XGpio gpio_encoder;

void initialize_trigger_buff_gpio( void )
{
	XGpio_Config *ConfigPtr;
	BaseType_t xStatus;

	// Initialise the GPIO driver.
	ConfigPtr = XGpio_LookupConfig( XPAR_GPIO_TRIGGER_CONTROL_DEVICE_ID );
	xStatus = XGpio_CfgInitialize( &gpio_trig_read, ConfigPtr, ConfigPtr->BaseAddress );
	configASSERT( xStatus == XST_SUCCESS );
	( void ) xStatus; // Remove compiler warning if configASSERT() is not defined.

	// Channel 1 is a 12 bit wide output channel
	XGpio_SetDataDirection(&gpio_trig_read, CH_TRIG_BUF_OUT, DIRECTION_OUTPUT);
	// Channel 2 is a 24 bit wide input channel
	XGpio_SetDataDirection(&gpio_trig_read, CH_TRIG_BUF_IN, DIRECTION_INPUT);
}

void initialize_trigger_buff_settings_gpio( void )
{
	XGpio_Config *ConfigPtr;
	BaseType_t xStatus;

	// Initialise the GPIO driver.
	ConfigPtr = XGpio_LookupConfig( XPAR_GPIO_TRIGGER_SETTINGS_DEVICE_ID );
	xStatus = XGpio_CfgInitialize( &gpio_trig_buff_settings, ConfigPtr, ConfigPtr->BaseAddress );
	configASSERT( xStatus == XST_SUCCESS );
	( void ) xStatus; // Remove compiler warning if configASSERT() is not defined.

	// Channel 1 is a 12 bit wide output channel
	XGpio_SetDataDirection(&gpio_trig_read, CH_TRIG_SETTINGS_OUT , DIRECTION_OUTPUT);
}

void initialize_screen_buffer_gpio( void )
{
	XGpio_Config *ConfigPtr;
	BaseType_t xStatus;

	// Initialise the GPIO driver.
	ConfigPtr = XGpio_LookupConfig( XPAR_SCREEN_BUFFER_GPIO_DEVICE_ID );
	xStatus = XGpio_CfgInitialize( &gpio_screen_buff, ConfigPtr, ConfigPtr->BaseAddress );
	configASSERT( xStatus == XST_SUCCESS );
	( void ) xStatus; // Remove compiler warning if configASSERT() is not defined.

	// Channel 1 is a 22 bit wide output channel
	XGpio_SetDataDirection(&gpio_screen_buff, CH_SCREEN_BUF_OUT, DIRECTION_OUTPUT);
	// Channel 2 is a 1 bit wide input channel
	XGpio_SetDataDirection(&gpio_screen_buff, CH_SCREEN_BUF_IN, DIRECTION_INPUT);
}

int16_t read_trigger_buff( uint16_t address )
{
	static long trig_buff_reg_in = 0;

	// Clear bottom 11 bits of trigger buffer output reg
	trig_buff_reg_out = trig_buff_reg_out & 0b100000000000;

	// Put address value on trigger buffer output reg
	trig_buff_reg_out = trig_buff_reg_out | address;

	// Write address to read channel of BRAM
	XGpio_DiscreteWrite(&gpio_trig_read, CH_TRIG_BUF_OUT, trig_buff_reg_out);

	// Read values output by BRAM
	trig_buff_reg_in = XGpio_DiscreteRead(&gpio_trig_read, CH_TRIG_BUF_IN);

	// Clear bottom 11 bits of trigger buffer output reg
	trig_buff_reg_out = trig_buff_reg_out & 0b100000000000;

	// Return bottom 12 bits of read trigger buffer
	return (trig_buff_reg_in & 0x000FFF);
}

int16_t check_trigger_status( void )
{
	static long trig_buff_reg_in = 0;

	// Read Buffer Control Input Register
	trig_buff_reg_in = XGpio_DiscreteRead(&gpio_trig_read, CH_TRIG_BUF_IN);

	if (trig_buff_reg_in & 0x800000) // View bit 23 = Done
		return 1;					 // Return 1 if done
	else
		return 0;
}

//  	Bits 22:11 of buff_settings_out = trigger threshold
void set_trigger_level( int16_t trigger_level )
{
	trig_buff_settings_out = (trig_buff_settings_out & 0x000007FF);	// Set trigger threshold to 0
	trig_buff_settings_out = trig_buff_settings_out | (trigger_level<<11);	// Set trigger threshold to trigger level

	XGpio_DiscreteWrite(&gpio_trig_buff_settings, CH_TRIG_BUF_OUT, trig_buff_settings_out); // Write settings to hardware

}

//  	Bits 10:0 of buff_settings_out = subsample counter
void set_subsample_counter( int16_t subsample_counter )
{
	trig_buff_settings_out = (trig_buff_settings_out & 0x007FF800);			// Set subsample counter to 0
	trig_buff_settings_out = trig_buff_settings_out | (subsample_counter);	// Load subsample counter

	XGpio_DiscreteWrite(&gpio_trig_buff_settings, CH_TRIG_BUF_OUT, trig_buff_settings_out); // Write settings to hardware

}

//		Bits 22:12 = Circular Buffer's Starting Address
int16_t read_trigger_buff_addr( void )
{
	static long trig_buff_reg_in = 0;

	// Read Buffer Control Input Register
	trig_buff_reg_in = XGpio_DiscreteRead(&gpio_trig_read, CH_TRIG_BUF_IN);

	return ( ((trig_buff_reg_in & 0x7FF000)>>12) + 1); // Return bits 22:12
		// Add 1 to it because the value read is actually the last address that was written to
		// Need to add one to overflow over to the first address written to

}

// 		Bits 11 = RST
void write_trigger_rst( uint16_t bit )
{
	trig_buff_reg_out = ( trig_buff_reg_out & 0xF7FF );						// Set RST to 0
	trig_buff_reg_out = ( trig_buff_reg_out | (bit << 11) );					// Load bit into RST bit

	XGpio_DiscreteWrite(&gpio_trig_read, CH_TRIG_BUF_OUT, trig_buff_reg_out);
}

void writePixel( uint16_t row, uint16_t column, uint16_t value )
{
	long datapacket = 0;

	// Concatenate Row, Column, and Value together to create the full data packet
	datapacket = (1<<21) + (value<<18) + (row<<9) + column;
	// Send Data packet with EN signal
	XGpio_DiscreteWrite(&gpio_screen_buff, CH_SCREEN_BUF_OUT, datapacket);
	// Read ACK bit. If ACK is not high, keep reading it
	while( !(XGpio_DiscreteRead(&gpio_screen_buff, CH_SCREEN_BUF_IN)) );
	// Now that ACK is high, transmission is complete, reset GPIO to all zeros
	XGpio_DiscreteWrite(&gpio_screen_buff, CH_SCREEN_BUF_OUT, 0);

}

void initialize_encoder_gpio( void )
{
	XGpio_Config *ConfigPtr;
	BaseType_t xStatus;

	// Initialise the GPIO driver.
	ConfigPtr = XGpio_LookupConfig( XPAR_ENCODER_BTN_GPIO_DEVICE_ID );
	xStatus = XGpio_CfgInitialize( &gpio_encoder, ConfigPtr, ConfigPtr->BaseAddress );
	configASSERT( xStatus == XST_SUCCESS );
	( void ) xStatus; // Remove compiler warning if configASSERT() is not defined.

	// Channel 1 is a 20 bit wide input channel
	XGpio_SetDataDirection(&gpio_encoder, CH_ENCODER_IN, DIRECTION_INPUT);
	// Channel 2 is a 3 bit wide output channel
	XGpio_SetDataDirection(&gpio_encoder, CH_ENCODER_OUT, DIRECTION_OUTPUT);
}

u32 read_encoder_values( void )
{
	return XGpio_DiscreteRead(&gpio_encoder, CH_ENCODER_IN);
}


void reset_encoders( void )
{
	XGpio_DiscreteWrite(&gpio_encoder, CH_ENCODER_OUT, 0xFFFF);
	XGpio_DiscreteWrite(&gpio_encoder, CH_ENCODER_OUT, 0x0000);
}