#include <msp430.h> 

/*
 * main.c
 */
void func()
{
	//int i;
	//for(i=0;i<20;i++)
	_delay_cycles(700);
}
void clock_delay()
{
	_delay_cycles(1000);
}

int main(void) {

	short arr[6][9] =
/*	{
	{1,0,1,0,0,0,0,1,0,0,1,1,1,1,1},
	{1,0,1,0,0,0,0,1,0,0,0,0,1,0,0},
	{1,0,1,1,1,1,1,1,0,0,0,0,1,0,0},
	{1,0,1,0,0,0,0,1,0,0,0,0,1,0,0},
	{1,0,1,0,0,0,0,1,0,0,0,0,1,0,0},
	{1,0,1,0,0,0,0,1,0,0,1,1,1,1,1}};
*/
	{
	{1,0,0,0,0,1,0,0,1},
	{1,0,0,0,0,1,0,0,1},
	{1,1,1,1,1,1,0,0,1},
	{1,0,0,0,0,1,0,0,1},
	{1,0,0,0,0,1,0,0,1},
	{1,0,0,0,0,1,0,0,1}};

	WDTCTL = WDTPW | WDTHOLD;	// Stop watchdog timer
	int i=0,j;



    /* USER CODE START (section: BCSplus_graceInit_prologue) */
    /* User initialization code */
    /* USER CODE END (section: BCSplus_graceInit_prologue) */

    /*
     * Basic Clock System Control 2
     *
     * SELM_0 -- DCOCLK
     * DIVM_0 -- Divide by 1
     * ~SELS -- DCOCLK
     * DIVS_0 -- Divide by 1
     * ~DCOR -- DCO uses internal resistor
     *
     * Note: ~<BIT> indicates that <BIT> has value zero
     */
    BCSCTL2 = SELM_0 + DIVM_0 + DIVS_0;

    /* Follow recommended flow. First, clear all DCOx and MODx bits. Then
     * apply new RSELx values. Finally, apply new DCOx and MODx bit values.
     */
    DCOCTL = 0x00;

    /* Adjust this accordingly to your VCC rise time */
    __delay_cycles(100000);

    /*
     * DCO Clock Frequency Control
     *
     * ~MOD0 -- Disable MOD0 bit
     * ~MOD1 -- Disable MOD1 bit
     * MOD2 -- Enable MOD2 bit
     * ~MOD3 -- Disable MOD3 bit
     * MOD4 -- Enable MOD4 bit
     * DCO0 -- Enable DCO0 bit
     * DCO1 -- Enable DCO1 bit
     * ~DCO2 -- Disable DCO2 bit
     *
     * Note: ~<BIT> indicates that <BIT> has value zero
     */
    DCOCTL = MOD2 + MOD4 + DCO0 + DCO1;

    /*
     * Basic Clock System Control 1
     *
     * XT2OFF -- Disable XT2CLK
     * ~XTS -- Low Frequency
     * DIVA_0 -- Divide by 1
     * RSEL0 -- Enable RSEL0 bit
     * RSEL1 -- Enable RSEL1 bit
     * RSEL2 -- Enable RSEL2 bit
     * RSEL3 -- Enable RSEL3 bit
     *
     * Note: ~XTS indicates that XTS has value zero
     */
    BCSCTL1 = XT2OFF + DIVA_0 + RSEL0 + RSEL1 + RSEL2 + RSEL3;

    /*
     * Basic Clock System Control 3
     *
     * XT2S_0 -- 0.4 - 1 MHz
     * LFXT1S_0 -- If XTS = 0, XT1 = 32768kHz Crystal ; If XTS = 1, XT1 = 0.4 - 1-MHz crystal or resonator
     * XCAP_1 -- ~6 pF
     */
    BCSCTL3 = XT2S_0 + LFXT1S_0 + XCAP_1;

    /* USER CODE START (section: BCSplus_graceInit_epilogue) */
    /* User code */
    /* USER CODE END (section: BCSplus_graceInit_epilogue) */

	P1DIR |= 0xff;                            	// Set P1.0 to output direction
/*	i=0;
	while(1)
	{
		P1OUT=i;
		P1OUT |= BIT3;
		func();
		i=(i+1)%6;
	}
*/
/*	for(i=0;;i=(i+1)%6)
	{
		P1OUT=i;
		for(j=0;j<7;j++)
		{
			if(arr[i][j])	P1OUT |= BIT3;
			else			P1OUT &= ~BIT3;
			clock_delay();
		}
	}
*/
/*	i=0;j=0;
	while(1)
	{
		if(arr[i][j]) P1OUT|=BIT3;
		else		P1OUT&=~BIT3;
		func();
		j++;
		if(j==6)
		{
			P1OUT=i;
			i=(i+1)%6;
			j=0;
		}
	}
*/
	int k;
for(i=0;;i=(i+1)%6)
{
	P1OUT=i;
	for(j=0;j<10;j++)
	{
		for(k=0;k<20;k++)
		{
			if(k<9)
			{
						if(arr[i][k]) P1OUT|=BIT3;
						else		P1OUT&=~BIT3;
			}
			func();
			P1OUT&=~BIT3;
		}
	//	func();
	//	func();
	}
}


}