UART Protocol Data Transfer Basic Diagram

Note: The receiver monitors the data wire constantly for digital level change, High or Low
1- The transmitter holds the data wire high indicating standby mode, receiver is idle
2- The transmitter pulls the data wire low indicating a START of data transfer to the receiver
The falling edge on the data wire alerts the receiver to sample the data line for a valid (Start) LOW state. NOTICE: The receiver clock pulse samples the bit at an average point in time along the length of the data pulse, not too close to the rising or falling edge of the data pulse. (Basically around the middle of the data pulse). This occurs so false data is not received. With this method the data is considered valid by the receiver. 
3- Once the start bit is verified by the receiver the clock samples the data wire at the selected baud rate and based on receiver configuration that eight data bits will be sent along with one stop bit.
Note: At this time, do not over-think how the receiver clock performs valid reads. There are numerous articles detailing how data is read by the receiver but the intent at this time is to write code to transmit data and not receive data. The TX logic will simplify with further explanation. 
The following is the guide used to hard code the PIC in simple terms 
1- Numerous UART resources refer to the TX Data transfer clocking at the same baud rate as the receiver clock. This is relevent and not to be disputed but the TX and RX clocks are not synchronized to one another so they run  independent of each other. Hence: UART (Universal Asyschronous Receiver Transmitter). This configuration makes the UART one of the easier protocols to design around. 
The code presented in this exercise is designed to simplify the TX transfer without designing a TX internal clock in the code. Based on previous explanation of the TX data bit being maintained for the receiver clock pulse to receive a valid read a simple delay (duration) timer in the code will time the data transfer from the PIC to the receiver. 
Question: What is the PIC duration (delay) timer programed for? 
2- With the receiver set for 2400 baud in this exercise: this equates to: 1/2400  = .416 mili seconds per bit. Meaning the receiver clocks a data bit every .416 mili seconds or 2400 bits per second. Based of theory the 2400 bps works on paper so this is close enough to program the PIC duration timer.
3- The PIC duration (delay) timer will be intially set for .416 mili-seconds and require some tweeking to compensate for instruction execution time and other peripherals. Because the receiver clock expects the next data bit to be valid and has now way to synchronize with the PIC TX the delay will be offset from .416 mili-seconds to find a medium. From research it is found the TX and RX timing can be within 10% of each other, so there is room for error.