
rf12tx.elf:     file format elf32-avr

Sections:
Idx Name          Size      VMA       LMA       File off  Algn
  0 .text         000004a0  00000000  00000000  00000094  2**1
                  CONTENTS, ALLOC, LOAD, READONLY, CODE
  1 .data         00000000  00800060  000004a0  00000534  2**0
                  CONTENTS, ALLOC, LOAD, DATA
  2 .bss          00000045  00800060  00800060  00000534  2**0
                  ALLOC
  3 .comment      00000030  00000000  00000000  00000534  2**0
                  CONTENTS, READONLY
  4 .debug_aranges 00000150  00000000  00000000  00000564  2**0
                  CONTENTS, READONLY, DEBUGGING
  5 .debug_info   00001137  00000000  00000000  000006b4  2**0
                  CONTENTS, READONLY, DEBUGGING
  6 .debug_abbrev 000005cc  00000000  00000000  000017eb  2**0
                  CONTENTS, READONLY, DEBUGGING
  7 .debug_line   00000750  00000000  00000000  00001db7  2**0
                  CONTENTS, READONLY, DEBUGGING
  8 .debug_frame  00000308  00000000  00000000  00002508  2**2
                  CONTENTS, READONLY, DEBUGGING
  9 .debug_str    000003db  00000000  00000000  00002810  2**0
                  CONTENTS, READONLY, DEBUGGING
 10 .debug_loc    00000995  00000000  00000000  00002beb  2**0
                  CONTENTS, READONLY, DEBUGGING
 11 .debug_ranges 00000128  00000000  00000000  00003580  2**0
                  CONTENTS, READONLY, DEBUGGING

Disassembly of section .text:

00000000 <__vectors>:
   0:	23 c0       	rjmp	.+70     	; 0x48 <__ctors_end>
   2:	eb c0       	rjmp	.+470    	; 0x1da <__vector_1>
   4:	31 c0       	rjmp	.+98     	; 0x68 <__bad_interrupt>
   6:	30 c0       	rjmp	.+96     	; 0x68 <__bad_interrupt>
   8:	2f c0       	rjmp	.+94     	; 0x68 <__bad_interrupt>
   a:	2e c0       	rjmp	.+92     	; 0x68 <__bad_interrupt>
   c:	2d c0       	rjmp	.+90     	; 0x68 <__bad_interrupt>
   e:	2c c0       	rjmp	.+88     	; 0x68 <__bad_interrupt>
  10:	2b c0       	rjmp	.+86     	; 0x68 <__bad_interrupt>
  12:	2a c0       	rjmp	.+84     	; 0x68 <__bad_interrupt>
  14:	29 c0       	rjmp	.+82     	; 0x68 <__bad_interrupt>
  16:	be c1       	rjmp	.+892    	; 0x394 <__vector_11>
  18:	e6 c1       	rjmp	.+972    	; 0x3e6 <__vector_12>
  1a:	26 c0       	rjmp	.+76     	; 0x68 <__bad_interrupt>
  1c:	25 c0       	rjmp	.+74     	; 0x68 <__bad_interrupt>
  1e:	24 c0       	rjmp	.+72     	; 0x68 <__bad_interrupt>
  20:	23 c0       	rjmp	.+70     	; 0x68 <__bad_interrupt>
  22:	22 c0       	rjmp	.+68     	; 0x68 <__bad_interrupt>
  24:	21 c0       	rjmp	.+66     	; 0x68 <__bad_interrupt>

00000026 <__trampolines_end>:
  26:	49 32       	cpi	r20, 0x29	; 41
  28:	63 20       	and	r6, r3
  2a:	54 65       	ori	r21, 0x54	; 84
  2c:	6d 70       	andi	r22, 0x0D	; 13
  2e:	20 72       	andi	r18, 0x20	; 32
  30:	65 61       	ori	r22, 0x15	; 21
  32:	64 21       	and	r22, r4
  34:	0a 00       	.word	0x000a	; ????

00000036 <__c.2020>:
  36:	41 74 6d 65 67 61 20 6c 61 65 75 66 74 20 21 0a     Atmega laeuft !.
	...

00000048 <__ctors_end>:
  48:	11 24       	eor	r1, r1
  4a:	1f be       	out	0x3f, r1	; 63
  4c:	cf e5       	ldi	r28, 0x5F	; 95
  4e:	d4 e0       	ldi	r29, 0x04	; 4
  50:	de bf       	out	0x3e, r29	; 62
  52:	cd bf       	out	0x3d, r28	; 61

00000054 <__do_clear_bss>:
  54:	20 e0       	ldi	r18, 0x00	; 0
  56:	a0 e6       	ldi	r26, 0x60	; 96
  58:	b0 e0       	ldi	r27, 0x00	; 0
  5a:	01 c0       	rjmp	.+2      	; 0x5e <.do_clear_bss_start>

0000005c <.do_clear_bss_loop>:
  5c:	1d 92       	st	X+, r1

0000005e <.do_clear_bss_start>:
  5e:	a5 3a       	cpi	r26, 0xA5	; 165
  60:	b2 07       	cpc	r27, r18
  62:	e1 f7       	brne	.-8      	; 0x5c <.do_clear_bss_loop>
  64:	e7 d0       	rcall	.+462    	; 0x234 <main>
  66:	1a c2       	rjmp	.+1076   	; 0x49c <_exit>

00000068 <__bad_interrupt>:
  68:	cb cf       	rjmp	.-106    	; 0x0 <__vectors>

0000006a <rf12_trans>:
#include <util/delay.h>

unsigned short rf12_trans(unsigned short wert)
{	unsigned char i;

	cbi(RF_PORT, CS);
  6a:	c2 98       	cbi	0x18, 2	; 24
  6c:	20 e1       	ldi	r18, 0x10	; 16
	for (i=0; i<16; i++)
	{	if (wert&32768)
  6e:	99 23       	and	r25, r25
  70:	14 f4       	brge	.+4      	; 0x76 <rf12_trans+0xc>
			sbi(RF_PORT, SDI);
  72:	c3 9a       	sbi	0x18, 3	; 24
  74:	01 c0       	rjmp	.+2      	; 0x78 <rf12_trans+0xe>
		else
			cbi(RF_PORT, SDI);
  76:	c3 98       	cbi	0x18, 3	; 24
		wert<<=1;
  78:	88 0f       	add	r24, r24
  7a:	99 1f       	adc	r25, r25
		if (RF_PIN&(1<<SDO))
  7c:	b4 99       	sbic	0x16, 4	; 22
			wert|=1;
  7e:	81 60       	ori	r24, 0x01	; 1
		sbi(RF_PORT, SCK);
  80:	c5 9a       	sbi	0x18, 5	; 24
		asm("nop");
  82:	00 00       	nop
		asm("nop");
  84:	00 00       	nop
		cbi(RF_PORT, SCK);
  86:	c5 98       	cbi	0x18, 5	; 24
  88:	21 50       	subi	r18, 0x01	; 1

unsigned short rf12_trans(unsigned short wert)
{	unsigned char i;

	cbi(RF_PORT, CS);
	for (i=0; i<16; i++)
  8a:	89 f7       	brne	.-30     	; 0x6e <rf12_trans+0x4>
		sbi(RF_PORT, SCK);
		asm("nop");
		asm("nop");
		cbi(RF_PORT, SCK);
	}
	sbi(RF_PORT, CS);
  8c:	c2 9a       	sbi	0x18, 2	; 24
	return wert;
}
  8e:	08 95       	ret

00000090 <rf12_init>:

void rf12_init(void)
{
	RF_DDR=(1<<SDI)|(1<<SCK)|(1<<CS);
  90:	8c e2       	ldi	r24, 0x2C	; 44
  92:	87 bb       	out	0x17, r24	; 23
	RF_PORT=(1<<CS);
  94:	84 e0       	ldi	r24, 0x04	; 4
  96:	88 bb       	out	0x18, r24	; 24
	DDRD = (1 << 5) | (1 << 6) | (1 << 7);
  98:	80 ee       	ldi	r24, 0xE0	; 224
  9a:	81 bb       	out	0x11, r24	; 17
  9c:	8a ef       	ldi	r24, 0xFA	; 250
	#else
		//round up by default
		__ticks_dc = (uint32_t)(ceil(fabs(__tmp)));
	#endif

	__builtin_avr_delay_cycles(__ticks_dc);
  9e:	ef e1       	ldi	r30, 0x1F	; 31
  a0:	fe e4       	ldi	r31, 0x4E	; 78
  a2:	31 97       	sbiw	r30, 0x01	; 1
  a4:	f1 f7       	brne	.-4      	; 0xa2 <rf12_init+0x12>
  a6:	00 c0       	rjmp	.+0      	; 0xa8 <rf12_init+0x18>
  a8:	00 00       	nop
  aa:	81 50       	subi	r24, 0x01	; 1
	for (unsigned char i=0; i<250; i++)
  ac:	c1 f7       	brne	.-16     	; 0x9e <rf12_init+0xe>
		_delay_ms(10);			// wait until POR done
	rf12_trans(0xC0E0);			// AVR CLK: 10MHz
  ae:	80 ee       	ldi	r24, 0xE0	; 224
  b0:	90 ec       	ldi	r25, 0xC0	; 192
  b2:	db df       	rcall	.-74     	; 0x6a <rf12_trans>
	rf12_trans(0x80D7);			// Enable FIFO
  b4:	87 ed       	ldi	r24, 0xD7	; 215
  b6:	90 e8       	ldi	r25, 0x80	; 128
  b8:	d8 df       	rcall	.-80     	; 0x6a <rf12_trans>
	rf12_trans(0xC2AB);			// Data Filter: internal
  ba:	8b ea       	ldi	r24, 0xAB	; 171
  bc:	92 ec       	ldi	r25, 0xC2	; 194
  be:	d5 df       	rcall	.-86     	; 0x6a <rf12_trans>
	rf12_trans(0xCA81);			// Set FIFO mode
  c0:	81 e8       	ldi	r24, 0x81	; 129
  c2:	9a ec       	ldi	r25, 0xCA	; 202
  c4:	d2 df       	rcall	.-92     	; 0x6a <rf12_trans>
	rf12_trans(0xE810);			// wakeuptimer ca 15s
  c6:	80 e1       	ldi	r24, 0x10	; 16
  c8:	98 ee       	ldi	r25, 0xE8	; 232
  ca:	cf df       	rcall	.-98     	; 0x6a <rf12_trans>
	rf12_trans(0xC800);			// disable low duty cycle
  cc:	80 e0       	ldi	r24, 0x00	; 0
  ce:	98 ec       	ldi	r25, 0xC8	; 200
  d0:	cc df       	rcall	.-104    	; 0x6a <rf12_trans>
	rf12_trans(0xC4F7);			// AFC settings: autotuning: -10kHz...+7,5kHz
  d2:	87 ef       	ldi	r24, 0xF7	; 247
  d4:	94 ec       	ldi	r25, 0xC4	; 196
  d6:	c9 df       	rcall	.-110    	; 0x6a <rf12_trans>
  d8:	08 95       	ret

000000da <rf12_setbandwidth>:
}

void rf12_setbandwidth(unsigned char bandwidth, unsigned char gain, unsigned char drssi)
{
	rf12_trans(0x9400|((bandwidth&7)<<5)|((gain&3)<<3)|(drssi&7));
  da:	47 70       	andi	r20, 0x07	; 7
  dc:	50 e0       	ldi	r21, 0x00	; 0
  de:	54 69       	ori	r21, 0x94	; 148
  e0:	63 70       	andi	r22, 0x03	; 3
  e2:	26 2f       	mov	r18, r22
  e4:	30 e0       	ldi	r19, 0x00	; 0
  e6:	22 0f       	add	r18, r18
  e8:	33 1f       	adc	r19, r19
  ea:	22 0f       	add	r18, r18
  ec:	33 1f       	adc	r19, r19
  ee:	22 0f       	add	r18, r18
  f0:	33 1f       	adc	r19, r19
  f2:	42 2b       	or	r20, r18
  f4:	53 2b       	or	r21, r19
  f6:	20 e2       	ldi	r18, 0x20	; 32
  f8:	82 9f       	mul	r24, r18
  fa:	c0 01       	movw	r24, r0
  fc:	11 24       	eor	r1, r1
  fe:	99 27       	eor	r25, r25
 100:	84 2b       	or	r24, r20
 102:	95 2b       	or	r25, r21
 104:	b2 df       	rcall	.-156    	; 0x6a <rf12_trans>
 106:	08 95       	ret

00000108 <rf12_setfreq>:
}

void rf12_setfreq(unsigned short freq)
{	if (freq<96)				// 430,2400MHz
 108:	80 36       	cpi	r24, 0x60	; 96
 10a:	91 05       	cpc	r25, r1
 10c:	38 f0       	brcs	.+14     	; 0x11c <rf12_setfreq+0x14>
 10e:	80 34       	cpi	r24, 0x40	; 64
 110:	2f e0       	ldi	r18, 0x0F	; 15
 112:	92 07       	cpc	r25, r18
 114:	28 f0       	brcs	.+10     	; 0x120 <rf12_setfreq+0x18>
 116:	8f e3       	ldi	r24, 0x3F	; 63
 118:	9f e0       	ldi	r25, 0x0F	; 15
 11a:	02 c0       	rjmp	.+4      	; 0x120 <rf12_setfreq+0x18>
		freq=96;
 11c:	80 e6       	ldi	r24, 0x60	; 96
 11e:	90 e0       	ldi	r25, 0x00	; 0
	else if (freq>3903)			// 439,7575MHz
		freq=3903;
	rf12_trans(0xA000|freq);
 120:	90 6a       	ori	r25, 0xA0	; 160
 122:	a3 df       	rcall	.-186    	; 0x6a <rf12_trans>
 124:	08 95       	ret

00000126 <rf12_setbaud>:
		//baud=664;
	//if (baud<5400)					// Baudrate= 344827,58621/(R+1)/(1+CS*7)
		//rf12_trans(0xC680|((43104/baud)-1));	// R=(344828/8)/Baud-1
	//else
	//	rf12_trans(0xC600|((344828UL/baud)-1));	// R=344828/Baud-1
		rf12_trans(0xc647);
 126:	87 e4       	ldi	r24, 0x47	; 71
 128:	96 ec       	ldi	r25, 0xC6	; 198
 12a:	9f df       	rcall	.-194    	; 0x6a <rf12_trans>
 12c:	08 95       	ret

0000012e <rf12_setpower>:
}

void rf12_setpower(unsigned char power, unsigned char mod)
{	
	rf12_trans(0x9800|(power&7)|((mod&15)<<4));
 12e:	87 70       	andi	r24, 0x07	; 7
 130:	90 e0       	ldi	r25, 0x00	; 0
 132:	98 69       	ori	r25, 0x98	; 152
 134:	20 e1       	ldi	r18, 0x10	; 16
 136:	62 9f       	mul	r22, r18
 138:	b0 01       	movw	r22, r0
 13a:	11 24       	eor	r1, r1
 13c:	77 27       	eor	r23, r23
 13e:	86 2b       	or	r24, r22
 140:	97 2b       	or	r25, r23
 142:	93 df       	rcall	.-218    	; 0x6a <rf12_trans>
 144:	08 95       	ret

00000146 <rf12_ready>:
}

void rf12_ready(void)
{	cbi(RF_PORT, SDI);
 146:	c3 98       	cbi	0x18, 3	; 24
	cbi(RF_PORT, CS);
 148:	c2 98       	cbi	0x18, 2	; 24
	asm("nop");
 14a:	00 00       	nop
	while (!(RF_PIN&(1<<SDO))); // wait until FIFO ready
 14c:	b4 9b       	sbis	0x16, 4	; 22
 14e:	fe cf       	rjmp	.-4      	; 0x14c <rf12_ready+0x6>
}
 150:	08 95       	ret

00000152 <rf12_txdata>:

void rf12_txdata(unsigned char *data, unsigned char number)
{	unsigned char i;
 152:	ff 92       	push	r15
 154:	0f 93       	push	r16
 156:	1f 93       	push	r17
 158:	cf 93       	push	r28
 15a:	df 93       	push	r29
 15c:	f8 2e       	mov	r15, r24
 15e:	19 2f       	mov	r17, r25
 160:	06 2f       	mov	r16, r22
	rf12_trans(0x80D7);			// FIFO	
 162:	87 ed       	ldi	r24, 0xD7	; 215
 164:	90 e8       	ldi	r25, 0x80	; 128
 166:	81 df       	rcall	.-254    	; 0x6a <rf12_trans>
	
	rf12_trans(0x8238);			// TX on
 168:	88 e3       	ldi	r24, 0x38	; 56
 16a:	92 e8       	ldi	r25, 0x82	; 130
 16c:	7e df       	rcall	.-260    	; 0x6a <rf12_trans>
	rf12_ready();
 16e:	eb df       	rcall	.-42     	; 0x146 <rf12_ready>
	rf12_trans(0xB8AA);
 170:	8a ea       	ldi	r24, 0xAA	; 170
 172:	98 eb       	ldi	r25, 0xB8	; 184
 174:	7a df       	rcall	.-268    	; 0x6a <rf12_trans>
	rf12_ready();
 176:	e7 df       	rcall	.-50     	; 0x146 <rf12_ready>
	rf12_trans(0xB8AA);
 178:	8a ea       	ldi	r24, 0xAA	; 170
 17a:	98 eb       	ldi	r25, 0xB8	; 184
 17c:	76 df       	rcall	.-276    	; 0x6a <rf12_trans>
	rf12_ready();
 17e:	e3 df       	rcall	.-58     	; 0x146 <rf12_ready>
	rf12_trans(0xB8AA);
 180:	8a ea       	ldi	r24, 0xAA	; 170
 182:	98 eb       	ldi	r25, 0xB8	; 184
 184:	72 df       	rcall	.-284    	; 0x6a <rf12_trans>
	rf12_ready();
 186:	df df       	rcall	.-66     	; 0x146 <rf12_ready>
	rf12_trans(0xB82D);
 188:	8d e2       	ldi	r24, 0x2D	; 45
 18a:	98 eb       	ldi	r25, 0xB8	; 184
 18c:	6e df       	rcall	.-292    	; 0x6a <rf12_trans>
	rf12_ready();
 18e:	db df       	rcall	.-74     	; 0x146 <rf12_ready>
	rf12_trans(0xB8D4);
 190:	84 ed       	ldi	r24, 0xD4	; 212
 192:	98 eb       	ldi	r25, 0xB8	; 184
 194:	6a df       	rcall	.-300    	; 0x6a <rf12_trans>
	for (i=0; i<number; i++)
 196:	00 23       	and	r16, r16
 198:	59 f0       	breq	.+22     	; 0x1b0 <rf12_txdata+0x5e>
 19a:	cf 2d       	mov	r28, r15
 19c:	d1 2f       	mov	r29, r17
 19e:	10 e0       	ldi	r17, 0x00	; 0
	{		rf12_ready();
 1a0:	d2 df       	rcall	.-92     	; 0x146 <rf12_ready>
		rf12_trans(0xB800|(*data++));
 1a2:	89 91       	ld	r24, Y+
 1a4:	90 e0       	ldi	r25, 0x00	; 0
 1a6:	98 6b       	ori	r25, 0xB8	; 184
 1a8:	60 df       	rcall	.-320    	; 0x6a <rf12_trans>
	rf12_trans(0xB8AA);
	rf12_ready();
	rf12_trans(0xB82D);
	rf12_ready();
	rf12_trans(0xB8D4);
	for (i=0; i<number; i++)
 1aa:	1f 5f       	subi	r17, 0xFF	; 255
 1ac:	10 13       	cpse	r17, r16
 1ae:	f8 cf       	rjmp	.-16     	; 0x1a0 <rf12_txdata+0x4e>
	{		rf12_ready();
		rf12_trans(0xB800|(*data++));
	}
	rf12_ready();
 1b0:	ca df       	rcall	.-108    	; 0x146 <rf12_ready>
		rf12_trans(0xB800);			// dummy data
 1b2:	80 e0       	ldi	r24, 0x00	; 0
 1b4:	98 eb       	ldi	r25, 0xB8	; 184
 1b6:	59 df       	rcall	.-334    	; 0x6a <rf12_trans>
		rf12_ready();
 1b8:	c6 df       	rcall	.-116    	; 0x146 <rf12_ready>
		rf12_trans(0xB800);			// dummy data
 1ba:	80 e0       	ldi	r24, 0x00	; 0
 1bc:	98 eb       	ldi	r25, 0xB8	; 184
 1be:	55 df       	rcall	.-342    	; 0x6a <rf12_trans>
		rf12_ready();
 1c0:	c2 df       	rcall	.-124    	; 0x146 <rf12_ready>
	rf12_trans(0x8200);			// TX off 8208 alt --> For Enable Wake up Timer 820A and Clock on
 1c2:	80 e0       	ldi	r24, 0x00	; 0
 1c4:	92 e8       	ldi	r25, 0x82	; 130
 1c6:	51 df       	rcall	.-350    	; 0x6a <rf12_trans>
	
		rf12_trans(0x8017);			
 1c8:	87 e1       	ldi	r24, 0x17	; 23
 1ca:	90 e8       	ldi	r25, 0x80	; 128
 1cc:	4e df       	rcall	.-356    	; 0x6a <rf12_trans>

}
 1ce:	df 91       	pop	r29
 1d0:	cf 91       	pop	r28
 1d2:	1f 91       	pop	r17
 1d4:	0f 91       	pop	r16
 1d6:	ff 90       	pop	r15
 1d8:	08 95       	ret

000001da <__vector_1>:
// externer Interrupt INT0

// Die Interruptroutine kann leer sein, ABER sie muss existieren!
// Sonst springt der AVR nach dem Aufwachen zum Reset, weil kein sinnvoller
// Interruptvektor eingetragen ist!
ISR(INT0_vect) {
 1da:	1f 92       	push	r1
 1dc:	0f 92       	push	r0
 1de:	0f b6       	in	r0, 0x3f	; 63
 1e0:	0f 92       	push	r0
 1e2:	11 24       	eor	r1, r1
 1e4:	8f 93       	push	r24
	   TWCR &= ~((1 << TWSTO) | (1 << TWEN));
 1e6:	86 b7       	in	r24, 0x36	; 54
 1e8:	8b 7e       	andi	r24, 0xEB	; 235
 1ea:	86 bf       	out	0x36, r24	; 54
	   TWCR |= (1 << TWEN);
 1ec:	86 b7       	in	r24, 0x36	; 54
 1ee:	84 60       	ori	r24, 0x04	; 4
 1f0:	86 bf       	out	0x36, r24	; 54
}
 1f2:	8f 91       	pop	r24
 1f4:	0f 90       	pop	r0
 1f6:	0f be       	out	0x3f, r0	; 63
 1f8:	0f 90       	pop	r0
 1fa:	1f 90       	pop	r1
 1fc:	18 95       	reti

000001fe <send>:
	for (unsigned char i=0; i<10; i++)
	uart_putc(test[i]);
}

void send(unsigned char temp, unsigned char temphalf)
{	unsigned char test[5];
 1fe:	cf 93       	push	r28
 200:	df 93       	push	r29
 202:	00 d0       	rcall	.+0      	; 0x204 <send+0x6>
 204:	00 d0       	rcall	.+0      	; 0x206 <send+0x8>
 206:	1f 92       	push	r1
 208:	cd b7       	in	r28, 0x3d	; 61
 20a:	de b7       	in	r29, 0x3e	; 62

	test[0]=temp;
 20c:	89 83       	std	Y+1, r24	; 0x01
	test[1]=temphalf;
 20e:	6a 83       	std	Y+2, r22	; 0x02
	test[2]=20;			//Reserve
 210:	84 e1       	ldi	r24, 0x14	; 20
 212:	8b 83       	std	Y+3, r24	; 0x03
	test[3]=30;			//Reserve
 214:	8e e1       	ldi	r24, 0x1E	; 30
 216:	8c 83       	std	Y+4, r24	; 0x04
	test[4]=40;			//Reserve
 218:	88 e2       	ldi	r24, 0x28	; 40
 21a:	8d 83       	std	Y+5, r24	; 0x05
	rf12_txdata(test,5);
 21c:	65 e0       	ldi	r22, 0x05	; 5
 21e:	ce 01       	movw	r24, r28
 220:	01 96       	adiw	r24, 0x01	; 1
 222:	97 df       	rcall	.-210    	; 0x152 <rf12_txdata>
}
 224:	0f 90       	pop	r0
 226:	0f 90       	pop	r0
 228:	0f 90       	pop	r0
 22a:	0f 90       	pop	r0
 22c:	0f 90       	pop	r0
 22e:	df 91       	pop	r29
 230:	cf 91       	pop	r28
 232:	08 95       	ret

00000234 <main>:

int main(void)
{

	//RFM
	rf12_init();					// ein paar Register setzen (z.B. CLK auf 10MHz)
 234:	2d df       	rcall	.-422    	; 0x90 <rf12_init>
	rf12_setfreq(RF12FREQ(433.92));	// Sende/Empfangsfrequenz auf 433,92MHz einstellen
 236:	80 e2       	ldi	r24, 0x20	; 32
 238:	96 e0       	ldi	r25, 0x06	; 6
 23a:	66 df       	rcall	.-308    	; 0x108 <rf12_setfreq>
	rf12_setbandwidth(4, 1, 4);		// 200kHz Bandbreite, -6dB Verstärkung, DRSSI threshold: -79dBm
 23c:	44 e0       	ldi	r20, 0x04	; 4
 23e:	61 e0       	ldi	r22, 0x01	; 1
 240:	84 e0       	ldi	r24, 0x04	; 4
 242:	4b df       	rcall	.-362    	; 0xda <rf12_setbandwidth>
	rf12_setbaud(19200);			// 19200 baud
 244:	80 e0       	ldi	r24, 0x00	; 0
 246:	9b e4       	ldi	r25, 0x4B	; 75
 248:	6e df       	rcall	.-292    	; 0x126 <rf12_setbaud>
	rf12_setpower(0, 6);			// 1mW Ausgangangsleistung, 120kHz Frequenzshift
 24a:	66 e0       	ldi	r22, 0x06	; 6
 24c:	80 e0       	ldi	r24, 0x00	; 0
 24e:	6f df       	rcall	.-290    	; 0x12e <rf12_setpower>
// 
// //DDRD |= (1<<PD6);	
// /	DDRC=0xff;

	// UART-Ausgabe
	 uart_init(UART_BAUD_SELECT(19200, F_CPU));
 250:	89 e1       	ldi	r24, 0x19	; 25
 252:	90 e0       	ldi	r25, 0x00	; 0
 254:	ed d0       	rcall	.+474    	; 0x430 <uart_init>
	 sei();
 256:	78 94       	sei
	 uart_puts_P("Atmega laeuft !\n");
 258:	86 e3       	ldi	r24, 0x36	; 54
 25a:	90 e0       	ldi	r25, 0x00	; 0
 25c:	0e d1       	rcall	.+540    	; 0x47a <uart_puts_p>

	//I²C
	DDRB |= (1<<1);   //PB1 auf Ausgang für Spannungsversorgung DS1621
 25e:	b9 9a       	sbi	0x17, 1	; 23
	unsigned char a[7];
	unsigned char b[7];
	a[0]=0;
	b[0]=0;
	//Initialisation for Sleep Mode
	DDRD &= ~(1<<PD2);		//INT0 als Eingang
 260:	8a 98       	cbi	0x11, 2	; 17
	PORTD |= (1<<PD2);//Pullup aktivieren für INT0
 262:	92 9a       	sbi	0x12, 2	; 18
	
	// Interrupt konfigurieren
	// level interrupt INT0 (low level)
	MCUCR &= ~((1 << ISC01) | (1 << ISC00));
 264:	85 b7       	in	r24, 0x35	; 53
 266:	8c 7f       	andi	r24, 0xFC	; 252
 268:	85 bf       	out	0x35, r24	; 53
	for (;;)
	{			
		float	calctemp=0.0;
		float	temp;
		float	temphalf;
		PORTB |= (1<<PB1);
 26a:	c1 9a       	sbi	0x18, 1	; 24
	#else
		//round up by default
		__ticks_dc = (uint32_t)(ceil(fabs(__tmp)));
	#endif

	__builtin_avr_delay_cycles(__ticks_dc);
 26c:	87 ec       	ldi	r24, 0xC7	; 199
 26e:	90 e0       	ldi	r25, 0x00	; 0
 270:	01 97       	sbiw	r24, 0x01	; 1
 272:	f1 f7       	brne	.-4      	; 0x270 <main+0x3c>
 274:	00 c0       	rjmp	.+0      	; 0x276 <main+0x42>
 276:	00 00       	nop
		_delay_us(100);
	//I²C 
	
		i2c_init();
 278:	4a d0       	rcall	.+148    	; 0x30e <i2c_init>
	#else
		//round up by default
		__ticks_dc = (uint32_t)(ceil(fabs(__tmp)));
	#endif

	__builtin_avr_delay_cycles(__ticks_dc);
 27a:	9f ef       	ldi	r25, 0xFF	; 255
 27c:	20 e7       	ldi	r18, 0x70	; 112
 27e:	82 e0       	ldi	r24, 0x02	; 2
 280:	91 50       	subi	r25, 0x01	; 1
 282:	20 40       	sbci	r18, 0x00	; 0
 284:	80 40       	sbci	r24, 0x00	; 0
 286:	e1 f7       	brne	.-8      	; 0x280 <main+0x4c>
 288:	00 c0       	rjmp	.+0      	; 0x28a <main+0x56>
 28a:	00 00       	nop
		
/*		uart_puts_P("I2c Init!\n");*/
		_delay_ms(100);
		i2c_start(Dev1621 + I2C_WRITE);	
 28c:	80 e9       	ldi	r24, 0x90	; 144
 28e:	43 d0       	rcall	.+134    	; 0x316 <i2c_start>
		uart_puts_P("I2c Temp read!\n");
 290:	86 e2       	ldi	r24, 0x26	; 38
 292:	90 e0       	ldi	r25, 0x00	; 0
 294:	f2 d0       	rcall	.+484    	; 0x47a <uart_puts_p>
		i2c_write(0xEE);
 296:	8e ee       	ldi	r24, 0xEE	; 238
 298:	62 d0       	rcall	.+196    	; 0x35e <i2c_write>
		i2c_stop();
 29a:	5b d0       	rcall	.+182    	; 0x352 <i2c_stop>
		i2c_start(Dev1621+I2C_WRITE);
 29c:	80 e9       	ldi	r24, 0x90	; 144
 29e:	3b d0       	rcall	.+118    	; 0x316 <i2c_start>
		i2c_write(0xAA);
 2a0:	8a ea       	ldi	r24, 0xAA	; 170
 2a2:	5d d0       	rcall	.+186    	; 0x35e <i2c_write>
		i2c_stop();
 2a4:	56 d0       	rcall	.+172    	; 0x352 <i2c_stop>
 2a6:	9f ef       	ldi	r25, 0xFF	; 255
 2a8:	26 e1       	ldi	r18, 0x16	; 22
 2aa:	81 e1       	ldi	r24, 0x11	; 17
 2ac:	91 50       	subi	r25, 0x01	; 1
 2ae:	20 40       	sbci	r18, 0x00	; 0
 2b0:	80 40       	sbci	r24, 0x00	; 0
 2b2:	e1 f7       	brne	.-8      	; 0x2ac <main+0x78>
 2b4:	00 c0       	rjmp	.+0      	; 0x2b6 <main+0x82>
 2b6:	00 00       	nop
		_delay_ms(700);
		
		i2c_start(Dev1621+I2C_READ);
 2b8:	81 e9       	ldi	r24, 0x91	; 145
 2ba:	2d d0       	rcall	.+90     	; 0x316 <i2c_start>
		a[0]=i2c_readAck();
 2bc:	5d d0       	rcall	.+186    	; 0x378 <i2c_readAck>
 2be:	c8 2f       	mov	r28, r24
		b[0]=i2c_readNak();
 2c0:	62 d0       	rcall	.+196    	; 0x386 <i2c_readNak>
 2c2:	d8 2f       	mov	r29, r24
		i2c_stop();
 2c4:	46 d0       	rcall	.+140    	; 0x352 <i2c_stop>
		temphalf=b[0];
		temp=a[0];
		uart_putc(temp);
 2c6:	8c 2f       	mov	r24, r28
 2c8:	c7 d0       	rcall	.+398    	; 0x458 <uart_putc>
		uart_putc(temphalf);
 2ca:	8d 2f       	mov	r24, r29
 2cc:	c5 d0       	rcall	.+394    	; 0x458 <uart_putc>
		//RFM12
		PORTB &= ~(1<<PB1);	//DS1621 Ausschalten
 2ce:	c1 98       	cbi	0x18, 1	; 24
		send(temp, temphalf);
 2d0:	6d 2f       	mov	r22, r29
 2d2:	8c 2f       	mov	r24, r28
 2d4:	94 df       	rcall	.-216    	; 0x1fe <send>
	rf12_trans(0xE920);    // Wakup-Timer 61000 ms E93F //E810 4000ms
 2d6:	80 e2       	ldi	r24, 0x20	; 32
 2d8:	99 ee       	ldi	r25, 0xE9	; 233
 2da:	c7 de       	rcall	.-626    	; 0x6a <rf12_trans>
	rf12_trans(0x0000);    // Statusregister auslesen;		
 2dc:	80 e0       	ldi	r24, 0x00	; 0
 2de:	90 e0       	ldi	r25, 0x00	; 0
 2e0:	c4 de       	rcall	.-632    	; 0x6a <rf12_trans>
	rf12_trans(0x8203);    // Wakeup aktivieren, Clockoutput aus	
 2e2:	83 e0       	ldi	r24, 0x03	; 3
 2e4:	92 e8       	ldi	r25, 0x82	; 130
 2e6:	c1 de       	rcall	.-638    	; 0x6a <rf12_trans>

		//Sleep Mode
		GICR |= (1 << INT0);            // externen Interrupt freigeben        
 2e8:	8b b7       	in	r24, 0x3b	; 59
 2ea:	80 64       	ori	r24, 0x40	; 64
 2ec:	8b bf       	out	0x3b, r24	; 59
		set_sleep_mode(SLEEP_MODE_PWR_DOWN);
 2ee:	85 b7       	in	r24, 0x35	; 53
 2f0:	8f 78       	andi	r24, 0x8F	; 143
 2f2:	80 62       	ori	r24, 0x20	; 32
 2f4:	85 bf       	out	0x35, r24	; 53
		sleep_enable();                // in den Schlafmodus wechseln        
 2f6:	85 b7       	in	r24, 0x35	; 53
 2f8:	80 68       	ori	r24, 0x80	; 128
 2fa:	85 bf       	out	0x35, r24	; 53
		sei();
 2fc:	78 94       	sei
		sleep_cpu();
 2fe:	88 95       	sleep
		sleep_disable();
 300:	85 b7       	in	r24, 0x35	; 53
 302:	8f 77       	andi	r24, 0x7F	; 127
 304:	85 bf       	out	0x35, r24	; 53
		// hier wachen wir wieder auf
		GICR &= ~(1 << INT0);           // externen Interrupt sperren
 306:	8b b7       	in	r24, 0x3b	; 59
 308:	8f 7b       	andi	r24, 0xBF	; 191
 30a:	8b bf       	out	0x3b, r24	; 59
 30c:	ae cf       	rjmp	.-164    	; 0x26a <main+0x36>

0000030e <i2c_init>:
*************************************************************************/
void i2c_init(void)
{
  /* initialize TWI clock: 100 kHz clock, TWPS = 0 => prescaler = 1 */
  
  TWSR = 0;                         /* no prescaler */
 30e:	11 b8       	out	0x01, r1	; 1
  TWBR = ((F_CPU/SCL_CLOCK)-16)/2;  /* must be > 10 for stable operation */
 310:	80 e2       	ldi	r24, 0x20	; 32
 312:	80 b9       	out	0x00, r24	; 0
 314:	08 95       	ret

00000316 <i2c_start>:
unsigned char i2c_start(unsigned char address)
{
    uint8_t   twst;

	// send START condition
	TWCR = (1<<TWINT) | (1<<TWSTA) | (1<<TWEN);
 316:	94 ea       	ldi	r25, 0xA4	; 164
 318:	96 bf       	out	0x36, r25	; 54

	// wait until transmission completed
	while(!(TWCR & (1<<TWINT)));		
 31a:	06 b6       	in	r0, 0x36	; 54
 31c:	07 fe       	sbrs	r0, 7
 31e:	fd cf       	rjmp	.-6      	; 0x31a <i2c_start+0x4>

	// check value of TWI Status Register. Mask prescaler bits.
	twst = TW_STATUS & 0xF8;
 320:	91 b1       	in	r25, 0x01	; 1
 322:	98 7f       	andi	r25, 0xF8	; 248
	if ( (twst != TW_START) && (twst != TW_REP_START)) return 1;
 324:	98 30       	cpi	r25, 0x08	; 8
 326:	11 f0       	breq	.+4      	; 0x32c <i2c_start+0x16>
 328:	90 31       	cpi	r25, 0x10	; 16
 32a:	79 f4       	brne	.+30     	; 0x34a <i2c_start+0x34>

	// send device address
	TWDR = address;
 32c:	83 b9       	out	0x03, r24	; 3
	TWCR = (1<<TWINT) | (1<<TWEN);
 32e:	84 e8       	ldi	r24, 0x84	; 132
 330:	86 bf       	out	0x36, r24	; 54

	// wail until transmission completed and ACK/NACK has been received
	while(!(TWCR & (1<<TWINT)));
 332:	06 b6       	in	r0, 0x36	; 54
 334:	07 fe       	sbrs	r0, 7
 336:	fd cf       	rjmp	.-6      	; 0x332 <i2c_start+0x1c>

	// check value of TWI Status Register. Mask prescaler bits.
	twst = TW_STATUS & 0xF8;
 338:	91 b1       	in	r25, 0x01	; 1
 33a:	98 7f       	andi	r25, 0xF8	; 248
	if ( (twst != TW_MT_SLA_ACK) && (twst != TW_MR_SLA_ACK) ) return 1;
 33c:	98 31       	cpi	r25, 0x18	; 24
 33e:	39 f0       	breq	.+14     	; 0x34e <i2c_start+0x38>
 340:	81 e0       	ldi	r24, 0x01	; 1
 342:	90 34       	cpi	r25, 0x40	; 64
 344:	29 f4       	brne	.+10     	; 0x350 <i2c_start+0x3a>
 346:	80 e0       	ldi	r24, 0x00	; 0
 348:	08 95       	ret
	// wait until transmission completed
	while(!(TWCR & (1<<TWINT)));		

	// check value of TWI Status Register. Mask prescaler bits.
	twst = TW_STATUS & 0xF8;
	if ( (twst != TW_START) && (twst != TW_REP_START)) return 1;
 34a:	81 e0       	ldi	r24, 0x01	; 1
 34c:	08 95       	ret

	// check value of TWI Status Register. Mask prescaler bits.
	twst = TW_STATUS & 0xF8;
	if ( (twst != TW_MT_SLA_ACK) && (twst != TW_MR_SLA_ACK) ) return 1;

	return 0;
 34e:	80 e0       	ldi	r24, 0x00	; 0

}/* i2c_start */
 350:	08 95       	ret

00000352 <i2c_stop>:
 Terminates the data transfer and releases the I2C bus
*************************************************************************/
void i2c_stop(void)
{
    /* send stop condition */
	TWCR = (1<<TWINT) | (1<<TWEN) | (1<<TWSTO);
 352:	84 e9       	ldi	r24, 0x94	; 148
 354:	86 bf       	out	0x36, r24	; 54
	
	// wait until stop condition is executed and bus released
	while(TWCR & (1<<TWSTO)); //wieso auskommentieren?
 356:	06 b6       	in	r0, 0x36	; 54
 358:	04 fc       	sbrc	r0, 4
 35a:	fd cf       	rjmp	.-6      	; 0x356 <i2c_stop+0x4>

}/* i2c_stop */
 35c:	08 95       	ret

0000035e <i2c_write>:
unsigned char i2c_write( unsigned char data )
{	
    uint8_t   twst;
    
	// send data to the previously addressed device
	TWDR = data;
 35e:	83 b9       	out	0x03, r24	; 3
	TWCR = (1<<TWINT) | (1<<TWEN);
 360:	84 e8       	ldi	r24, 0x84	; 132
 362:	86 bf       	out	0x36, r24	; 54

	// wait until transmission completed
	while(!(TWCR & (1<<TWINT)));		
 364:	06 b6       	in	r0, 0x36	; 54
 366:	07 fe       	sbrs	r0, 7
 368:	fd cf       	rjmp	.-6      	; 0x364 <i2c_write+0x6>

	// check value of TWI Status Register. Mask prescaler bits
	twst = TW_STATUS & 0xF8;
 36a:	91 b1       	in	r25, 0x01	; 1
 36c:	98 7f       	andi	r25, 0xF8	; 248
	if( twst != TW_MT_DATA_ACK) return 1;
 36e:	81 e0       	ldi	r24, 0x01	; 1
 370:	98 32       	cpi	r25, 0x28	; 40
 372:	09 f4       	brne	.+2      	; 0x376 <i2c_write+0x18>
 374:	80 e0       	ldi	r24, 0x00	; 0
	return 0;

}/* i2c_write */
 376:	08 95       	ret

00000378 <i2c_readAck>:
 
 Return:  byte read from I2C device
*************************************************************************/
unsigned char i2c_readAck(void)
{
	TWCR = (1<<TWINT) | (1<<TWEN) | (1<<TWEA);
 378:	84 ec       	ldi	r24, 0xC4	; 196
 37a:	86 bf       	out	0x36, r24	; 54
	while(!(TWCR & (1<<TWINT)));    
 37c:	06 b6       	in	r0, 0x36	; 54
 37e:	07 fe       	sbrs	r0, 7
 380:	fd cf       	rjmp	.-6      	; 0x37c <i2c_readAck+0x4>

    return TWDR;
 382:	83 b1       	in	r24, 0x03	; 3

}/* i2c_readAck */
 384:	08 95       	ret

00000386 <i2c_readNak>:
 
 Return:  byte read from I2C device
*************************************************************************/
unsigned char i2c_readNak(void)
{
	TWCR = (1<<TWINT) | (1<<TWEN);
 386:	84 e8       	ldi	r24, 0x84	; 132
 388:	86 bf       	out	0x36, r24	; 54
	while(!(TWCR & (1<<TWINT)));
 38a:	06 b6       	in	r0, 0x36	; 54
 38c:	07 fe       	sbrs	r0, 7
 38e:	fd cf       	rjmp	.-6      	; 0x38a <i2c_readNak+0x4>
	
    return TWDR;
 390:	83 b1       	in	r24, 0x03	; 3

}/* i2c_readNak */
 392:	08 95       	ret

00000394 <__vector_11>:
ISR(UART0_RECEIVE_INTERRUPT)
/*************************************************************************
Function: UART Receive Complete interrupt
Purpose:  called when the UART has received a character
**************************************************************************/
{
 394:	1f 92       	push	r1
 396:	0f 92       	push	r0
 398:	0f b6       	in	r0, 0x3f	; 63
 39a:	0f 92       	push	r0
 39c:	11 24       	eor	r1, r1
 39e:	2f 93       	push	r18
 3a0:	8f 93       	push	r24
 3a2:	9f 93       	push	r25
 3a4:	ef 93       	push	r30
 3a6:	ff 93       	push	r31
    unsigned char usr;
    unsigned char lastRxError;
 
 
    /* read UART status register and UART data register */ 
    usr  = UART0_STATUS;
 3a8:	8b b1       	in	r24, 0x0b	; 11
    data = UART0_DATA;
 3aa:	2c b1       	in	r18, 0x0c	; 12
    
    /* */
#if defined( AT90_UART )
    lastRxError = (usr & (_BV(FE)|_BV(DOR)) );
#elif defined( ATMEGA_USART )
    lastRxError = (usr & (_BV(FE)|_BV(DOR)) );
 3ac:	88 71       	andi	r24, 0x18	; 24
#elif defined ( ATMEGA_UART )
    lastRxError = (usr & (_BV(FE)|_BV(DOR)) );
#endif
        
    /* calculate buffer index */ 
    tmphead = ( UART_RxHead + 1) & UART_RX_BUFFER_MASK;
 3ae:	e0 91 62 00 	lds	r30, 0x0062
 3b2:	ef 5f       	subi	r30, 0xFF	; 255
 3b4:	ef 71       	andi	r30, 0x1F	; 31
    
    if ( tmphead == UART_RxTail ) {
 3b6:	90 91 61 00 	lds	r25, 0x0061
 3ba:	e9 17       	cp	r30, r25
 3bc:	39 f0       	breq	.+14     	; 0x3cc <__vector_11+0x38>
        /* error: receive buffer overflow */
        lastRxError = UART_BUFFER_OVERFLOW >> 8;
    }else{
        /* store new index */
        UART_RxHead = tmphead;
 3be:	e0 93 62 00 	sts	0x0062, r30
        /* store received data in buffer */
        UART_RxBuf[tmphead] = data;
 3c2:	f0 e0       	ldi	r31, 0x00	; 0
 3c4:	eb 59       	subi	r30, 0x9B	; 155
 3c6:	ff 4f       	sbci	r31, 0xFF	; 255
 3c8:	20 83       	st	Z, r18
 3ca:	01 c0       	rjmp	.+2      	; 0x3ce <__vector_11+0x3a>
    /* calculate buffer index */ 
    tmphead = ( UART_RxHead + 1) & UART_RX_BUFFER_MASK;
    
    if ( tmphead == UART_RxTail ) {
        /* error: receive buffer overflow */
        lastRxError = UART_BUFFER_OVERFLOW >> 8;
 3cc:	82 e0       	ldi	r24, 0x02	; 2
        /* store new index */
        UART_RxHead = tmphead;
        /* store received data in buffer */
        UART_RxBuf[tmphead] = data;
    }
    UART_LastRxError = lastRxError;   
 3ce:	80 93 60 00 	sts	0x0060, r24
}
 3d2:	ff 91       	pop	r31
 3d4:	ef 91       	pop	r30
 3d6:	9f 91       	pop	r25
 3d8:	8f 91       	pop	r24
 3da:	2f 91       	pop	r18
 3dc:	0f 90       	pop	r0
 3de:	0f be       	out	0x3f, r0	; 63
 3e0:	0f 90       	pop	r0
 3e2:	1f 90       	pop	r1
 3e4:	18 95       	reti

000003e6 <__vector_12>:
ISR(UART0_TRANSMIT_INTERRUPT)
/*************************************************************************
Function: UART Data Register Empty interrupt
Purpose:  called when the UART is ready to transmit the next byte
**************************************************************************/
{
 3e6:	1f 92       	push	r1
 3e8:	0f 92       	push	r0
 3ea:	0f b6       	in	r0, 0x3f	; 63
 3ec:	0f 92       	push	r0
 3ee:	11 24       	eor	r1, r1
 3f0:	8f 93       	push	r24
 3f2:	9f 93       	push	r25
 3f4:	ef 93       	push	r30
 3f6:	ff 93       	push	r31
    unsigned char tmptail;

    
    if ( UART_TxHead != UART_TxTail) {
 3f8:	90 91 64 00 	lds	r25, 0x0064
 3fc:	80 91 63 00 	lds	r24, 0x0063
 400:	98 17       	cp	r25, r24
 402:	61 f0       	breq	.+24     	; 0x41c <__vector_12+0x36>
        /* calculate and store new buffer index */
        tmptail = (UART_TxTail + 1) & UART_TX_BUFFER_MASK;
 404:	e0 91 63 00 	lds	r30, 0x0063
 408:	ef 5f       	subi	r30, 0xFF	; 255
 40a:	ef 71       	andi	r30, 0x1F	; 31
        UART_TxTail = tmptail;
 40c:	e0 93 63 00 	sts	0x0063, r30
        /* get one byte from buffer and write it to UART */
        UART0_DATA = UART_TxBuf[tmptail];  /* start transmission */
 410:	f0 e0       	ldi	r31, 0x00	; 0
 412:	eb 57       	subi	r30, 0x7B	; 123
 414:	ff 4f       	sbci	r31, 0xFF	; 255
 416:	80 81       	ld	r24, Z
 418:	8c b9       	out	0x0c, r24	; 12
 41a:	01 c0       	rjmp	.+2      	; 0x41e <__vector_12+0x38>
    }else{
        /* tx buffer empty, disable UDRE interrupt */
        UART0_CONTROL &= ~_BV(UART0_UDRIE);
 41c:	55 98       	cbi	0x0a, 5	; 10
    }
}
 41e:	ff 91       	pop	r31
 420:	ef 91       	pop	r30
 422:	9f 91       	pop	r25
 424:	8f 91       	pop	r24
 426:	0f 90       	pop	r0
 428:	0f be       	out	0x3f, r0	; 63
 42a:	0f 90       	pop	r0
 42c:	1f 90       	pop	r1
 42e:	18 95       	reti

00000430 <uart_init>:
Input:    baudrate using macro UART_BAUD_SELECT()
Returns:  none
**************************************************************************/
void uart_init(unsigned int baudrate)
{
    UART_TxHead = 0;
 430:	10 92 64 00 	sts	0x0064, r1
    UART_TxTail = 0;
 434:	10 92 63 00 	sts	0x0063, r1
    UART_RxHead = 0;
 438:	10 92 62 00 	sts	0x0062, r1
    UART_RxTail = 0;
 43c:	10 92 61 00 	sts	0x0061, r1
    /* enable UART receiver and transmmitter and receive complete interrupt */
    UART0_CONTROL = _BV(RXCIE)|_BV(RXEN)|_BV(TXEN);

#elif defined (ATMEGA_USART)
    /* Set baud rate */
    if ( baudrate & 0x8000 )
 440:	99 23       	and	r25, r25
 442:	1c f4       	brge	.+6      	; 0x44a <uart_init+0x1a>
    {
    	 UART0_STATUS = (1<<U2X);  //Enable 2x speed 
 444:	22 e0       	ldi	r18, 0x02	; 2
 446:	2b b9       	out	0x0b, r18	; 11
    	 baudrate &= ~0x8000;
 448:	9f 77       	andi	r25, 0x7F	; 127
    }
    UBRRH = (unsigned char)(baudrate>>8);
 44a:	90 bd       	out	0x20, r25	; 32
    UBRRL = (unsigned char) baudrate;
 44c:	89 b9       	out	0x09, r24	; 9
   
    /* Enable USART receiver and transmitter and receive complete interrupt */
    UART0_CONTROL = _BV(RXCIE)|(1<<RXEN)|(1<<TXEN);
 44e:	88 e9       	ldi	r24, 0x98	; 152
 450:	8a b9       	out	0x0a, r24	; 10
    
    /* Set frame format: asynchronous, 8data, no parity, 1stop bit */
    #ifdef URSEL
    UCSRC = (1<<URSEL)|(3<<UCSZ0);
 452:	86 e8       	ldi	r24, 0x86	; 134
 454:	80 bd       	out	0x20, r24	; 32
 456:	08 95       	ret

00000458 <uart_putc>:
void uart_putc(unsigned char data)
{
    unsigned char tmphead;

    
    tmphead  = (UART_TxHead + 1) & UART_TX_BUFFER_MASK;
 458:	20 91 64 00 	lds	r18, 0x0064
 45c:	2f 5f       	subi	r18, 0xFF	; 255
 45e:	2f 71       	andi	r18, 0x1F	; 31
    
    while ( tmphead == UART_TxTail ){
 460:	90 91 63 00 	lds	r25, 0x0063
 464:	29 17       	cp	r18, r25
 466:	e1 f3       	breq	.-8      	; 0x460 <__stack+0x1>
        ;/* wait for free space in buffer */
    }
    
    UART_TxBuf[tmphead] = data;
 468:	e2 2f       	mov	r30, r18
 46a:	f0 e0       	ldi	r31, 0x00	; 0
 46c:	eb 57       	subi	r30, 0x7B	; 123
 46e:	ff 4f       	sbci	r31, 0xFF	; 255
 470:	80 83       	st	Z, r24
    UART_TxHead = tmphead;
 472:	20 93 64 00 	sts	0x0064, r18

    /* enable UDRE interrupt */
    UART0_CONTROL    |= _BV(UART0_UDRIE);
 476:	55 9a       	sbi	0x0a, 5	; 10
 478:	08 95       	ret

0000047a <uart_puts_p>:
Purpose:  transmit string from program memory to UART
Input:    program memory string to be transmitted
Returns:  none
**************************************************************************/
void uart_puts_p(const char *progmem_s )
{
 47a:	cf 93       	push	r28
 47c:	df 93       	push	r29
    register char c;
    
    while ( (c = pgm_read_byte(progmem_s++)) ) 
 47e:	ec 01       	movw	r28, r24
 480:	21 96       	adiw	r28, 0x01	; 1
 482:	fc 01       	movw	r30, r24
 484:	84 91       	lpm	r24, Z
 486:	88 23       	and	r24, r24
 488:	31 f0       	breq	.+12     	; 0x496 <uart_puts_p+0x1c>
      uart_putc(c);
 48a:	e6 df       	rcall	.-52     	; 0x458 <uart_putc>
**************************************************************************/
void uart_puts_p(const char *progmem_s )
{
    register char c;
    
    while ( (c = pgm_read_byte(progmem_s++)) ) 
 48c:	fe 01       	movw	r30, r28
 48e:	84 91       	lpm	r24, Z
 490:	21 96       	adiw	r28, 0x01	; 1
 492:	81 11       	cpse	r24, r1
 494:	fa cf       	rjmp	.-12     	; 0x48a <uart_puts_p+0x10>
      uart_putc(c);

}/* uart_puts_p */
 496:	df 91       	pop	r29
 498:	cf 91       	pop	r28
 49a:	08 95       	ret

0000049c <_exit>:
 49c:	f8 94       	cli

0000049e <__stop_program>:
 49e:	ff cf       	rjmp	.-2      	; 0x49e <__stop_program>
