Static Timing Analysis

Project : PS0C4_Intro
Build Time : 04/15/18 13:12:21
Device : CY8C4245AXI-483
Temperature : -40C - 85C
VDDA : 3.30
VDDD : 3.30
Voltage : 3.3
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+ Timing Violation Section
No Timing Violations
+ Clock Summary Section
Clock Domain Nominal Frequency Required Frequency Maximum Frequency Violation
CyHFCLK CyHFCLK 24.000 MHz 24.000 MHz N/A
Clock_1 CyHFCLK 12.000 MHz 12.000 MHz 43.159 MHz
CyILO CyILO 32.000 kHz 32.000 kHz N/A
CyIMO CyIMO 24.000 MHz 24.000 MHz N/A
CyLFCLK CyLFCLK 32.000 kHz 32.000 kHz N/A
CyRouted1 CyRouted1 24.000 MHz 24.000 MHz N/A
CySYSCLK CySYSCLK 24.000 MHz 24.000 MHz N/A
+ Register to Register Section
+ Setup Subsection
Path Delay Requirement : 83.3333ns(12 MHz)
Source Destination FMax Delay (ns) Slack (ns) Violation
\PWM2:PWMUDB:sP16:pwmdp:u0\/z0 \PWM2:PWMUDB:sP16:pwmdp:u1\/ci 43.159 MHz 23.170 60.163
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell3 U(0,1) 1 \PWM2:PWMUDB:sP16:pwmdp:u0\ \PWM2:PWMUDB:sP16:pwmdp:u0\/clock \PWM2:PWMUDB:sP16:pwmdp:u0\/z0 2.320
Route 1 \PWM2:PWMUDB:sP16:pwmdp:u0.z0__sig\ \PWM2:PWMUDB:sP16:pwmdp:u0\/z0 \PWM2:PWMUDB:sP16:pwmdp:u1\/z0i 0.000
datapathcell4 U(1,1) 1 \PWM2:PWMUDB:sP16:pwmdp:u1\ \PWM2:PWMUDB:sP16:pwmdp:u1\/z0i \PWM2:PWMUDB:sP16:pwmdp:u1\/z0_comb 2.960
Route 1 \PWM2:PWMUDB:tc_i\ \PWM2:PWMUDB:sP16:pwmdp:u1\/z0_comb \PWM2:PWMUDB:sP16:pwmdp:u0\/cs_addr_2 3.090
datapathcell3 U(0,1) 1 \PWM2:PWMUDB:sP16:pwmdp:u0\ \PWM2:PWMUDB:sP16:pwmdp:u0\/cs_addr_2 \PWM2:PWMUDB:sP16:pwmdp:u0\/co_msb 9.710
Route 1 \PWM2:PWMUDB:sP16:pwmdp:u0.co_msb__sig\ \PWM2:PWMUDB:sP16:pwmdp:u0\/co_msb \PWM2:PWMUDB:sP16:pwmdp:u1\/ci 0.000
datapathcell4 U(1,1) 1 \PWM2:PWMUDB:sP16:pwmdp:u1\ SETUP 5.090
Clock Skew 0.000
\PWM1:PWMUDB:sP16:pwmdp:u0\/z0 \PWM1:PWMUDB:sP16:pwmdp:u1\/ci 43.634 MHz 22.918 60.415
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell1 U(1,0) 1 \PWM1:PWMUDB:sP16:pwmdp:u0\ \PWM1:PWMUDB:sP16:pwmdp:u0\/clock \PWM1:PWMUDB:sP16:pwmdp:u0\/z0 2.320
Route 1 \PWM1:PWMUDB:sP16:pwmdp:u0.z0__sig\ \PWM1:PWMUDB:sP16:pwmdp:u0\/z0 \PWM1:PWMUDB:sP16:pwmdp:u1\/z0i 0.000
datapathcell2 U(0,0) 1 \PWM1:PWMUDB:sP16:pwmdp:u1\ \PWM1:PWMUDB:sP16:pwmdp:u1\/z0i \PWM1:PWMUDB:sP16:pwmdp:u1\/z0_comb 2.960
Route 1 \PWM1:PWMUDB:tc_i\ \PWM1:PWMUDB:sP16:pwmdp:u1\/z0_comb \PWM1:PWMUDB:sP16:pwmdp:u0\/cs_addr_2 2.838
datapathcell1 U(1,0) 1 \PWM1:PWMUDB:sP16:pwmdp:u0\ \PWM1:PWMUDB:sP16:pwmdp:u0\/cs_addr_2 \PWM1:PWMUDB:sP16:pwmdp:u0\/co_msb 9.710
Route 1 \PWM1:PWMUDB:sP16:pwmdp:u0.co_msb__sig\ \PWM1:PWMUDB:sP16:pwmdp:u0\/co_msb \PWM1:PWMUDB:sP16:pwmdp:u1\/ci 0.000
datapathcell2 U(0,0) 1 \PWM1:PWMUDB:sP16:pwmdp:u1\ SETUP 5.090
Clock Skew 0.000
\PWM2:PWMUDB:sP16:pwmdp:u1\/z0_comb \PWM2:PWMUDB:sP16:pwmdp:u1\/ci 45.998 MHz 21.740 61.593
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell4 U(1,1) 1 \PWM2:PWMUDB:sP16:pwmdp:u1\ \PWM2:PWMUDB:sP16:pwmdp:u1\/clock \PWM2:PWMUDB:sP16:pwmdp:u1\/z0_comb 3.850
Route 1 \PWM2:PWMUDB:tc_i\ \PWM2:PWMUDB:sP16:pwmdp:u1\/z0_comb \PWM2:PWMUDB:sP16:pwmdp:u0\/cs_addr_2 3.090
datapathcell3 U(0,1) 1 \PWM2:PWMUDB:sP16:pwmdp:u0\ \PWM2:PWMUDB:sP16:pwmdp:u0\/cs_addr_2 \PWM2:PWMUDB:sP16:pwmdp:u0\/co_msb 9.710
Route 1 \PWM2:PWMUDB:sP16:pwmdp:u0.co_msb__sig\ \PWM2:PWMUDB:sP16:pwmdp:u0\/co_msb \PWM2:PWMUDB:sP16:pwmdp:u1\/ci 0.000
datapathcell4 U(1,1) 1 \PWM2:PWMUDB:sP16:pwmdp:u1\ SETUP 5.090
Clock Skew 0.000
\PWM1:PWMUDB:sP16:pwmdp:u1\/z0_comb \PWM1:PWMUDB:sP16:pwmdp:u1\/ci 46.538 MHz 21.488 61.845
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell2 U(0,0) 1 \PWM1:PWMUDB:sP16:pwmdp:u1\ \PWM1:PWMUDB:sP16:pwmdp:u1\/clock \PWM1:PWMUDB:sP16:pwmdp:u1\/z0_comb 3.850
Route 1 \PWM1:PWMUDB:tc_i\ \PWM1:PWMUDB:sP16:pwmdp:u1\/z0_comb \PWM1:PWMUDB:sP16:pwmdp:u0\/cs_addr_2 2.838
datapathcell1 U(1,0) 1 \PWM1:PWMUDB:sP16:pwmdp:u0\ \PWM1:PWMUDB:sP16:pwmdp:u0\/cs_addr_2 \PWM1:PWMUDB:sP16:pwmdp:u0\/co_msb 9.710
Route 1 \PWM1:PWMUDB:sP16:pwmdp:u0.co_msb__sig\ \PWM1:PWMUDB:sP16:pwmdp:u0\/co_msb \PWM1:PWMUDB:sP16:pwmdp:u1\/ci 0.000
datapathcell2 U(0,0) 1 \PWM1:PWMUDB:sP16:pwmdp:u1\ SETUP 5.090
Clock Skew 0.000
\PWM2:PWMUDB:sP16:pwmdp:u0\/z0 \PWM2:PWMUDB:sP16:pwmdp:u0\/cs_addr_2 50.277 MHz 19.890 63.443
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell3 U(0,1) 1 \PWM2:PWMUDB:sP16:pwmdp:u0\ \PWM2:PWMUDB:sP16:pwmdp:u0\/clock \PWM2:PWMUDB:sP16:pwmdp:u0\/z0 2.320
Route 1 \PWM2:PWMUDB:sP16:pwmdp:u0.z0__sig\ \PWM2:PWMUDB:sP16:pwmdp:u0\/z0 \PWM2:PWMUDB:sP16:pwmdp:u1\/z0i 0.000
datapathcell4 U(1,1) 1 \PWM2:PWMUDB:sP16:pwmdp:u1\ \PWM2:PWMUDB:sP16:pwmdp:u1\/z0i \PWM2:PWMUDB:sP16:pwmdp:u1\/z0_comb 2.960
Route 1 \PWM2:PWMUDB:tc_i\ \PWM2:PWMUDB:sP16:pwmdp:u1\/z0_comb \PWM2:PWMUDB:sP16:pwmdp:u0\/cs_addr_2 3.090
datapathcell3 U(0,1) 1 \PWM2:PWMUDB:sP16:pwmdp:u0\ SETUP 11.520
Clock Skew 0.000
\PWM2:PWMUDB:sP16:pwmdp:u0\/z0 \PWM2:PWMUDB:sP16:pwmdp:u1\/cs_addr_2 50.277 MHz 19.890 63.443
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell3 U(0,1) 1 \PWM2:PWMUDB:sP16:pwmdp:u0\ \PWM2:PWMUDB:sP16:pwmdp:u0\/clock \PWM2:PWMUDB:sP16:pwmdp:u0\/z0 2.320
Route 1 \PWM2:PWMUDB:sP16:pwmdp:u0.z0__sig\ \PWM2:PWMUDB:sP16:pwmdp:u0\/z0 \PWM2:PWMUDB:sP16:pwmdp:u1\/z0i 0.000
datapathcell4 U(1,1) 1 \PWM2:PWMUDB:sP16:pwmdp:u1\ \PWM2:PWMUDB:sP16:pwmdp:u1\/z0i \PWM2:PWMUDB:sP16:pwmdp:u1\/z0_comb 2.960
datapathcell4 U(1,1) 1 \PWM2:PWMUDB:sP16:pwmdp:u1\ \PWM2:PWMUDB:sP16:pwmdp:u1\/z0_comb \PWM2:PWMUDB:sP16:pwmdp:u1\/cs_addr_2 3.090
datapathcell4 U(1,1) 1 \PWM2:PWMUDB:sP16:pwmdp:u1\ SETUP 11.520
Clock Skew 0.000
\PWM1:PWMUDB:sP16:pwmdp:u0\/z0 \PWM1:PWMUDB:sP16:pwmdp:u1\/cs_addr_2 50.919 MHz 19.639 63.694
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell1 U(1,0) 1 \PWM1:PWMUDB:sP16:pwmdp:u0\ \PWM1:PWMUDB:sP16:pwmdp:u0\/clock \PWM1:PWMUDB:sP16:pwmdp:u0\/z0 2.320
Route 1 \PWM1:PWMUDB:sP16:pwmdp:u0.z0__sig\ \PWM1:PWMUDB:sP16:pwmdp:u0\/z0 \PWM1:PWMUDB:sP16:pwmdp:u1\/z0i 0.000
datapathcell2 U(0,0) 1 \PWM1:PWMUDB:sP16:pwmdp:u1\ \PWM1:PWMUDB:sP16:pwmdp:u1\/z0i \PWM1:PWMUDB:sP16:pwmdp:u1\/z0_comb 2.960
datapathcell2 U(0,0) 1 \PWM1:PWMUDB:sP16:pwmdp:u1\ \PWM1:PWMUDB:sP16:pwmdp:u1\/z0_comb \PWM1:PWMUDB:sP16:pwmdp:u1\/cs_addr_2 2.839
datapathcell2 U(0,0) 1 \PWM1:PWMUDB:sP16:pwmdp:u1\ SETUP 11.520
Clock Skew 0.000
\PWM1:PWMUDB:sP16:pwmdp:u0\/z0 \PWM1:PWMUDB:sP16:pwmdp:u0\/cs_addr_2 50.922 MHz 19.638 63.695
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell1 U(1,0) 1 \PWM1:PWMUDB:sP16:pwmdp:u0\ \PWM1:PWMUDB:sP16:pwmdp:u0\/clock \PWM1:PWMUDB:sP16:pwmdp:u0\/z0 2.320
Route 1 \PWM1:PWMUDB:sP16:pwmdp:u0.z0__sig\ \PWM1:PWMUDB:sP16:pwmdp:u0\/z0 \PWM1:PWMUDB:sP16:pwmdp:u1\/z0i 0.000
datapathcell2 U(0,0) 1 \PWM1:PWMUDB:sP16:pwmdp:u1\ \PWM1:PWMUDB:sP16:pwmdp:u1\/z0i \PWM1:PWMUDB:sP16:pwmdp:u1\/z0_comb 2.960
Route 1 \PWM1:PWMUDB:tc_i\ \PWM1:PWMUDB:sP16:pwmdp:u1\/z0_comb \PWM1:PWMUDB:sP16:pwmdp:u0\/cs_addr_2 2.838
datapathcell1 U(1,0) 1 \PWM1:PWMUDB:sP16:pwmdp:u0\ SETUP 11.520
Clock Skew 0.000
\PWM2:PWMUDB:runmode_enable\/q \PWM2:PWMUDB:sP16:pwmdp:u1\/ci 51.722 MHz 19.334 63.999
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell10 U(1,1) 1 \PWM2:PWMUDB:runmode_enable\ \PWM2:PWMUDB:runmode_enable\/clock_0 \PWM2:PWMUDB:runmode_enable\/q 1.250
Route 1 \PWM2:PWMUDB:runmode_enable\ \PWM2:PWMUDB:runmode_enable\/q \PWM2:PWMUDB:sP16:pwmdp:u0\/cs_addr_1 3.284
datapathcell3 U(0,1) 1 \PWM2:PWMUDB:sP16:pwmdp:u0\ \PWM2:PWMUDB:sP16:pwmdp:u0\/cs_addr_1 \PWM2:PWMUDB:sP16:pwmdp:u0\/co_msb 9.710
Route 1 \PWM2:PWMUDB:sP16:pwmdp:u0.co_msb__sig\ \PWM2:PWMUDB:sP16:pwmdp:u0\/co_msb \PWM2:PWMUDB:sP16:pwmdp:u1\/ci 0.000
datapathcell4 U(1,1) 1 \PWM2:PWMUDB:sP16:pwmdp:u1\ SETUP 5.090
Clock Skew 0.000
\PWM1:PWMUDB:runmode_enable\/q \PWM1:PWMUDB:sP16:pwmdp:u1\/ci 52.876 MHz 18.912 64.421
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell3 U(0,0) 1 \PWM1:PWMUDB:runmode_enable\ \PWM1:PWMUDB:runmode_enable\/clock_0 \PWM1:PWMUDB:runmode_enable\/q 1.250
Route 1 \PWM1:PWMUDB:runmode_enable\ \PWM1:PWMUDB:runmode_enable\/q \PWM1:PWMUDB:sP16:pwmdp:u0\/cs_addr_1 2.862
datapathcell1 U(1,0) 1 \PWM1:PWMUDB:sP16:pwmdp:u0\ \PWM1:PWMUDB:sP16:pwmdp:u0\/cs_addr_1 \PWM1:PWMUDB:sP16:pwmdp:u0\/co_msb 9.710
Route 1 \PWM1:PWMUDB:sP16:pwmdp:u0.co_msb__sig\ \PWM1:PWMUDB:sP16:pwmdp:u0\/co_msb \PWM1:PWMUDB:sP16:pwmdp:u1\/ci 0.000
datapathcell2 U(0,0) 1 \PWM1:PWMUDB:sP16:pwmdp:u1\ SETUP 5.090
Clock Skew 0.000
+ Hold Subsection
Source Destination Slack (ns) Violation
\PWM1:PWMUDB:status_1\/q \PWM1:PWMUDB:genblk8:stsreg\/status_1 1.507
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell7 U(0,0) 1 \PWM1:PWMUDB:status_1\ \PWM1:PWMUDB:status_1\/clock_0 \PWM1:PWMUDB:status_1\/q 1.250
Route 1 \PWM1:PWMUDB:status_1\ \PWM1:PWMUDB:status_1\/q \PWM1:PWMUDB:genblk8:stsreg\/status_1 2.257
statusicell1 U(0,0) 1 \PWM1:PWMUDB:genblk8:stsreg\ HOLD -2.000
Clock Skew 0.000
\PWM2:PWMUDB:status_0\/q \PWM2:PWMUDB:genblk8:stsreg\/status_0 1.557
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell13 U(1,1) 1 \PWM2:PWMUDB:status_0\ \PWM2:PWMUDB:status_0\/clock_0 \PWM2:PWMUDB:status_0\/q 1.250
Route 1 \PWM2:PWMUDB:status_0\ \PWM2:PWMUDB:status_0\/q \PWM2:PWMUDB:genblk8:stsreg\/status_0 2.307
statusicell2 U(1,1) 1 \PWM2:PWMUDB:genblk8:stsreg\ HOLD -2.000
Clock Skew 0.000
\PWM2:PWMUDB:status_1\/q \PWM2:PWMUDB:genblk8:stsreg\/status_1 1.559
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell14 U(1,1) 1 \PWM2:PWMUDB:status_1\ \PWM2:PWMUDB:status_1\/clock_0 \PWM2:PWMUDB:status_1\/q 1.250
Route 1 \PWM2:PWMUDB:status_1\ \PWM2:PWMUDB:status_1\/q \PWM2:PWMUDB:genblk8:stsreg\/status_1 2.309
statusicell2 U(1,1) 1 \PWM2:PWMUDB:genblk8:stsreg\ HOLD -2.000
Clock Skew 0.000
\PWM1:PWMUDB:sP16:pwmdp:u0\/co_msb \PWM1:PWMUDB:sP16:pwmdp:u1\/ci 3.210
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell1 U(1,0) 1 \PWM1:PWMUDB:sP16:pwmdp:u0\ \PWM1:PWMUDB:sP16:pwmdp:u0\/clock \PWM1:PWMUDB:sP16:pwmdp:u0\/co_msb 3.210
Route 1 \PWM1:PWMUDB:sP16:pwmdp:u0.co_msb__sig\ \PWM1:PWMUDB:sP16:pwmdp:u0\/co_msb \PWM1:PWMUDB:sP16:pwmdp:u1\/ci 0.000
datapathcell2 U(0,0) 1 \PWM1:PWMUDB:sP16:pwmdp:u1\ HOLD 0.000
Clock Skew 0.000
\PWM2:PWMUDB:sP16:pwmdp:u0\/co_msb \PWM2:PWMUDB:sP16:pwmdp:u1\/ci 3.210
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell3 U(0,1) 1 \PWM2:PWMUDB:sP16:pwmdp:u0\ \PWM2:PWMUDB:sP16:pwmdp:u0\/clock \PWM2:PWMUDB:sP16:pwmdp:u0\/co_msb 3.210
Route 1 \PWM2:PWMUDB:sP16:pwmdp:u0.co_msb__sig\ \PWM2:PWMUDB:sP16:pwmdp:u0\/co_msb \PWM2:PWMUDB:sP16:pwmdp:u1\/ci 0.000
datapathcell4 U(1,1) 1 \PWM2:PWMUDB:sP16:pwmdp:u1\ HOLD 0.000
Clock Skew 0.000
\PWM1:PWMUDB:status_0\/q \PWM1:PWMUDB:genblk8:stsreg\/status_0 3.282
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell6 U(0,0) 1 \PWM1:PWMUDB:status_0\ \PWM1:PWMUDB:status_0\/clock_0 \PWM1:PWMUDB:status_0\/q 1.250
Route 1 \PWM1:PWMUDB:status_0\ \PWM1:PWMUDB:status_0\/q \PWM1:PWMUDB:genblk8:stsreg\/status_0 4.032
statusicell1 U(0,0) 1 \PWM1:PWMUDB:genblk8:stsreg\ HOLD -2.000
Clock Skew 0.000
\PWM1:PWMUDB:prevCompare1\/q \PWM1:PWMUDB:status_0\/main_0 3.478
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell4 U(0,0) 1 \PWM1:PWMUDB:prevCompare1\ \PWM1:PWMUDB:prevCompare1\/clock_0 \PWM1:PWMUDB:prevCompare1\/q 1.250
Route 1 \PWM1:PWMUDB:prevCompare1\ \PWM1:PWMUDB:prevCompare1\/q \PWM1:PWMUDB:status_0\/main_0 2.228
macrocell6 U(0,0) 1 \PWM1:PWMUDB:status_0\ HOLD 0.000
Clock Skew 0.000
\PWM1:PWMUDB:prevCompare2\/q \PWM1:PWMUDB:status_1\/main_0 3.479
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell5 U(0,0) 1 \PWM1:PWMUDB:prevCompare2\ \PWM1:PWMUDB:prevCompare2\/clock_0 \PWM1:PWMUDB:prevCompare2\/q 1.250
Route 1 \PWM1:PWMUDB:prevCompare2\ \PWM1:PWMUDB:prevCompare2\/q \PWM1:PWMUDB:status_1\/main_0 2.229
macrocell7 U(0,0) 1 \PWM1:PWMUDB:status_1\ HOLD 0.000
Clock Skew 0.000
\PWM2:PWMUDB:prevCompare1\/q \PWM2:PWMUDB:status_0\/main_0 3.541
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell11 U(1,1) 1 \PWM2:PWMUDB:prevCompare1\ \PWM2:PWMUDB:prevCompare1\/clock_0 \PWM2:PWMUDB:prevCompare1\/q 1.250
Route 1 \PWM2:PWMUDB:prevCompare1\ \PWM2:PWMUDB:prevCompare1\/q \PWM2:PWMUDB:status_0\/main_0 2.291
macrocell13 U(1,1) 1 \PWM2:PWMUDB:status_0\ HOLD 0.000
Clock Skew 0.000
\PWM2:PWMUDB:prevCompare2\/q \PWM2:PWMUDB:status_1\/main_0 3.555
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell12 U(1,1) 1 \PWM2:PWMUDB:prevCompare2\ \PWM2:PWMUDB:prevCompare2\/clock_0 \PWM2:PWMUDB:prevCompare2\/q 1.250
Route 1 \PWM2:PWMUDB:prevCompare2\ \PWM2:PWMUDB:prevCompare2\/q \PWM2:PWMUDB:status_1\/main_0 2.305
macrocell14 U(1,1) 1 \PWM2:PWMUDB:status_1\ HOLD 0.000
Clock Skew 0.000
+ Clock To Output Section
+ Clock_1
Source Destination Delay (ns)
Net_285/q B(0)_PAD 23.653
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell15 U(1,1) 1 Net_285 Net_285/clock_0 Net_285/q 1.250
Route 1 Net_285 Net_285/q B(0)/pin_input 6.173
iocell3 P1[2] 1 B(0) B(0)/pin_input B(0)/pad_out 16.230
Route 1 B(0)_PAD B(0)/pad_out B(0)_PAD 0.000
Clock Clock path delay 0.000
Net_273/q G(0)_PAD 22.059
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell9 U(0,0) 1 Net_273 Net_273/clock_0 Net_273/q 1.250
Route 1 Net_273 Net_273/q G(0)/pin_input 5.829
iocell2 P1[1] 1 G(0) G(0)/pin_input G(0)/pad_out 14.980
Route 1 G(0)_PAD G(0)/pad_out G(0)_PAD 0.000
Clock Clock path delay 0.000
Net_193/q R(0)_PAD 21.761
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell8 U(0,0) 1 Net_193 Net_193/clock_0 Net_193/q 1.250
Route 1 Net_193 Net_193/q R(0)/pin_input 5.391
iocell1 P1[0] 1 R(0) R(0)/pin_input R(0)/pad_out 15.120
Route 1 R(0)_PAD R(0)/pad_out R(0)_PAD 0.000
Clock Clock path delay 0.000