Device Usage Page (usage_statistics_webtalk.html)

This HTML page displays the device usage statistics that will be sent to Xilinx.
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software_version_and_target_device
betaFALSE build_version1682563
date_generatedMon Dec 12 13:21:18 2016 os_platformWIN64
product_versionVivado v2016.3 (64-bit) project_id175c14cadc5140268d352ee6d316031c
project_iteration42 random_id7d4e4a01fbe65fdfa3025226e137833a
registration_id7d4e4a01fbe65fdfa3025226e137833a route_designTRUE
target_devicexc7a35t target_familyartix7
target_packagecpg236 target_speed-1
tool_flowVivado

user_environment
cpu_nameIntel(R) Core(TM) i7-6700HQ CPU @ 2.60GHz cpu_speed2592 MHz
os_nameMicrosoft Windows 8 or later , 64-bit os_releasemajor release (build 9200)
system_ram16.000 GB total_processors1

vivado_usage
gui_resources
amplitude_prescaler.vhd, 1199, 485=1 amplitude_prescaler.vhd, 134, 504=1 amplitude_prescaler.vhd, 252, 501=1 amplitude_prescaler.vhd, 279, 347=2
amplitude_prescaler.vhd, 279, 347, false, false, false, false, true=1 amplitude_prescaler.vhd, 381, 502=1 amplitude_prescaler.vhd, 385, 501=1 amplitude_prescaler.vhd, 398, 502=1
amplitude_prescaler.vhd, 409, 365=1 amplitude_prescaler.vhd, 411, 505=1 amplitude_prescaler.vhd, 420, 481=1 amplitude_prescaler.vhd, 678, 482=1
amplitude_prescaler.vhd, 76, 501=1 amplitude_prescaler.vhd, 76, 501, false, false, false, false, true=1 amplitude_prescaler.vhd, 79, 210=1 amplitude_prescaler.vhd, 80, 348=1
basedialog_cancel=7 basedialog_ok=16 basedialog_yes=10 closeplanner_no=1
cmdmsgdialog_ok=8 filesetpanel_0_critical_warning=2 filesetpanel_file_set_panel_tree=34 findandreplacealldialog_find=1
findinfilesview_replace_all_occurrences_in_all_files=1 flownavigatortreepanel_flow_navigator_tree=40 fourier_func_gen.vhd, 177, 362=2 fourier_func_gen.vhd, 177, 362, false, false, false, false, true=1
fourier_func_gen.vhd, 328, 364=1 fourier_func_gen.vhd, 401, 369=1 fourier_func_gen.vhd, 424, 299=1 fourier_func_gen.vhd, 501, 217=1
fourier_func_gen.vhd, 545, 357=1 fourier_register.vhd, 104, 231=1 fourier_register.vhd, 119, 335=1 fourier_register.vhd, 120, 262=1
fourier_register.vhd, 142, 262=1 fourier_register.vhd, 144, 290=1 fourier_register.vhd, 15, 252=1 fourier_register.vhd, 164, 276=1
fourier_register.vhd, 166, 309=1 fourier_register.vhd, 171, 294=1 fourier_register.vhd, 173, 320=1 fourier_register.vhd, 177, 206=1
fourier_register.vhd, 178, 491=1 fourier_register.vhd, 179, 295=1 fourier_register.vhd, 179, 298=1 fourier_register.vhd, 185, 329=1
fourier_register.vhd, 185, 338=1 fourier_register.vhd, 185, 360=1 fourier_register.vhd, 186, 166=1 fourier_register.vhd, 187, 332=1
fourier_register.vhd, 188, 281=1 fourier_register.vhd, 188, 345=1 fourier_register.vhd, 188, 347=1 fourier_register.vhd, 188, 365=1
fourier_register.vhd, 189, 298=1 fourier_register.vhd, 189, 421=1 fourier_register.vhd, 192, 308=1 fourier_register.vhd, 196, 308=1
fourier_register.vhd, 208, 111=1 fourier_register.vhd, 209, 297=1 fourier_register.vhd, 218, 322=1 fourier_register.vhd, 219, 147=1
fourier_register.vhd, 229, 402=1 fourier_register.vhd, 237, 260=1 fourier_register.vhd, 243, 347=1 fourier_register.vhd, 245, 161=1
fourier_register.vhd, 245, 57=1 fourier_register.vhd, 248, 125=1 fourier_register.vhd, 248, 176=1 fourier_register.vhd, 249, 285=1
fourier_register.vhd, 249, 78=1 fourier_register.vhd, 250, 163=1 fourier_register.vhd, 250, 165=1 fourier_register.vhd, 250, 196=1
fourier_register.vhd, 250, 314=1 fourier_register.vhd, 250, 382=1 fourier_register.vhd, 250, 58=1 fourier_register.vhd, 250, 94=1
fourier_register.vhd, 251, 129=1 fourier_register.vhd, 251, 145=1 fourier_register.vhd, 251, 96=1 fourier_register.vhd, 252, 126=1
fourier_register.vhd, 252, 127=1 fourier_register.vhd, 252, 128=1 fourier_register.vhd, 252, 214=1 fourier_register.vhd, 252, 98=1
fourier_register.vhd, 253, 113=1 fourier_register.vhd, 253, 126=1 fourier_register.vhd, 253, 146=1 fourier_register.vhd, 253, 176=1
fourier_register.vhd, 253, 99=1 fourier_register.vhd, 260, 384=1 fourier_register.vhd, 276, 179=1 fourier_register.vhd, 277, 397=1
fourier_register.vhd, 279, 281=1 fourier_register.vhd, 285, 471=1 fourier_register.vhd, 316, 368=1 fourier_register.vhd, 394, 217=2
fourier_register.vhd, 394, 217, false, false, false, false, true=1 fourier_register.vhd, 420, 436=1 fourier_register.vhd, 431, 286=1 fourier_register.vhd, 445, 277=1
fourier_register.vhd, 453, 267=1 fourier_register.vhd, 495, 195=1 fourier_register.vhd, 540, 211=1 fourier_register.vhd, 551, 211=1
fourier_register.vhd, 614, 249=2 fourier_register.vhd, 614, 249, false, false, false, false, true=1 fourier_register.vhd, 681, 215=1 fourier_register.vhd, 698, 210=1
fourier_register.vhd, 699, 232=1 fourier_register.vhd, 70, 228=1 fourier_register.vhd, 711, 225=1 fourier_register.vhd, 755, 247=1
fourier_register.vhd, 88, 285=1 gettingstartedview_open_project=3 hcodeeditor_search_text_combo_box=10 messagewithoptiondialog_dont_show_this_dialog_again=4
msgtreepanel_message_view_tree=21 msgview_warning_messages=3 pacommandnames_auto_connect_target=3 pacommandnames_auto_update_hier=1
pacommandnames_message_window=1 paresourceatod.cmdmsgdialog_ok, ok=2 paresourcecommand.pacommandnames_auto_connect_target, auto connect=1 paresourceetoh.filesetpanel_file_set_panel_tree, [root, design sources, fourier_func_gen - behavioral (fourier_func_gen.vhd=8
paresourceetoh.flownavigatortreepanel_flow_navigator_tree, [, program and debug, generate bitstream], 29, false, false, false, false, true, false=1 paresourceetoh.flownavigatortreepanel_flow_navigator_tree, [, program and debug, hardware manager, program device], 31, false=1 paresourceetoh.flownavigatortreepanel_flow_navigator_tree, [, program and debug, open hardware manager, open target], 31, false=1 paresourceetoh.flownavigatortreepanel_flow_navigator_tree, [, program and debug, open hardware manager, program device], 32, false=1
paresourceetoh.flownavigatortreepanel_flow_navigator_tree, [, program and debug, open hardware manager], 30=1 paresourceetoh.flownavigatortreepanel_flow_navigator_tree, [, program and debug, open hardware manager], 30, true, false, false, false, true, false=1 paresourceetoh.flownavigatortreepanel_flow_navigator_tree, [, rtl analysis, elaborated design], 14, true=1 paresourceiton.msgtreepanel_message_view_tree, [, rtl_1, refresh_design. , [synth 8-3493] module 'fourier_register' declared at 'c:/users/nmah/documents/github/cal-poly-slo-cpe-133/final_project_2/final_project_2.srcs/sources_1/new/fourier_register.vhd:34' does not have matching formal port for component port 'reg0_inv' [c:/users/nmah/documents/github/cal-poly-slo-cpe-133/final_project_2/final_project_2.srcs/sources_1/new/fourier_func_gen.vhd:128]. ], 2, true=1
paresourceiton.msgtreepanel_message_view_tree, [, rtl_1, refresh_design. , [synth 8-426] missing choice(s=1 paresourceiton.msgview_warning_messages, (string=1 paresourceotop.programfpgadialog_program, program=1 paresourceotop.projecttab_reload, reload=2
paviews_code=2 paviews_schematic=1 programdebugtab_open_target=2 programdebugtab_program_device=2
programfpgadialog_program=4 projecttab_reload=7 rdicommands_delete=1 rdiresource.basedialog_cancel, cancel=1
rungadget_show_error_and_critical_warning_messages=1 saveprojectutils_save=1 scaler.vhd, 165, 329=1 scaler.vhd, 210, 481=1
scaler.vhd, 27, 483=1 scaler.vhd, 308, 384=1 scaler.vhd, 406, 451=1 scaler.vhd, 422, 489=1
scaler.vhd, 529, 499=1 scaler.vhd, 534, 487=1 scaler.vhd, 593, 498=1 sincos_decoder.vhd, 1116, 351=1
sincos_decoder.vhd, 33, 316=1 sincos_decoder.vhd, 649, 353, true, false, false, false, false=1 srcmenu_ip_hierarchy=1 statemonitor_cancel=2
statemonitor_reset_run=1 statemonitor_reset_step=1
java_command_handlers
addsources=20 autoconnecttarget=9 coreview=1 createinterfacedefinitionhandler=1
customizecore=1 editdelete=13 editpaste=23 editredo=30
editundo=64 ippackagerwizardhandler=1 launchprogramfpga=53 newproject=1
opendesign=1 openexistingreport=4 openhardwaremanager=41 openproject=17
openrecenttarget=6 programdevice=18 projectsettingscmdhandler=12 refreshdevice=1
reloaddesign=2 runbitgen=70 runimplementation=53 runschematic=4
runsynthesis=48 savedesign=7 savefileproxyhandler=23 saveprojectas=4
setsourceenabled=2 settopnode=6 showsource=3 showview=60
simulationbreak=27 simulationclose=28 simulationrestart=52 simulationrun=104
simulationrunall=5 simulationrunfortime=139 toggleautofitselection=1 toolstemplates=1
ui.views.b.h.e=14 ui.views.c.h.e=13 viewtaskimplementation=11 viewtaskrtlanalysis=42
viewtasksynthesis=1 writecfgmemfile=1 zoomfit=7 zoomin=4
zoomout=6
other_data
guimode=15
project_data
constraintsetcount=1 core_container=false currentimplrun=impl_1 currentsynthesisrun=synth_1
default_library=xil_defaultlib designmode=RTL export_simulation_activehdl=1 export_simulation_ies=1
export_simulation_modelsim=1 export_simulation_questa=1 export_simulation_riviera=1 export_simulation_vcs=1
export_simulation_xsim=1 implstrategy=Vivado Implementation Defaults launch_simulation_activehdl=0 launch_simulation_ies=0
launch_simulation_modelsim=0 launch_simulation_questa=0 launch_simulation_riviera=0 launch_simulation_vcs=0
launch_simulation_xsim=111 simulator_language=Mixed srcsetcount=9 synthesisstrategy=Vivado Synthesis Defaults
target_language=VHDL target_simulator=XSim totalimplruns=1 totalsynthesisruns=1

unisim_transformation
post_unisim_transformation
bufg=3 carry4=155 dsp48e1=17 fdce=261
fdre=1159 fdse=4 gnd=33 ibuf=22
lut1=593 lut2=171 lut3=538 lut4=1292
lut5=3227 lut6=7176 muxf7=4026 muxf8=1802
obuf=29 vcc=31
pre_unisim_transformation
bufg=3 carry4=155 dsp48e1=17 fdce=261
fdre=1159 fdse=4 gnd=33 ibuf=22
lut1=593 lut2=171 lut3=538 lut4=1292
lut5=3227 lut6=7176 muxf7=4026 muxf8=1802
obuf=29 vcc=31

report_drc
command_line_options
-append=default::[not_specified] -checks=default::[not_specified] -fail_on=default::[not_specified] -force=default::[not_specified]
-format=default::[not_specified] -messages=default::[not_specified] -name=default::[not_specified] -return_string=default::[not_specified]
-ruledecks=default::[not_specified] -upgrade_cw=default::[not_specified]
results
cfgbvs-1=1 dpip-1=19 dpir-1=256 dpop-1=3
dpop-2=2

report_methodology
command_line_options
-append=default::[not_specified] -checks=default::[not_specified] -fail_on=default::[not_specified] -force=default::[not_specified]
-format=default::[not_specified] -messages=default::[not_specified] -name=default::[not_specified] -return_string=default::[not_specified]
results
synth-11=16 synth-13=1 timing-17=1000 timing-18=37

report_power
command_line_options
-advisory=default::[not_specified] -append=default::[not_specified] -file=[specified] -format=default::text
-hier=default::power -l=default::[not_specified] -name=default::[not_specified] -no_propagation=default::[not_specified]
-return_string=default::[not_specified] -rpx=[specified] -verbose=default::[not_specified] -vid=default::[not_specified]
-xpe=default::[not_specified]
usage
airflow=250 (LFM) ambient_temp=25.0 (C) bi-dir_toggle=12.500000 bidir_output_enable=1.000000
board_layers=12to15 (12 to 15 Layers) board_selection=medium (10"x10") clocks=0.003034 confidence_level_clock_activity=Low
confidence_level_design_state=High confidence_level_device_models=High confidence_level_internal_activity=Medium confidence_level_io_activity=Low
confidence_level_overall=Low customer=TBD customer_class=TBD devstatic=0.071815
die=xc7a35tcpg236-1 dsp=0.009619 dsp_output_toggle=12.500000 dynamic=0.054505
effective_thetaja=5.0 enable_probability=0.990000 family=artix7 ff_toggle=12.500000
flow_state=routed heatsink=medium (Medium Profile) i/o=0.038195 input_toggle=12.500000
junction_temp=25.6 (C) logic=0.001149 mgtavcc_dynamic_current=0.000000 mgtavcc_static_current=0.000000
mgtavcc_total_current=0.000000 mgtavcc_voltage=1.000000 mgtavtt_dynamic_current=0.000000 mgtavtt_static_current=0.000000
mgtavtt_total_current=0.000000 mgtavtt_voltage=1.200000 netlist_net_matched=NA off-chip_power=0.000000
on-chip_power=0.126320 output_enable=1.000000 output_load=5.000000 output_toggle=12.500000
package=cpg236 pct_clock_constrained=9.000000 pct_inputs_defined=4 platform=nt64
process=typical ram_enable=50.000000 ram_write=50.000000 read_saif=False
set/reset_probability=0.000000 signal_rate=False signals=0.002509 simulation_file=None
speedgrade=-1 static_prob=False temp_grade=commercial thetajb=7.5 (C/W)
thetasa=4.6 (C/W) toggle_rate=False user_board_temp=25.0 (C) user_effective_thetaja=5.0
user_junc_temp=25.6 (C) user_thetajb=7.5 (C/W) user_thetasa=4.6 (C/W) vccadc_dynamic_current=0.000000
vccadc_static_current=0.020000 vccadc_total_current=0.020000 vccadc_voltage=1.800000 vccaux_dynamic_current=0.001394
vccaux_io_dynamic_current=0.000000 vccaux_io_static_current=0.000000 vccaux_io_total_current=0.000000 vccaux_io_voltage=1.800000
vccaux_static_current=0.012622 vccaux_total_current=0.014016 vccaux_voltage=1.800000 vccbram_dynamic_current=0.000000
vccbram_static_current=0.000163 vccbram_total_current=0.000163 vccbram_voltage=1.000000 vccint_dynamic_current=0.016455
vccint_static_current=0.009633 vccint_total_current=0.026088 vccint_voltage=1.000000 vcco12_dynamic_current=0.000000
vcco12_static_current=0.000000 vcco12_total_current=0.000000 vcco12_voltage=1.200000 vcco135_dynamic_current=0.000000
vcco135_static_current=0.000000 vcco135_total_current=0.000000 vcco135_voltage=1.350000 vcco15_dynamic_current=0.000000
vcco15_static_current=0.000000 vcco15_total_current=0.000000 vcco15_voltage=1.500000 vcco18_dynamic_current=0.000000
vcco18_static_current=0.000000 vcco18_total_current=0.000000 vcco18_voltage=1.800000 vcco25_dynamic_current=0.000000
vcco25_static_current=0.000000 vcco25_total_current=0.000000 vcco25_voltage=2.500000 vcco33_dynamic_current=0.010770
vcco33_static_current=0.001000 vcco33_total_current=0.011770 vcco33_voltage=3.300000 version=2016.3

report_utilization
clocking
bufgctrl_available=32 bufgctrl_fixed=0 bufgctrl_used=3 bufgctrl_util_percentage=9.38
bufhce_available=72 bufhce_fixed=0 bufhce_used=0 bufhce_util_percentage=0.00
bufio_available=20 bufio_fixed=0 bufio_used=0 bufio_util_percentage=0.00
bufmrce_available=10 bufmrce_fixed=0 bufmrce_used=0 bufmrce_util_percentage=0.00
bufr_available=20 bufr_fixed=0 bufr_used=0 bufr_util_percentage=0.00
mmcme2_adv_available=5 mmcme2_adv_fixed=0 mmcme2_adv_used=0 mmcme2_adv_util_percentage=0.00
plle2_adv_available=5 plle2_adv_fixed=0 plle2_adv_used=0 plle2_adv_util_percentage=0.00
dsp
dsp48e1_only_used=17 dsps_available=90 dsps_fixed=0 dsps_used=17
dsps_util_percentage=18.89
io_standard
blvds_25=0 diff_hstl_i=0 diff_hstl_i_18=0 diff_hstl_ii=0
diff_hstl_ii_18=0 diff_hsul_12=0 diff_mobile_ddr=0 diff_sstl135=0
diff_sstl135_r=0 diff_sstl15=0 diff_sstl15_r=0 diff_sstl18_i=0
diff_sstl18_ii=0 hstl_i=0 hstl_i_18=0 hstl_ii=0
hstl_ii_18=0 hsul_12=0 lvcmos12=0 lvcmos15=0
lvcmos18=0 lvcmos25=0 lvcmos33=1 lvds_25=0
lvttl=0 mini_lvds_25=0 mobile_ddr=0 pci33_3=0
ppds_25=0 rsds_25=0 sstl135=0 sstl135_r=0
sstl15=0 sstl15_r=0 sstl18_i=0 sstl18_ii=0
tmds_33=0
memory
block_ram_tile_available=50 block_ram_tile_fixed=0 block_ram_tile_used=0 block_ram_tile_util_percentage=0.00
ramb18_available=100 ramb18_fixed=0 ramb18_used=0 ramb18_util_percentage=0.00
ramb36_fifo_available=50 ramb36_fifo_fixed=0 ramb36_fifo_used=0 ramb36_fifo_util_percentage=0.00
primitives
bufg_functional_category=Clock bufg_used=3 carry4_functional_category=CarryLogic carry4_used=155
dsp48e1_functional_category=Block Arithmetic dsp48e1_used=17 fdce_functional_category=Flop & Latch fdce_used=261
fdre_functional_category=Flop & Latch fdre_used=1159 fdse_functional_category=Flop & Latch fdse_used=4
ibuf_functional_category=IO ibuf_used=22 lut1_functional_category=LUT lut1_used=103
lut2_functional_category=LUT lut2_used=171 lut3_functional_category=LUT lut3_used=610
lut4_functional_category=LUT lut4_used=1292 lut5_functional_category=LUT lut5_used=3227
lut6_functional_category=LUT lut6_used=7176 muxf7_functional_category=MuxFx muxf7_used=3954
muxf8_functional_category=MuxFx muxf8_used=1802 obuf_functional_category=IO obuf_used=29
slice_logic
f7_muxes_available=16300 f7_muxes_fixed=0 f7_muxes_used=3954 f7_muxes_util_percentage=24.26
f8_muxes_available=8150 f8_muxes_fixed=0 f8_muxes_used=1802 f8_muxes_util_percentage=22.11
lut_as_logic_available=20800 lut_as_logic_fixed=0 lut_as_logic_used=11489 lut_as_logic_util_percentage=55.24
lut_as_memory_available=9600 lut_as_memory_fixed=0 lut_as_memory_used=0 lut_as_memory_util_percentage=0.00
register_as_flip_flop_available=41600 register_as_flip_flop_fixed=0 register_as_flip_flop_used=1424 register_as_flip_flop_util_percentage=3.42
register_as_latch_available=41600 register_as_latch_fixed=0 register_as_latch_used=0 register_as_latch_util_percentage=0.00
slice_luts_available=20800 slice_luts_fixed=0 slice_luts_used=11489 slice_luts_util_percentage=55.24
slice_registers_available=41600 slice_registers_fixed=0 slice_registers_used=1424 slice_registers_util_percentage=3.42
fully_used_lut_ff_pairs_fixed=3.42 fully_used_lut_ff_pairs_used=6 lut_as_distributed_ram_fixed=0 lut_as_distributed_ram_used=0
lut_as_logic_available=20800 lut_as_logic_fixed=0 lut_as_logic_used=11489 lut_as_logic_util_percentage=55.24
lut_as_memory_available=9600 lut_as_memory_fixed=0 lut_as_memory_used=0 lut_as_memory_util_percentage=0.00
lut_as_shift_register_fixed=0 lut_as_shift_register_used=0 lut_ff_pairs_with_one_unused_flip_flop_fixed=0 lut_ff_pairs_with_one_unused_flip_flop_used=261
lut_ff_pairs_with_one_unused_lut_output_fixed=261 lut_ff_pairs_with_one_unused_lut_output_used=284 lut_flip_flop_pairs_available=20800 lut_flip_flop_pairs_fixed=0
lut_flip_flop_pairs_used=291 lut_flip_flop_pairs_util_percentage=1.40 slice_available=8150 slice_fixed=0
slice_used=3232 slice_util_percentage=39.66 slicel_fixed=0 slicel_used=2221
slicem_fixed=0 slicem_used=1011 unique_control_sets_used=29 using_o5_and_o6_fixed=29
using_o5_and_o6_used=1090 using_o5_output_only_fixed=1090 using_o5_output_only_used=0 using_o6_output_only_fixed=0
using_o6_output_only_used=10399
specific_feature
bscane2_available=4 bscane2_fixed=0 bscane2_used=0 bscane2_util_percentage=0.00
capturee2_available=1 capturee2_fixed=0 capturee2_used=0 capturee2_util_percentage=0.00
dna_port_available=1 dna_port_fixed=0 dna_port_used=0 dna_port_util_percentage=0.00
efuse_usr_available=1 efuse_usr_fixed=0 efuse_usr_used=0 efuse_usr_util_percentage=0.00
frame_ecce2_available=1 frame_ecce2_fixed=0 frame_ecce2_used=0 frame_ecce2_util_percentage=0.00
icape2_available=2 icape2_fixed=0 icape2_used=0 icape2_util_percentage=0.00
pcie_2_1_available=1 pcie_2_1_fixed=0 pcie_2_1_used=0 pcie_2_1_util_percentage=0.00
startupe2_available=1 startupe2_fixed=0 startupe2_used=0 startupe2_util_percentage=0.00
xadc_available=1 xadc_fixed=0 xadc_used=0 xadc_util_percentage=0.00

router
usage
actual_expansions=5457248 bogomips=0 bram18=0 bram36=0
bufg=0 bufr=0 congestion_level=0 ctrls=29
dsp=17 effort=2 estimated_expansions=7664076 ff=1424
global_clocks=3 high_fanout_nets=3 iob=51 lut=12573
movable_instances=20049 nets=21349 pins=119408 pll=0
router_runtime=0.000000 router_timing_driven=1 threads=2 timing_constraints_exist=1

synthesis
command_line_options
-assert=default::[not_specified] -bufg=default::12 -cascade_dsp=default::auto -constrset=default::[not_specified]
-control_set_opt_threshold=default::auto -directive=default::default -fanout_limit=default::10000 -flatten_hierarchy=default::rebuilt
-fsm_extraction=default::auto -gated_clock_conversion=default::off -generic=default::[not_specified] -include_dirs=default::[not_specified]
-keep_equivalent_registers=default::[not_specified] -max_bram=default::-1 -max_bram_cascade_height=default::-1 -max_dsp=default::-1
-max_uram=default::-1 -max_uram_cascade_height=default::-1 -mode=default::default -name=default::[not_specified]
-no_lc=default::[not_specified] -no_srlextract=default::[not_specified] -no_timing_driven=default::[not_specified] -part=xc7a35tcpg236-1
-resource_sharing=default::auto -retiming=default::[not_specified] -rtl=default::[not_specified] -rtl_skip_constraints=default::[not_specified]
-rtl_skip_ip=default::[not_specified] -seu_protect=default::none -shreg_min_size=default::3 -top=Fourier_Func_Gen
-verilog_define=default::[not_specified]
usage
elapsed=00:05:21s hls_ip=0 memory_gain=771.410MB memory_peak=981.645MB

xsim
command_line_options
-sim_mode=default::behavioral -sim_type=default::