-- ==============================================================
-- RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2017.2
-- Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved.
-- 
-- ===========================================================

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;

entity design_1_v_frmbuf_wr_0_0_AXIvideo2MultiPixStr is
port (
    ap_clk : IN STD_LOGIC;
    ap_rst : IN STD_LOGIC;
    ap_start : IN STD_LOGIC;
    ap_done : OUT STD_LOGIC;
    ap_continue : IN STD_LOGIC;
    ap_idle : OUT STD_LOGIC;
    ap_ready : OUT STD_LOGIC;
    s_axis_video_TDATA : IN STD_LOGIC_VECTOR (23 downto 0);
    s_axis_video_TVALID : IN STD_LOGIC;
    s_axis_video_TREADY : OUT STD_LOGIC;
    s_axis_video_TKEEP : IN STD_LOGIC_VECTOR (2 downto 0);
    s_axis_video_TSTRB : IN STD_LOGIC_VECTOR (2 downto 0);
    s_axis_video_TUSER : IN STD_LOGIC_VECTOR (0 downto 0);
    s_axis_video_TLAST : IN STD_LOGIC_VECTOR (0 downto 0);
    s_axis_video_TID : IN STD_LOGIC_VECTOR (0 downto 0);
    s_axis_video_TDEST : IN STD_LOGIC_VECTOR (0 downto 0);
    img_V_val_0_V_din : OUT STD_LOGIC_VECTOR (7 downto 0);
    img_V_val_0_V_full_n : IN STD_LOGIC;
    img_V_val_0_V_write : OUT STD_LOGIC;
    img_V_val_1_V_din : OUT STD_LOGIC_VECTOR (7 downto 0);
    img_V_val_1_V_full_n : IN STD_LOGIC;
    img_V_val_1_V_write : OUT STD_LOGIC;
    img_V_val_2_V_din : OUT STD_LOGIC_VECTOR (7 downto 0);
    img_V_val_2_V_full_n : IN STD_LOGIC;
    img_V_val_2_V_write : OUT STD_LOGIC;
    HwReg_height_cast8_l_2_dout : IN STD_LOGIC_VECTOR (8 downto 0);
    HwReg_height_cast8_l_2_empty_n : IN STD_LOGIC;
    HwReg_height_cast8_l_2_read : OUT STD_LOGIC;
    HwReg_width_cast9_lo_1_dout : IN STD_LOGIC_VECTOR (9 downto 0);
    HwReg_width_cast9_lo_1_empty_n : IN STD_LOGIC;
    HwReg_width_cast9_lo_1_read : OUT STD_LOGIC;
    tmp_2_loc_channel : IN STD_LOGIC_VECTOR (1 downto 0);
    HwReg_height_cast8_l_1_din : OUT STD_LOGIC_VECTOR (8 downto 0);
    HwReg_height_cast8_l_1_full_n : IN STD_LOGIC;
    HwReg_height_cast8_l_1_write : OUT STD_LOGIC;
    HwReg_width_cast9_lo_din : OUT STD_LOGIC_VECTOR (9 downto 0);
    HwReg_width_cast9_lo_full_n : IN STD_LOGIC;
    HwReg_width_cast9_lo_write : OUT STD_LOGIC );
end;


architecture behav of design_1_v_frmbuf_wr_0_0_AXIvideo2MultiPixStr is 
    constant ap_const_logic_1 : STD_LOGIC := '1';
    constant ap_const_logic_0 : STD_LOGIC := '0';
    constant ap_ST_fsm_state1 : STD_LOGIC_VECTOR (8 downto 0) := "000000001";
    constant ap_ST_fsm_state2 : STD_LOGIC_VECTOR (8 downto 0) := "000000010";
    constant ap_ST_fsm_state3 : STD_LOGIC_VECTOR (8 downto 0) := "000000100";
    constant ap_ST_fsm_state4 : STD_LOGIC_VECTOR (8 downto 0) := "000001000";
    constant ap_ST_fsm_state5 : STD_LOGIC_VECTOR (8 downto 0) := "000010000";
    constant ap_ST_fsm_pp1_stage0 : STD_LOGIC_VECTOR (8 downto 0) := "000100000";
    constant ap_ST_fsm_state8 : STD_LOGIC_VECTOR (8 downto 0) := "001000000";
    constant ap_ST_fsm_pp2_stage0 : STD_LOGIC_VECTOR (8 downto 0) := "010000000";
    constant ap_ST_fsm_state11 : STD_LOGIC_VECTOR (8 downto 0) := "100000000";
    constant ap_const_lv32_0 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000000";
    constant ap_const_boolean_1 : BOOLEAN := true;
    constant ap_const_lv1_0 : STD_LOGIC_VECTOR (0 downto 0) := "0";
    constant ap_const_lv1_1 : STD_LOGIC_VECTOR (0 downto 0) := "1";
    constant ap_const_lv2_0 : STD_LOGIC_VECTOR (1 downto 0) := "00";
    constant ap_const_lv2_2 : STD_LOGIC_VECTOR (1 downto 0) := "10";
    constant ap_const_lv2_3 : STD_LOGIC_VECTOR (1 downto 0) := "11";
    constant ap_const_lv2_1 : STD_LOGIC_VECTOR (1 downto 0) := "01";
    constant ap_const_lv32_2 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000010";
    constant ap_const_lv32_5 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000101";
    constant ap_const_boolean_0 : BOOLEAN := false;
    constant ap_const_lv32_7 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000111";
    constant ap_const_lv32_1 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000001";
    constant ap_const_lv32_3 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000011";
    constant ap_const_lv32_4 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000100";
    constant ap_const_lv32_6 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000110";
    constant ap_const_lv32_8 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001000";
    constant ap_const_lv9_0 : STD_LOGIC_VECTOR (8 downto 0) := "000000000";
    constant ap_const_lv10_0 : STD_LOGIC_VECTOR (9 downto 0) := "0000000000";
    constant ap_const_lv9_1 : STD_LOGIC_VECTOR (8 downto 0) := "000000001";
    constant ap_const_lv10_1 : STD_LOGIC_VECTOR (9 downto 0) := "0000000001";
    constant ap_const_lv32_10 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000010000";
    constant ap_const_lv32_17 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000010111";
    constant ap_const_lv32_F : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001111";

    signal ap_done_reg : STD_LOGIC := '0';
    signal ap_CS_fsm : STD_LOGIC_VECTOR (8 downto 0) := "000000001";
    attribute fsm_encoding : string;
    attribute fsm_encoding of ap_CS_fsm : signal is "none";
    signal ap_CS_fsm_state1 : STD_LOGIC;
    attribute fsm_encoding of ap_CS_fsm_state1 : signal is "none";
    signal s_axis_video_V_data_V_0_data_out : STD_LOGIC_VECTOR (23 downto 0);
    signal s_axis_video_V_data_V_0_vld_in : STD_LOGIC;
    signal s_axis_video_V_data_V_0_vld_out : STD_LOGIC;
    signal s_axis_video_V_data_V_0_ack_in : STD_LOGIC;
    signal s_axis_video_V_data_V_0_ack_out : STD_LOGIC;
    signal s_axis_video_V_data_V_0_payload_A : STD_LOGIC_VECTOR (23 downto 0);
    signal s_axis_video_V_data_V_0_payload_B : STD_LOGIC_VECTOR (23 downto 0);
    signal s_axis_video_V_data_V_0_sel_rd : STD_LOGIC := '0';
    signal s_axis_video_V_data_V_0_sel_wr : STD_LOGIC := '0';
    signal s_axis_video_V_data_V_0_sel : STD_LOGIC;
    signal s_axis_video_V_data_V_0_load_A : STD_LOGIC;
    signal s_axis_video_V_data_V_0_load_B : STD_LOGIC;
    signal s_axis_video_V_data_V_0_state : STD_LOGIC_VECTOR (1 downto 0) := "00";
    signal s_axis_video_V_data_V_0_state_cmp_full : STD_LOGIC;
    signal s_axis_video_V_user_V_0_data_out : STD_LOGIC_VECTOR (0 downto 0);
    signal s_axis_video_V_user_V_0_vld_in : STD_LOGIC;
    signal s_axis_video_V_user_V_0_vld_out : STD_LOGIC;
    signal s_axis_video_V_user_V_0_ack_in : STD_LOGIC;
    signal s_axis_video_V_user_V_0_ack_out : STD_LOGIC;
    signal s_axis_video_V_user_V_0_payload_A : STD_LOGIC_VECTOR (0 downto 0);
    signal s_axis_video_V_user_V_0_payload_B : STD_LOGIC_VECTOR (0 downto 0);
    signal s_axis_video_V_user_V_0_sel_rd : STD_LOGIC := '0';
    signal s_axis_video_V_user_V_0_sel_wr : STD_LOGIC := '0';
    signal s_axis_video_V_user_V_0_sel : STD_LOGIC;
    signal s_axis_video_V_user_V_0_load_A : STD_LOGIC;
    signal s_axis_video_V_user_V_0_load_B : STD_LOGIC;
    signal s_axis_video_V_user_V_0_state : STD_LOGIC_VECTOR (1 downto 0) := "00";
    signal s_axis_video_V_user_V_0_state_cmp_full : STD_LOGIC;
    signal s_axis_video_V_last_V_0_data_out : STD_LOGIC_VECTOR (0 downto 0);
    signal s_axis_video_V_last_V_0_vld_in : STD_LOGIC;
    signal s_axis_video_V_last_V_0_vld_out : STD_LOGIC;
    signal s_axis_video_V_last_V_0_ack_in : STD_LOGIC;
    signal s_axis_video_V_last_V_0_ack_out : STD_LOGIC;
    signal s_axis_video_V_last_V_0_payload_A : STD_LOGIC_VECTOR (0 downto 0);
    signal s_axis_video_V_last_V_0_payload_B : STD_LOGIC_VECTOR (0 downto 0);
    signal s_axis_video_V_last_V_0_sel_rd : STD_LOGIC := '0';
    signal s_axis_video_V_last_V_0_sel_wr : STD_LOGIC := '0';
    signal s_axis_video_V_last_V_0_sel : STD_LOGIC;
    signal s_axis_video_V_last_V_0_load_A : STD_LOGIC;
    signal s_axis_video_V_last_V_0_load_B : STD_LOGIC;
    signal s_axis_video_V_last_V_0_state : STD_LOGIC_VECTOR (1 downto 0) := "00";
    signal s_axis_video_V_last_V_0_state_cmp_full : STD_LOGIC;
    signal s_axis_video_V_dest_V_0_vld_in : STD_LOGIC;
    signal s_axis_video_V_dest_V_0_ack_out : STD_LOGIC;
    signal s_axis_video_V_dest_V_0_state : STD_LOGIC_VECTOR (1 downto 0) := "00";
    signal s_axis_video_TDATA_blk_n : STD_LOGIC;
    signal ap_CS_fsm_state3 : STD_LOGIC;
    attribute fsm_encoding of ap_CS_fsm_state3 : signal is "none";
    signal ap_CS_fsm_pp1_stage0 : STD_LOGIC;
    attribute fsm_encoding of ap_CS_fsm_pp1_stage0 : signal is "none";
    signal ap_enable_reg_pp1_iter1 : STD_LOGIC := '0';
    signal ap_block_pp1_stage0_flag00000000 : BOOLEAN;
    signal exitcond6_i_i_i_reg_506 : STD_LOGIC_VECTOR (0 downto 0);
    signal brmerge_i_i_i_reg_515 : STD_LOGIC_VECTOR (0 downto 0);
    signal ap_CS_fsm_pp2_stage0 : STD_LOGIC;
    attribute fsm_encoding of ap_CS_fsm_pp2_stage0 : signal is "none";
    signal ap_enable_reg_pp2_iter1 : STD_LOGIC := '0';
    signal ap_block_pp2_stage0_flag00000000 : BOOLEAN;
    signal eol_2_i_i_i_reg_282 : STD_LOGIC_VECTOR (0 downto 0);
    signal img_V_val_0_V_blk_n : STD_LOGIC;
    signal img_V_val_1_V_blk_n : STD_LOGIC;
    signal img_V_val_2_V_blk_n : STD_LOGIC;
    signal HwReg_height_cast8_l_2_blk_n : STD_LOGIC;
    signal HwReg_width_cast9_lo_1_blk_n : STD_LOGIC;
    signal HwReg_height_cast8_l_1_blk_n : STD_LOGIC;
    signal HwReg_width_cast9_lo_blk_n : STD_LOGIC;
    signal eol_i_i_i_reg_212 : STD_LOGIC_VECTOR (0 downto 0);
    signal j_i_i_i_reg_224 : STD_LOGIC_VECTOR (9 downto 0);
    signal eol_reg_235 : STD_LOGIC_VECTOR (0 downto 0);
    signal axi_data_V_1_i_i_i_reg_246 : STD_LOGIC_VECTOR (23 downto 0);
    signal axi_last_V_3_i_i_i_reg_293 : STD_LOGIC_VECTOR (0 downto 0);
    signal axi_data_V_3_i_i_i_reg_305 : STD_LOGIC_VECTOR (23 downto 0);
    signal HwReg_width_cast9_lo_2_reg_445 : STD_LOGIC_VECTOR (9 downto 0);
    signal ap_block_state1 : BOOLEAN;
    signal Height_cast_i_i_i_fu_327_p1 : STD_LOGIC_VECTOR (9 downto 0);
    signal Height_cast_i_i_i_reg_450 : STD_LOGIC_VECTOR (9 downto 0);
    signal ap_CS_fsm_state2 : STD_LOGIC;
    attribute fsm_encoding of ap_CS_fsm_state2 : signal is "none";
    signal grp_reg_unsigned_short_s_fu_331_ap_done : STD_LOGIC;
    signal grp_reg_unsigned_short_s_fu_337_ap_done : STD_LOGIC;
    signal ap_block_state2_on_subcall_done : BOOLEAN;
    signal grp_reg_unsigned_short_s_fu_331_ap_return : STD_LOGIC_VECTOR (9 downto 0);
    signal tmp_i_i_i_reg_460 : STD_LOGIC_VECTOR (9 downto 0);
    signal grp_reg_unsigned_short_s_fu_337_ap_return : STD_LOGIC_VECTOR (9 downto 0);
    signal tmp_i_i_i_235_reg_465 : STD_LOGIC_VECTOR (9 downto 0);
    signal tmp_data_V_reg_470 : STD_LOGIC_VECTOR (23 downto 0);
    signal tmp_last_V_reg_478 : STD_LOGIC_VECTOR (0 downto 0);
    signal sel_tmp2_i_fu_347_p2 : STD_LOGIC_VECTOR (0 downto 0);
    signal sel_tmp2_i_reg_490 : STD_LOGIC_VECTOR (0 downto 0);
    signal ap_CS_fsm_state4 : STD_LOGIC;
    attribute fsm_encoding of ap_CS_fsm_state4 : signal is "none";
    signal exitcond5_i_i_i_fu_361_p2 : STD_LOGIC_VECTOR (0 downto 0);
    signal ap_CS_fsm_state5 : STD_LOGIC;
    attribute fsm_encoding of ap_CS_fsm_state5 : signal is "none";
    signal i_fu_366_p2 : STD_LOGIC_VECTOR (8 downto 0);
    signal i_reg_501 : STD_LOGIC_VECTOR (8 downto 0);
    signal exitcond6_i_i_i_fu_372_p2 : STD_LOGIC_VECTOR (0 downto 0);
    signal ap_block_state6_pp1_stage0_iter0 : BOOLEAN;
    signal ap_predicate_op80_read_state7 : BOOLEAN;
    signal img_V_val_0_V1_status : STD_LOGIC;
    signal ap_block_state7_pp1_stage0_iter1 : BOOLEAN;
    signal ap_block_pp1_stage0_flag00011001 : BOOLEAN;
    signal j_fu_377_p2 : STD_LOGIC_VECTOR (9 downto 0);
    signal ap_enable_reg_pp1_iter0 : STD_LOGIC := '0';
    signal brmerge_i_i_i_fu_386_p2 : STD_LOGIC_VECTOR (0 downto 0);
    signal ap_block_state9_pp2_stage0_iter0 : BOOLEAN;
    signal ap_block_state10_pp2_stage0_iter1 : BOOLEAN;
    signal ap_block_pp2_stage0_flag00011001 : BOOLEAN;
    signal ap_block_pp1_stage0_flag00011011 : BOOLEAN;
    signal ap_enable_reg_pp2_iter0 : STD_LOGIC := '0';
    signal ap_CS_fsm_state8 : STD_LOGIC;
    attribute fsm_encoding of ap_CS_fsm_state8 : signal is "none";
    signal ap_block_pp2_stage0_flag00011011 : BOOLEAN;
    signal eol_2_i_i_i_phi_fu_285_p4 : STD_LOGIC_VECTOR (0 downto 0);
    signal grp_reg_unsigned_short_s_fu_331_ap_start : STD_LOGIC;
    signal grp_reg_unsigned_short_s_fu_331_ap_idle : STD_LOGIC;
    signal grp_reg_unsigned_short_s_fu_331_ap_ready : STD_LOGIC;
    signal grp_reg_unsigned_short_s_fu_337_ap_start : STD_LOGIC;
    signal grp_reg_unsigned_short_s_fu_337_ap_idle : STD_LOGIC;
    signal grp_reg_unsigned_short_s_fu_337_ap_ready : STD_LOGIC;
    signal axi_last_V1_i_i_i_reg_181 : STD_LOGIC_VECTOR (0 downto 0);
    signal ap_CS_fsm_state11 : STD_LOGIC;
    attribute fsm_encoding of ap_CS_fsm_state11 : signal is "none";
    signal axi_data_V1_i_i_i_reg_191 : STD_LOGIC_VECTOR (23 downto 0);
    signal i_i_i_i_reg_201 : STD_LOGIC_VECTOR (8 downto 0);
    signal eol_i_i_i_phi_fu_216_p4 : STD_LOGIC_VECTOR (0 downto 0);
    signal axi_last_V_2_i_i_i_phi_fu_262_p4 : STD_LOGIC_VECTOR (0 downto 0);
    signal p_Val2_s_phi_fu_274_p4 : STD_LOGIC_VECTOR (23 downto 0);
    signal ap_phi_precharge_reg_pp1_iter1_axi_last_V_2_i_i_i_reg_257 : STD_LOGIC_VECTOR (0 downto 0);
    signal ap_phi_precharge_reg_pp1_iter1_p_Val2_s_reg_270 : STD_LOGIC_VECTOR (23 downto 0);
    signal ap_reg_grp_reg_unsigned_short_s_fu_331_ap_start : STD_LOGIC := '0';
    signal ap_block_state1_ignore_call21 : BOOLEAN;
    signal ap_reg_grp_reg_unsigned_short_s_fu_337_ap_start : STD_LOGIC := '0';
    signal ap_block_state1_ignore_call22 : BOOLEAN;
    signal img_V_val_0_V1_update : STD_LOGIC;
    signal ap_block_pp1_stage0_flag00001001 : BOOLEAN;
    signal sof_1_i_i_i_fu_112 : STD_LOGIC_VECTOR (0 downto 0);
    signal i_cast_i_i_i_fu_357_p1 : STD_LOGIC_VECTOR (9 downto 0);
    signal pix_val_2_V_fu_411_p4 : STD_LOGIC_VECTOR (7 downto 0);
    signal pix_val_0_V_fu_397_p4 : STD_LOGIC_VECTOR (7 downto 0);
    signal pix_val_1_V_8_fu_407_p1 : STD_LOGIC_VECTOR (7 downto 0);
    signal tmp_user_V_fu_343_p1 : STD_LOGIC_VECTOR (0 downto 0);
    signal ap_NS_fsm : STD_LOGIC_VECTOR (8 downto 0);
    signal ap_idle_pp1 : STD_LOGIC;
    signal ap_enable_pp1 : STD_LOGIC;
    signal ap_idle_pp2 : STD_LOGIC;
    signal ap_enable_pp2 : STD_LOGIC;
    signal ap_condition_511 : BOOLEAN;

    component design_1_v_frmbuf_wr_0_0_reg_unsigned_short_s IS
    port (
        ap_clk : IN STD_LOGIC;
        ap_rst : IN STD_LOGIC;
        ap_start : IN STD_LOGIC;
        ap_done : OUT STD_LOGIC;
        ap_idle : OUT STD_LOGIC;
        ap_ready : OUT STD_LOGIC;
        in_r : IN STD_LOGIC_VECTOR (9 downto 0);
        ap_return : OUT STD_LOGIC_VECTOR (9 downto 0) );
    end component;



begin
    grp_reg_unsigned_short_s_fu_331 : component design_1_v_frmbuf_wr_0_0_reg_unsigned_short_s
    port map (
        ap_clk => ap_clk,
        ap_rst => ap_rst,
        ap_start => grp_reg_unsigned_short_s_fu_331_ap_start,
        ap_done => grp_reg_unsigned_short_s_fu_331_ap_done,
        ap_idle => grp_reg_unsigned_short_s_fu_331_ap_idle,
        ap_ready => grp_reg_unsigned_short_s_fu_331_ap_ready,
        in_r => Height_cast_i_i_i_reg_450,
        ap_return => grp_reg_unsigned_short_s_fu_331_ap_return);

    grp_reg_unsigned_short_s_fu_337 : component design_1_v_frmbuf_wr_0_0_reg_unsigned_short_s
    port map (
        ap_clk => ap_clk,
        ap_rst => ap_rst,
        ap_start => grp_reg_unsigned_short_s_fu_337_ap_start,
        ap_done => grp_reg_unsigned_short_s_fu_337_ap_done,
        ap_idle => grp_reg_unsigned_short_s_fu_337_ap_idle,
        ap_ready => grp_reg_unsigned_short_s_fu_337_ap_ready,
        in_r => HwReg_width_cast9_lo_2_reg_445,
        ap_return => grp_reg_unsigned_short_s_fu_337_ap_return);





    ap_CS_fsm_assign_proc : process(ap_clk)
    begin
        if (ap_clk'event and ap_clk =  '1') then
            if (ap_rst = '1') then
                ap_CS_fsm <= ap_ST_fsm_state1;
            else
                ap_CS_fsm <= ap_NS_fsm;
            end if;
        end if;
    end process;


    ap_done_reg_assign_proc : process(ap_clk)
    begin
        if (ap_clk'event and ap_clk =  '1') then
            if (ap_rst = '1') then
                ap_done_reg <= ap_const_logic_0;
            else
                if ((ap_const_logic_1 = ap_continue)) then 
                    ap_done_reg <= ap_const_logic_0;
                elsif (((ap_const_logic_1 = ap_CS_fsm_state5) and (ap_const_lv1_1 = exitcond5_i_i_i_fu_361_p2))) then 
                    ap_done_reg <= ap_const_logic_1;
                end if; 
            end if;
        end if;
    end process;


    ap_enable_reg_pp1_iter0_assign_proc : process(ap_clk)
    begin
        if (ap_clk'event and ap_clk =  '1') then
            if (ap_rst = '1') then
                ap_enable_reg_pp1_iter0 <= ap_const_logic_0;
            else
                if (((ap_const_logic_1 = ap_CS_fsm_pp1_stage0) and (ap_block_pp1_stage0_flag00011011 = ap_const_boolean_0) and (ap_const_lv1_1 = exitcond6_i_i_i_fu_372_p2))) then 
                    ap_enable_reg_pp1_iter0 <= ap_const_logic_0;
                elsif (((ap_const_logic_1 = ap_CS_fsm_state5) and (ap_const_lv1_0 = exitcond5_i_i_i_fu_361_p2))) then 
                    ap_enable_reg_pp1_iter0 <= ap_const_logic_1;
                end if; 
            end if;
        end if;
    end process;


    ap_enable_reg_pp1_iter1_assign_proc : process(ap_clk)
    begin
        if (ap_clk'event and ap_clk =  '1') then
            if (ap_rst = '1') then
                ap_enable_reg_pp1_iter1 <= ap_const_logic_0;
            else
                if ((ap_block_pp1_stage0_flag00011011 = ap_const_boolean_0)) then 
                    ap_enable_reg_pp1_iter1 <= ap_enable_reg_pp1_iter0;
                elsif (((ap_const_logic_1 = ap_CS_fsm_state5) and (ap_const_lv1_0 = exitcond5_i_i_i_fu_361_p2))) then 
                    ap_enable_reg_pp1_iter1 <= ap_const_logic_0;
                end if; 
            end if;
        end if;
    end process;


    ap_enable_reg_pp2_iter0_assign_proc : process(ap_clk)
    begin
        if (ap_clk'event and ap_clk =  '1') then
            if (ap_rst = '1') then
                ap_enable_reg_pp2_iter0 <= ap_const_logic_0;
            else
                if (((ap_const_logic_1 = ap_CS_fsm_pp2_stage0) and (ap_block_pp2_stage0_flag00011011 = ap_const_boolean_0) and (ap_const_lv1_1 = eol_2_i_i_i_phi_fu_285_p4))) then 
                    ap_enable_reg_pp2_iter0 <= ap_const_logic_0;
                elsif ((ap_const_logic_1 = ap_CS_fsm_state8)) then 
                    ap_enable_reg_pp2_iter0 <= ap_const_logic_1;
                end if; 
            end if;
        end if;
    end process;


    ap_enable_reg_pp2_iter1_assign_proc : process(ap_clk)
    begin
        if (ap_clk'event and ap_clk =  '1') then
            if (ap_rst = '1') then
                ap_enable_reg_pp2_iter1 <= ap_const_logic_0;
            else
                if ((ap_block_pp2_stage0_flag00011011 = ap_const_boolean_0)) then 
                    ap_enable_reg_pp2_iter1 <= ap_enable_reg_pp2_iter0;
                elsif ((ap_const_logic_1 = ap_CS_fsm_state8)) then 
                    ap_enable_reg_pp2_iter1 <= ap_const_logic_0;
                end if; 
            end if;
        end if;
    end process;


    ap_reg_grp_reg_unsigned_short_s_fu_331_ap_start_assign_proc : process(ap_clk)
    begin
        if (ap_clk'event and ap_clk =  '1') then
            if (ap_rst = '1') then
                ap_reg_grp_reg_unsigned_short_s_fu_331_ap_start <= ap_const_logic_0;
            else
                if (((ap_const_logic_1 = ap_CS_fsm_state1) and not(((ap_const_logic_0 = ap_start) or (ap_done_reg = ap_const_logic_1) or (ap_const_logic_0 = HwReg_height_cast8_l_2_empty_n) or (ap_const_logic_0 = HwReg_width_cast9_lo_1_empty_n) or (ap_const_logic_0 = HwReg_height_cast8_l_1_full_n) or (ap_const_logic_0 = HwReg_width_cast9_lo_full_n))))) then 
                    ap_reg_grp_reg_unsigned_short_s_fu_331_ap_start <= ap_const_logic_1;
                elsif ((ap_const_logic_1 = grp_reg_unsigned_short_s_fu_331_ap_ready)) then 
                    ap_reg_grp_reg_unsigned_short_s_fu_331_ap_start <= ap_const_logic_0;
                end if; 
            end if;
        end if;
    end process;


    ap_reg_grp_reg_unsigned_short_s_fu_337_ap_start_assign_proc : process(ap_clk)
    begin
        if (ap_clk'event and ap_clk =  '1') then
            if (ap_rst = '1') then
                ap_reg_grp_reg_unsigned_short_s_fu_337_ap_start <= ap_const_logic_0;
            else
                if (((ap_const_logic_1 = ap_CS_fsm_state1) and not(((ap_const_logic_0 = ap_start) or (ap_done_reg = ap_const_logic_1) or (ap_const_logic_0 = HwReg_height_cast8_l_2_empty_n) or (ap_const_logic_0 = HwReg_width_cast9_lo_1_empty_n) or (ap_const_logic_0 = HwReg_height_cast8_l_1_full_n) or (ap_const_logic_0 = HwReg_width_cast9_lo_full_n))))) then 
                    ap_reg_grp_reg_unsigned_short_s_fu_337_ap_start <= ap_const_logic_1;
                elsif ((ap_const_logic_1 = grp_reg_unsigned_short_s_fu_337_ap_ready)) then 
                    ap_reg_grp_reg_unsigned_short_s_fu_337_ap_start <= ap_const_logic_0;
                end if; 
            end if;
        end if;
    end process;


    s_axis_video_V_data_V_0_sel_rd_assign_proc : process(ap_clk)
    begin
        if (ap_clk'event and ap_clk =  '1') then
            if (ap_rst = '1') then
                s_axis_video_V_data_V_0_sel_rd <= ap_const_logic_0;
            else
                if (((ap_const_logic_1 = s_axis_video_V_data_V_0_ack_out) and (ap_const_logic_1 = s_axis_video_V_data_V_0_vld_out))) then 
                                        s_axis_video_V_data_V_0_sel_rd <= not(s_axis_video_V_data_V_0_sel_rd);
                end if; 
            end if;
        end if;
    end process;


    s_axis_video_V_data_V_0_sel_wr_assign_proc : process(ap_clk)
    begin
        if (ap_clk'event and ap_clk =  '1') then
            if (ap_rst = '1') then
                s_axis_video_V_data_V_0_sel_wr <= ap_const_logic_0;
            else
                if (((ap_const_logic_1 = s_axis_video_V_data_V_0_vld_in) and (ap_const_logic_1 = s_axis_video_V_data_V_0_ack_in))) then 
                                        s_axis_video_V_data_V_0_sel_wr <= not(s_axis_video_V_data_V_0_sel_wr);
                end if; 
            end if;
        end if;
    end process;


    s_axis_video_V_data_V_0_state_assign_proc : process(ap_clk)
    begin
        if (ap_clk'event and ap_clk =  '1') then
            if (ap_rst = '1') then
                s_axis_video_V_data_V_0_state <= ap_const_lv2_0;
            else
                if ((((ap_const_logic_0 = s_axis_video_V_data_V_0_vld_in) and (ap_const_logic_1 = s_axis_video_V_data_V_0_ack_out) and (s_axis_video_V_data_V_0_state = ap_const_lv2_3)) or ((ap_const_logic_0 = s_axis_video_V_data_V_0_vld_in) and (s_axis_video_V_data_V_0_state = ap_const_lv2_2)))) then 
                    s_axis_video_V_data_V_0_state <= ap_const_lv2_2;
                elsif ((((ap_const_logic_1 = s_axis_video_V_data_V_0_vld_in) and (ap_const_logic_0 = s_axis_video_V_data_V_0_ack_out) and (s_axis_video_V_data_V_0_state = ap_const_lv2_3)) or ((ap_const_logic_0 = s_axis_video_V_data_V_0_ack_out) and (s_axis_video_V_data_V_0_state = ap_const_lv2_1)))) then 
                    s_axis_video_V_data_V_0_state <= ap_const_lv2_1;
                elsif ((((ap_const_logic_1 = s_axis_video_V_data_V_0_vld_in) and (s_axis_video_V_data_V_0_state = ap_const_lv2_2)) or ((ap_const_logic_1 = s_axis_video_V_data_V_0_ack_out) and (s_axis_video_V_data_V_0_state = ap_const_lv2_1)) or ((s_axis_video_V_data_V_0_state = ap_const_lv2_3) and not(((ap_const_logic_1 = s_axis_video_V_data_V_0_vld_in) and (ap_const_logic_0 = s_axis_video_V_data_V_0_ack_out))) and not(((ap_const_logic_0 = s_axis_video_V_data_V_0_vld_in) and (ap_const_logic_1 = s_axis_video_V_data_V_0_ack_out)))))) then 
                    s_axis_video_V_data_V_0_state <= ap_const_lv2_3;
                else 
                    s_axis_video_V_data_V_0_state <= ap_const_lv2_2;
                end if; 
            end if;
        end if;
    end process;


    s_axis_video_V_dest_V_0_state_assign_proc : process(ap_clk)
    begin
        if (ap_clk'event and ap_clk =  '1') then
            if (ap_rst = '1') then
                s_axis_video_V_dest_V_0_state <= ap_const_lv2_0;
            else
                if ((((ap_const_logic_0 = s_axis_video_V_dest_V_0_vld_in) and (ap_const_logic_1 = s_axis_video_V_dest_V_0_ack_out) and (ap_const_lv2_3 = s_axis_video_V_dest_V_0_state)) or ((ap_const_logic_0 = s_axis_video_V_dest_V_0_vld_in) and (ap_const_lv2_2 = s_axis_video_V_dest_V_0_state)))) then 
                    s_axis_video_V_dest_V_0_state <= ap_const_lv2_2;
                elsif ((((ap_const_logic_1 = s_axis_video_V_dest_V_0_vld_in) and (ap_const_logic_0 = s_axis_video_V_dest_V_0_ack_out) and (ap_const_lv2_3 = s_axis_video_V_dest_V_0_state)) or ((ap_const_logic_0 = s_axis_video_V_dest_V_0_ack_out) and (ap_const_lv2_1 = s_axis_video_V_dest_V_0_state)))) then 
                    s_axis_video_V_dest_V_0_state <= ap_const_lv2_1;
                elsif ((((ap_const_logic_1 = s_axis_video_V_dest_V_0_vld_in) and (ap_const_lv2_2 = s_axis_video_V_dest_V_0_state)) or ((ap_const_logic_1 = s_axis_video_V_dest_V_0_ack_out) and (ap_const_lv2_1 = s_axis_video_V_dest_V_0_state)) or ((ap_const_lv2_3 = s_axis_video_V_dest_V_0_state) and not(((ap_const_logic_1 = s_axis_video_V_dest_V_0_vld_in) and (ap_const_logic_0 = s_axis_video_V_dest_V_0_ack_out))) and not(((ap_const_logic_0 = s_axis_video_V_dest_V_0_vld_in) and (ap_const_logic_1 = s_axis_video_V_dest_V_0_ack_out)))))) then 
                    s_axis_video_V_dest_V_0_state <= ap_const_lv2_3;
                else 
                    s_axis_video_V_dest_V_0_state <= ap_const_lv2_2;
                end if; 
            end if;
        end if;
    end process;


    s_axis_video_V_last_V_0_sel_rd_assign_proc : process(ap_clk)
    begin
        if (ap_clk'event and ap_clk =  '1') then
            if (ap_rst = '1') then
                s_axis_video_V_last_V_0_sel_rd <= ap_const_logic_0;
            else
                if (((ap_const_logic_1 = s_axis_video_V_last_V_0_ack_out) and (ap_const_logic_1 = s_axis_video_V_last_V_0_vld_out))) then 
                                        s_axis_video_V_last_V_0_sel_rd <= not(s_axis_video_V_last_V_0_sel_rd);
                end if; 
            end if;
        end if;
    end process;


    s_axis_video_V_last_V_0_sel_wr_assign_proc : process(ap_clk)
    begin
        if (ap_clk'event and ap_clk =  '1') then
            if (ap_rst = '1') then
                s_axis_video_V_last_V_0_sel_wr <= ap_const_logic_0;
            else
                if (((ap_const_logic_1 = s_axis_video_V_last_V_0_vld_in) and (ap_const_logic_1 = s_axis_video_V_last_V_0_ack_in))) then 
                                        s_axis_video_V_last_V_0_sel_wr <= not(s_axis_video_V_last_V_0_sel_wr);
                end if; 
            end if;
        end if;
    end process;


    s_axis_video_V_last_V_0_state_assign_proc : process(ap_clk)
    begin
        if (ap_clk'event and ap_clk =  '1') then
            if (ap_rst = '1') then
                s_axis_video_V_last_V_0_state <= ap_const_lv2_0;
            else
                if ((((ap_const_logic_0 = s_axis_video_V_last_V_0_vld_in) and (ap_const_logic_1 = s_axis_video_V_last_V_0_ack_out) and (ap_const_lv2_3 = s_axis_video_V_last_V_0_state)) or ((ap_const_logic_0 = s_axis_video_V_last_V_0_vld_in) and (ap_const_lv2_2 = s_axis_video_V_last_V_0_state)))) then 
                    s_axis_video_V_last_V_0_state <= ap_const_lv2_2;
                elsif ((((ap_const_logic_1 = s_axis_video_V_last_V_0_vld_in) and (ap_const_logic_0 = s_axis_video_V_last_V_0_ack_out) and (ap_const_lv2_3 = s_axis_video_V_last_V_0_state)) or ((ap_const_logic_0 = s_axis_video_V_last_V_0_ack_out) and (ap_const_lv2_1 = s_axis_video_V_last_V_0_state)))) then 
                    s_axis_video_V_last_V_0_state <= ap_const_lv2_1;
                elsif ((((ap_const_logic_1 = s_axis_video_V_last_V_0_vld_in) and (ap_const_lv2_2 = s_axis_video_V_last_V_0_state)) or ((ap_const_logic_1 = s_axis_video_V_last_V_0_ack_out) and (ap_const_lv2_1 = s_axis_video_V_last_V_0_state)) or ((ap_const_lv2_3 = s_axis_video_V_last_V_0_state) and not(((ap_const_logic_1 = s_axis_video_V_last_V_0_vld_in) and (ap_const_logic_0 = s_axis_video_V_last_V_0_ack_out))) and not(((ap_const_logic_0 = s_axis_video_V_last_V_0_vld_in) and (ap_const_logic_1 = s_axis_video_V_last_V_0_ack_out)))))) then 
                    s_axis_video_V_last_V_0_state <= ap_const_lv2_3;
                else 
                    s_axis_video_V_last_V_0_state <= ap_const_lv2_2;
                end if; 
            end if;
        end if;
    end process;


    s_axis_video_V_user_V_0_sel_rd_assign_proc : process(ap_clk)
    begin
        if (ap_clk'event and ap_clk =  '1') then
            if (ap_rst = '1') then
                s_axis_video_V_user_V_0_sel_rd <= ap_const_logic_0;
            else
                if (((ap_const_logic_1 = s_axis_video_V_user_V_0_ack_out) and (ap_const_logic_1 = s_axis_video_V_user_V_0_vld_out))) then 
                                        s_axis_video_V_user_V_0_sel_rd <= not(s_axis_video_V_user_V_0_sel_rd);
                end if; 
            end if;
        end if;
    end process;


    s_axis_video_V_user_V_0_sel_wr_assign_proc : process(ap_clk)
    begin
        if (ap_clk'event and ap_clk =  '1') then
            if (ap_rst = '1') then
                s_axis_video_V_user_V_0_sel_wr <= ap_const_logic_0;
            else
                if (((ap_const_logic_1 = s_axis_video_V_user_V_0_vld_in) and (ap_const_logic_1 = s_axis_video_V_user_V_0_ack_in))) then 
                                        s_axis_video_V_user_V_0_sel_wr <= not(s_axis_video_V_user_V_0_sel_wr);
                end if; 
            end if;
        end if;
    end process;


    s_axis_video_V_user_V_0_state_assign_proc : process(ap_clk)
    begin
        if (ap_clk'event and ap_clk =  '1') then
            if (ap_rst = '1') then
                s_axis_video_V_user_V_0_state <= ap_const_lv2_0;
            else
                if ((((ap_const_logic_0 = s_axis_video_V_user_V_0_vld_in) and (ap_const_logic_1 = s_axis_video_V_user_V_0_ack_out) and (ap_const_lv2_3 = s_axis_video_V_user_V_0_state)) or ((ap_const_logic_0 = s_axis_video_V_user_V_0_vld_in) and (ap_const_lv2_2 = s_axis_video_V_user_V_0_state)))) then 
                    s_axis_video_V_user_V_0_state <= ap_const_lv2_2;
                elsif ((((ap_const_logic_1 = s_axis_video_V_user_V_0_vld_in) and (ap_const_logic_0 = s_axis_video_V_user_V_0_ack_out) and (ap_const_lv2_3 = s_axis_video_V_user_V_0_state)) or ((ap_const_logic_0 = s_axis_video_V_user_V_0_ack_out) and (ap_const_lv2_1 = s_axis_video_V_user_V_0_state)))) then 
                    s_axis_video_V_user_V_0_state <= ap_const_lv2_1;
                elsif ((((ap_const_logic_1 = s_axis_video_V_user_V_0_vld_in) and (ap_const_lv2_2 = s_axis_video_V_user_V_0_state)) or ((ap_const_logic_1 = s_axis_video_V_user_V_0_ack_out) and (ap_const_lv2_1 = s_axis_video_V_user_V_0_state)) or ((ap_const_lv2_3 = s_axis_video_V_user_V_0_state) and not(((ap_const_logic_1 = s_axis_video_V_user_V_0_vld_in) and (ap_const_logic_0 = s_axis_video_V_user_V_0_ack_out))) and not(((ap_const_logic_0 = s_axis_video_V_user_V_0_vld_in) and (ap_const_logic_1 = s_axis_video_V_user_V_0_ack_out)))))) then 
                    s_axis_video_V_user_V_0_state <= ap_const_lv2_3;
                else 
                    s_axis_video_V_user_V_0_state <= ap_const_lv2_2;
                end if; 
            end if;
        end if;
    end process;


    axi_data_V1_i_i_i_reg_191_assign_proc : process (ap_clk)
    begin
        if (ap_clk'event and ap_clk = '1') then
            if ((ap_const_logic_1 = ap_CS_fsm_state4)) then 
                axi_data_V1_i_i_i_reg_191 <= tmp_data_V_reg_470;
            elsif ((ap_const_logic_1 = ap_CS_fsm_state11)) then 
                axi_data_V1_i_i_i_reg_191 <= axi_data_V_3_i_i_i_reg_305;
            end if; 
        end if;
    end process;

    axi_data_V_1_i_i_i_reg_246_assign_proc : process (ap_clk)
    begin
        if (ap_clk'event and ap_clk = '1') then
            if (((ap_const_logic_1 = ap_CS_fsm_pp1_stage0) and (ap_const_logic_1 = ap_enable_reg_pp1_iter1) and (ap_const_lv1_0 = exitcond6_i_i_i_reg_506) and (ap_block_pp1_stage0_flag00011001 = ap_const_boolean_0))) then 
                axi_data_V_1_i_i_i_reg_246 <= p_Val2_s_phi_fu_274_p4;
            elsif (((ap_const_logic_1 = ap_CS_fsm_state5) and (ap_const_lv1_0 = exitcond5_i_i_i_fu_361_p2))) then 
                axi_data_V_1_i_i_i_reg_246 <= axi_data_V1_i_i_i_reg_191;
            end if; 
        end if;
    end process;

    axi_data_V_3_i_i_i_reg_305_assign_proc : process (ap_clk)
    begin
        if (ap_clk'event and ap_clk = '1') then
            if ((ap_const_logic_1 = ap_CS_fsm_state8)) then 
                axi_data_V_3_i_i_i_reg_305 <= axi_data_V_1_i_i_i_reg_246;
            elsif (((ap_const_logic_1 = ap_CS_fsm_pp2_stage0) and (ap_const_logic_1 = ap_enable_reg_pp2_iter1) and (ap_const_lv1_0 = eol_2_i_i_i_reg_282) and (ap_block_pp2_stage0_flag00011001 = ap_const_boolean_0))) then 
                axi_data_V_3_i_i_i_reg_305 <= s_axis_video_V_data_V_0_data_out;
            end if; 
        end if;
    end process;

    axi_last_V1_i_i_i_reg_181_assign_proc : process (ap_clk)
    begin
        if (ap_clk'event and ap_clk = '1') then
            if ((ap_const_logic_1 = ap_CS_fsm_state4)) then 
                axi_last_V1_i_i_i_reg_181 <= tmp_last_V_reg_478;
            elsif ((ap_const_logic_1 = ap_CS_fsm_state11)) then 
                axi_last_V1_i_i_i_reg_181 <= axi_last_V_3_i_i_i_reg_293;
            end if; 
        end if;
    end process;

    axi_last_V_3_i_i_i_reg_293_assign_proc : process (ap_clk)
    begin
        if (ap_clk'event and ap_clk = '1') then
            if ((ap_const_logic_1 = ap_CS_fsm_state8)) then 
                axi_last_V_3_i_i_i_reg_293 <= eol_reg_235;
            elsif (((ap_const_logic_1 = ap_CS_fsm_pp2_stage0) and (ap_const_logic_1 = ap_enable_reg_pp2_iter1) and (ap_const_lv1_0 = eol_2_i_i_i_reg_282) and (ap_block_pp2_stage0_flag00011001 = ap_const_boolean_0))) then 
                axi_last_V_3_i_i_i_reg_293 <= s_axis_video_V_last_V_0_data_out;
            end if; 
        end if;
    end process;

    eol_2_i_i_i_reg_282_assign_proc : process (ap_clk)
    begin
        if (ap_clk'event and ap_clk = '1') then
            if ((ap_const_logic_1 = ap_CS_fsm_state8)) then 
                eol_2_i_i_i_reg_282 <= eol_i_i_i_reg_212;
            elsif (((ap_const_logic_1 = ap_CS_fsm_pp2_stage0) and (ap_const_logic_1 = ap_enable_reg_pp2_iter1) and (ap_const_lv1_0 = eol_2_i_i_i_reg_282) and (ap_block_pp2_stage0_flag00011001 = ap_const_boolean_0))) then 
                eol_2_i_i_i_reg_282 <= s_axis_video_V_last_V_0_data_out;
            end if; 
        end if;
    end process;

    eol_i_i_i_reg_212_assign_proc : process (ap_clk)
    begin
        if (ap_clk'event and ap_clk = '1') then
            if (((ap_const_logic_1 = ap_CS_fsm_pp1_stage0) and (ap_const_logic_1 = ap_enable_reg_pp1_iter1) and (ap_const_lv1_0 = exitcond6_i_i_i_reg_506) and (ap_block_pp1_stage0_flag00011001 = ap_const_boolean_0))) then 
                eol_i_i_i_reg_212 <= axi_last_V_2_i_i_i_phi_fu_262_p4;
            elsif (((ap_const_logic_1 = ap_CS_fsm_state5) and (ap_const_lv1_0 = exitcond5_i_i_i_fu_361_p2))) then 
                eol_i_i_i_reg_212 <= ap_const_lv1_0;
            end if; 
        end if;
    end process;

    eol_reg_235_assign_proc : process (ap_clk)
    begin
        if (ap_clk'event and ap_clk = '1') then
            if (((ap_const_logic_1 = ap_CS_fsm_pp1_stage0) and (ap_const_logic_1 = ap_enable_reg_pp1_iter1) and (ap_const_lv1_0 = exitcond6_i_i_i_reg_506) and (ap_block_pp1_stage0_flag00011001 = ap_const_boolean_0))) then 
                eol_reg_235 <= axi_last_V_2_i_i_i_phi_fu_262_p4;
            elsif (((ap_const_logic_1 = ap_CS_fsm_state5) and (ap_const_lv1_0 = exitcond5_i_i_i_fu_361_p2))) then 
                eol_reg_235 <= axi_last_V1_i_i_i_reg_181;
            end if; 
        end if;
    end process;

    i_i_i_i_reg_201_assign_proc : process (ap_clk)
    begin
        if (ap_clk'event and ap_clk = '1') then
            if ((ap_const_logic_1 = ap_CS_fsm_state4)) then 
                i_i_i_i_reg_201 <= ap_const_lv9_0;
            elsif ((ap_const_logic_1 = ap_CS_fsm_state11)) then 
                i_i_i_i_reg_201 <= i_reg_501;
            end if; 
        end if;
    end process;

    j_i_i_i_reg_224_assign_proc : process (ap_clk)
    begin
        if (ap_clk'event and ap_clk = '1') then
            if (((ap_const_logic_1 = ap_CS_fsm_pp1_stage0) and (ap_block_pp1_stage0_flag00011001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp1_iter0) and (ap_const_lv1_0 = exitcond6_i_i_i_fu_372_p2))) then 
                j_i_i_i_reg_224 <= j_fu_377_p2;
            elsif (((ap_const_logic_1 = ap_CS_fsm_state5) and (ap_const_lv1_0 = exitcond5_i_i_i_fu_361_p2))) then 
                j_i_i_i_reg_224 <= ap_const_lv10_0;
            end if; 
        end if;
    end process;

    sof_1_i_i_i_fu_112_assign_proc : process (ap_clk)
    begin
        if (ap_clk'event and ap_clk = '1') then
            if (((ap_const_logic_1 = ap_CS_fsm_pp1_stage0) and (ap_block_pp1_stage0_flag00011001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp1_iter0) and (ap_const_lv1_0 = exitcond6_i_i_i_fu_372_p2))) then 
                sof_1_i_i_i_fu_112 <= ap_const_lv1_0;
            elsif ((ap_const_logic_1 = ap_CS_fsm_state4)) then 
                sof_1_i_i_i_fu_112 <= ap_const_lv1_1;
            end if; 
        end if;
    end process;
    process (ap_clk)
    begin
        if (ap_clk'event and ap_clk = '1') then
            if (((ap_const_logic_1 = ap_CS_fsm_state1) and not(((ap_const_logic_0 = ap_start) or (ap_done_reg = ap_const_logic_1) or (ap_const_logic_0 = HwReg_height_cast8_l_2_empty_n) or (ap_const_logic_0 = HwReg_width_cast9_lo_1_empty_n) or (ap_const_logic_0 = HwReg_height_cast8_l_1_full_n) or (ap_const_logic_0 = HwReg_width_cast9_lo_full_n))))) then
                    Height_cast_i_i_i_reg_450(8 downto 0) <= Height_cast_i_i_i_fu_327_p1(8 downto 0);
                HwReg_width_cast9_lo_2_reg_445 <= HwReg_width_cast9_lo_1_dout;
            end if;
        end if;
    end process;
    process (ap_clk)
    begin
        if (ap_clk'event and ap_clk = '1') then
            if (((ap_const_logic_1 = ap_CS_fsm_pp1_stage0) and (ap_block_pp1_stage0_flag00011001 = ap_const_boolean_0) and (ap_const_lv1_0 = exitcond6_i_i_i_fu_372_p2))) then
                brmerge_i_i_i_reg_515 <= brmerge_i_i_i_fu_386_p2;
            end if;
        end if;
    end process;
    process (ap_clk)
    begin
        if (ap_clk'event and ap_clk = '1') then
            if (((ap_const_logic_1 = ap_CS_fsm_pp1_stage0) and (ap_block_pp1_stage0_flag00011001 = ap_const_boolean_0))) then
                exitcond6_i_i_i_reg_506 <= exitcond6_i_i_i_fu_372_p2;
            end if;
        end if;
    end process;
    process (ap_clk)
    begin
        if (ap_clk'event and ap_clk = '1') then
            if ((ap_const_logic_1 = ap_CS_fsm_state5)) then
                i_reg_501 <= i_fu_366_p2;
            end if;
        end if;
    end process;
    process (ap_clk)
    begin
        if (ap_clk'event and ap_clk = '1') then
            if ((ap_const_logic_1 = s_axis_video_V_data_V_0_load_A)) then
                s_axis_video_V_data_V_0_payload_A <= s_axis_video_TDATA;
            end if;
        end if;
    end process;
    process (ap_clk)
    begin
        if (ap_clk'event and ap_clk = '1') then
            if ((ap_const_logic_1 = s_axis_video_V_data_V_0_load_B)) then
                s_axis_video_V_data_V_0_payload_B <= s_axis_video_TDATA;
            end if;
        end if;
    end process;
    process (ap_clk)
    begin
        if (ap_clk'event and ap_clk = '1') then
            if ((ap_const_logic_1 = s_axis_video_V_last_V_0_load_A)) then
                s_axis_video_V_last_V_0_payload_A <= s_axis_video_TLAST;
            end if;
        end if;
    end process;
    process (ap_clk)
    begin
        if (ap_clk'event and ap_clk = '1') then
            if ((ap_const_logic_1 = s_axis_video_V_last_V_0_load_B)) then
                s_axis_video_V_last_V_0_payload_B <= s_axis_video_TLAST;
            end if;
        end if;
    end process;
    process (ap_clk)
    begin
        if (ap_clk'event and ap_clk = '1') then
            if ((ap_const_logic_1 = s_axis_video_V_user_V_0_load_A)) then
                s_axis_video_V_user_V_0_payload_A <= s_axis_video_TUSER;
            end if;
        end if;
    end process;
    process (ap_clk)
    begin
        if (ap_clk'event and ap_clk = '1') then
            if ((ap_const_logic_1 = s_axis_video_V_user_V_0_load_B)) then
                s_axis_video_V_user_V_0_payload_B <= s_axis_video_TUSER;
            end if;
        end if;
    end process;
    process (ap_clk)
    begin
        if (ap_clk'event and ap_clk = '1') then
            if ((ap_const_logic_1 = ap_CS_fsm_state4)) then
                sel_tmp2_i_reg_490 <= sel_tmp2_i_fu_347_p2;
            end if;
        end if;
    end process;
    process (ap_clk)
    begin
        if (ap_clk'event and ap_clk = '1') then
            if (((ap_const_logic_1 = ap_CS_fsm_state3) and (s_axis_video_V_data_V_0_vld_out = ap_const_logic_1))) then
                tmp_data_V_reg_470 <= s_axis_video_V_data_V_0_data_out;
                tmp_last_V_reg_478 <= s_axis_video_V_last_V_0_data_out;
            end if;
        end if;
    end process;
    process (ap_clk)
    begin
        if (ap_clk'event and ap_clk = '1') then
            if (((ap_const_logic_1 = ap_CS_fsm_state2) and (ap_block_state2_on_subcall_done = ap_const_boolean_0))) then
                tmp_i_i_i_235_reg_465 <= grp_reg_unsigned_short_s_fu_337_ap_return;
                tmp_i_i_i_reg_460 <= grp_reg_unsigned_short_s_fu_331_ap_return;
            end if;
        end if;
    end process;
    Height_cast_i_i_i_reg_450(9) <= '0';

    ap_NS_fsm_assign_proc : process (ap_start, ap_done_reg, ap_CS_fsm, ap_CS_fsm_state1, s_axis_video_V_data_V_0_vld_out, HwReg_height_cast8_l_2_empty_n, HwReg_width_cast9_lo_1_empty_n, HwReg_height_cast8_l_1_full_n, HwReg_width_cast9_lo_full_n, ap_CS_fsm_state3, ap_CS_fsm_pp1_stage0, ap_enable_reg_pp1_iter1, ap_CS_fsm_pp2_stage0, ap_enable_reg_pp2_iter1, ap_CS_fsm_state2, ap_block_state2_on_subcall_done, exitcond5_i_i_i_fu_361_p2, ap_CS_fsm_state5, ap_enable_reg_pp1_iter0, ap_block_pp1_stage0_flag00011011, ap_enable_reg_pp2_iter0, ap_block_pp2_stage0_flag00011011, tmp_user_V_fu_343_p1)
    begin
        case ap_CS_fsm is
            when ap_ST_fsm_state1 => 
                if (((ap_const_logic_1 = ap_CS_fsm_state1) and not(((ap_const_logic_0 = ap_start) or (ap_done_reg = ap_const_logic_1) or (ap_const_logic_0 = HwReg_height_cast8_l_2_empty_n) or (ap_const_logic_0 = HwReg_width_cast9_lo_1_empty_n) or (ap_const_logic_0 = HwReg_height_cast8_l_1_full_n) or (ap_const_logic_0 = HwReg_width_cast9_lo_full_n))))) then
                    ap_NS_fsm <= ap_ST_fsm_state2;
                else
                    ap_NS_fsm <= ap_ST_fsm_state1;
                end if;
            when ap_ST_fsm_state2 => 
                if (((ap_const_logic_1 = ap_CS_fsm_state2) and (ap_block_state2_on_subcall_done = ap_const_boolean_0))) then
                    ap_NS_fsm <= ap_ST_fsm_state3;
                else
                    ap_NS_fsm <= ap_ST_fsm_state2;
                end if;
            when ap_ST_fsm_state3 => 
                if (((ap_const_logic_1 = ap_CS_fsm_state3) and (s_axis_video_V_data_V_0_vld_out = ap_const_logic_1) and (ap_const_lv1_0 = tmp_user_V_fu_343_p1))) then
                    ap_NS_fsm <= ap_ST_fsm_state3;
                elsif (((ap_const_logic_1 = ap_CS_fsm_state3) and (s_axis_video_V_data_V_0_vld_out = ap_const_logic_1) and (ap_const_lv1_1 = tmp_user_V_fu_343_p1))) then
                    ap_NS_fsm <= ap_ST_fsm_state4;
                else
                    ap_NS_fsm <= ap_ST_fsm_state3;
                end if;
            when ap_ST_fsm_state4 => 
                ap_NS_fsm <= ap_ST_fsm_state5;
            when ap_ST_fsm_state5 => 
                if (((ap_const_logic_1 = ap_CS_fsm_state5) and (ap_const_lv1_1 = exitcond5_i_i_i_fu_361_p2))) then
                    ap_NS_fsm <= ap_ST_fsm_state1;
                else
                    ap_NS_fsm <= ap_ST_fsm_pp1_stage0;
                end if;
            when ap_ST_fsm_pp1_stage0 => 
                if (not(((ap_const_logic_1 = ap_CS_fsm_pp1_stage0) and (ap_const_logic_1 = ap_enable_reg_pp1_iter1) and (ap_block_pp1_stage0_flag00011011 = ap_const_boolean_0) and (ap_enable_reg_pp1_iter0 = ap_const_logic_0)))) then
                    ap_NS_fsm <= ap_ST_fsm_pp1_stage0;
                elsif (((ap_const_logic_1 = ap_CS_fsm_pp1_stage0) and (ap_const_logic_1 = ap_enable_reg_pp1_iter1) and (ap_block_pp1_stage0_flag00011011 = ap_const_boolean_0) and (ap_enable_reg_pp1_iter0 = ap_const_logic_0))) then
                    ap_NS_fsm <= ap_ST_fsm_state8;
                else
                    ap_NS_fsm <= ap_ST_fsm_pp1_stage0;
                end if;
            when ap_ST_fsm_state8 => 
                ap_NS_fsm <= ap_ST_fsm_pp2_stage0;
            when ap_ST_fsm_pp2_stage0 => 
                if (not(((ap_const_logic_1 = ap_CS_fsm_pp2_stage0) and (ap_const_logic_1 = ap_enable_reg_pp2_iter1) and (ap_block_pp2_stage0_flag00011011 = ap_const_boolean_0) and (ap_enable_reg_pp2_iter0 = ap_const_logic_0)))) then
                    ap_NS_fsm <= ap_ST_fsm_pp2_stage0;
                elsif (((ap_const_logic_1 = ap_CS_fsm_pp2_stage0) and (ap_const_logic_1 = ap_enable_reg_pp2_iter1) and (ap_block_pp2_stage0_flag00011011 = ap_const_boolean_0) and (ap_enable_reg_pp2_iter0 = ap_const_logic_0))) then
                    ap_NS_fsm <= ap_ST_fsm_state11;
                else
                    ap_NS_fsm <= ap_ST_fsm_pp2_stage0;
                end if;
            when ap_ST_fsm_state11 => 
                ap_NS_fsm <= ap_ST_fsm_state5;
            when others =>  
                ap_NS_fsm <= "XXXXXXXXX";
        end case;
    end process;
    Height_cast_i_i_i_fu_327_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(HwReg_height_cast8_l_2_dout),10));

    HwReg_height_cast8_l_1_blk_n_assign_proc : process(ap_start, ap_done_reg, ap_CS_fsm_state1, HwReg_height_cast8_l_1_full_n)
    begin
        if (((ap_const_logic_1 = ap_CS_fsm_state1) and not(((ap_const_logic_0 = ap_start) or (ap_done_reg = ap_const_logic_1))))) then 
            HwReg_height_cast8_l_1_blk_n <= HwReg_height_cast8_l_1_full_n;
        else 
            HwReg_height_cast8_l_1_blk_n <= ap_const_logic_1;
        end if; 
    end process;

    HwReg_height_cast8_l_1_din <= HwReg_height_cast8_l_2_dout;

    HwReg_height_cast8_l_1_write_assign_proc : process(ap_start, ap_done_reg, ap_CS_fsm_state1, HwReg_height_cast8_l_2_empty_n, HwReg_width_cast9_lo_1_empty_n, HwReg_height_cast8_l_1_full_n, HwReg_width_cast9_lo_full_n)
    begin
        if (((ap_const_logic_1 = ap_CS_fsm_state1) and not(((ap_const_logic_0 = ap_start) or (ap_done_reg = ap_const_logic_1) or (ap_const_logic_0 = HwReg_height_cast8_l_2_empty_n) or (ap_const_logic_0 = HwReg_width_cast9_lo_1_empty_n) or (ap_const_logic_0 = HwReg_height_cast8_l_1_full_n) or (ap_const_logic_0 = HwReg_width_cast9_lo_full_n))))) then 
            HwReg_height_cast8_l_1_write <= ap_const_logic_1;
        else 
            HwReg_height_cast8_l_1_write <= ap_const_logic_0;
        end if; 
    end process;


    HwReg_height_cast8_l_2_blk_n_assign_proc : process(ap_start, ap_done_reg, ap_CS_fsm_state1, HwReg_height_cast8_l_2_empty_n)
    begin
        if (((ap_const_logic_1 = ap_CS_fsm_state1) and not(((ap_const_logic_0 = ap_start) or (ap_done_reg = ap_const_logic_1))))) then 
            HwReg_height_cast8_l_2_blk_n <= HwReg_height_cast8_l_2_empty_n;
        else 
            HwReg_height_cast8_l_2_blk_n <= ap_const_logic_1;
        end if; 
    end process;


    HwReg_height_cast8_l_2_read_assign_proc : process(ap_start, ap_done_reg, ap_CS_fsm_state1, HwReg_height_cast8_l_2_empty_n, HwReg_width_cast9_lo_1_empty_n, HwReg_height_cast8_l_1_full_n, HwReg_width_cast9_lo_full_n)
    begin
        if (((ap_const_logic_1 = ap_CS_fsm_state1) and not(((ap_const_logic_0 = ap_start) or (ap_done_reg = ap_const_logic_1) or (ap_const_logic_0 = HwReg_height_cast8_l_2_empty_n) or (ap_const_logic_0 = HwReg_width_cast9_lo_1_empty_n) or (ap_const_logic_0 = HwReg_height_cast8_l_1_full_n) or (ap_const_logic_0 = HwReg_width_cast9_lo_full_n))))) then 
            HwReg_height_cast8_l_2_read <= ap_const_logic_1;
        else 
            HwReg_height_cast8_l_2_read <= ap_const_logic_0;
        end if; 
    end process;


    HwReg_width_cast9_lo_1_blk_n_assign_proc : process(ap_start, ap_done_reg, ap_CS_fsm_state1, HwReg_width_cast9_lo_1_empty_n)
    begin
        if (((ap_const_logic_1 = ap_CS_fsm_state1) and not(((ap_const_logic_0 = ap_start) or (ap_done_reg = ap_const_logic_1))))) then 
            HwReg_width_cast9_lo_1_blk_n <= HwReg_width_cast9_lo_1_empty_n;
        else 
            HwReg_width_cast9_lo_1_blk_n <= ap_const_logic_1;
        end if; 
    end process;


    HwReg_width_cast9_lo_1_read_assign_proc : process(ap_start, ap_done_reg, ap_CS_fsm_state1, HwReg_height_cast8_l_2_empty_n, HwReg_width_cast9_lo_1_empty_n, HwReg_height_cast8_l_1_full_n, HwReg_width_cast9_lo_full_n)
    begin
        if (((ap_const_logic_1 = ap_CS_fsm_state1) and not(((ap_const_logic_0 = ap_start) or (ap_done_reg = ap_const_logic_1) or (ap_const_logic_0 = HwReg_height_cast8_l_2_empty_n) or (ap_const_logic_0 = HwReg_width_cast9_lo_1_empty_n) or (ap_const_logic_0 = HwReg_height_cast8_l_1_full_n) or (ap_const_logic_0 = HwReg_width_cast9_lo_full_n))))) then 
            HwReg_width_cast9_lo_1_read <= ap_const_logic_1;
        else 
            HwReg_width_cast9_lo_1_read <= ap_const_logic_0;
        end if; 
    end process;


    HwReg_width_cast9_lo_blk_n_assign_proc : process(ap_start, ap_done_reg, ap_CS_fsm_state1, HwReg_width_cast9_lo_full_n)
    begin
        if (((ap_const_logic_1 = ap_CS_fsm_state1) and not(((ap_const_logic_0 = ap_start) or (ap_done_reg = ap_const_logic_1))))) then 
            HwReg_width_cast9_lo_blk_n <= HwReg_width_cast9_lo_full_n;
        else 
            HwReg_width_cast9_lo_blk_n <= ap_const_logic_1;
        end if; 
    end process;

    HwReg_width_cast9_lo_din <= HwReg_width_cast9_lo_1_dout;

    HwReg_width_cast9_lo_write_assign_proc : process(ap_start, ap_done_reg, ap_CS_fsm_state1, HwReg_height_cast8_l_2_empty_n, HwReg_width_cast9_lo_1_empty_n, HwReg_height_cast8_l_1_full_n, HwReg_width_cast9_lo_full_n)
    begin
        if (((ap_const_logic_1 = ap_CS_fsm_state1) and not(((ap_const_logic_0 = ap_start) or (ap_done_reg = ap_const_logic_1) or (ap_const_logic_0 = HwReg_height_cast8_l_2_empty_n) or (ap_const_logic_0 = HwReg_width_cast9_lo_1_empty_n) or (ap_const_logic_0 = HwReg_height_cast8_l_1_full_n) or (ap_const_logic_0 = HwReg_width_cast9_lo_full_n))))) then 
            HwReg_width_cast9_lo_write <= ap_const_logic_1;
        else 
            HwReg_width_cast9_lo_write <= ap_const_logic_0;
        end if; 
    end process;

    ap_CS_fsm_pp1_stage0 <= ap_CS_fsm(5);
    ap_CS_fsm_pp2_stage0 <= ap_CS_fsm(7);
    ap_CS_fsm_state1 <= ap_CS_fsm(0);
    ap_CS_fsm_state11 <= ap_CS_fsm(8);
    ap_CS_fsm_state2 <= ap_CS_fsm(1);
    ap_CS_fsm_state3 <= ap_CS_fsm(2);
    ap_CS_fsm_state4 <= ap_CS_fsm(3);
    ap_CS_fsm_state5 <= ap_CS_fsm(4);
    ap_CS_fsm_state8 <= ap_CS_fsm(6);
        ap_block_pp1_stage0_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1));

    ap_block_pp1_stage0_flag00001001_assign_proc : process(s_axis_video_V_data_V_0_vld_out, ap_enable_reg_pp1_iter1, exitcond6_i_i_i_reg_506, ap_predicate_op80_read_state7, img_V_val_0_V1_status)
    begin
                ap_block_pp1_stage0_flag00001001 <= ((ap_const_logic_1 = ap_enable_reg_pp1_iter1) and (((ap_const_logic_0 = s_axis_video_V_data_V_0_vld_out) and (ap_const_boolean_1 = ap_predicate_op80_read_state7)) or ((ap_const_lv1_0 = exitcond6_i_i_i_reg_506) and (ap_const_logic_0 = img_V_val_0_V1_status))));
    end process;


    ap_block_pp1_stage0_flag00011001_assign_proc : process(s_axis_video_V_data_V_0_vld_out, ap_enable_reg_pp1_iter1, exitcond6_i_i_i_reg_506, ap_predicate_op80_read_state7, img_V_val_0_V1_status)
    begin
                ap_block_pp1_stage0_flag00011001 <= ((ap_const_logic_1 = ap_enable_reg_pp1_iter1) and (((ap_const_logic_0 = s_axis_video_V_data_V_0_vld_out) and (ap_const_boolean_1 = ap_predicate_op80_read_state7)) or ((ap_const_lv1_0 = exitcond6_i_i_i_reg_506) and (ap_const_logic_0 = img_V_val_0_V1_status))));
    end process;


    ap_block_pp1_stage0_flag00011011_assign_proc : process(s_axis_video_V_data_V_0_vld_out, ap_enable_reg_pp1_iter1, exitcond6_i_i_i_reg_506, ap_predicate_op80_read_state7, img_V_val_0_V1_status)
    begin
                ap_block_pp1_stage0_flag00011011 <= ((ap_const_logic_1 = ap_enable_reg_pp1_iter1) and (((ap_const_logic_0 = s_axis_video_V_data_V_0_vld_out) and (ap_const_boolean_1 = ap_predicate_op80_read_state7)) or ((ap_const_lv1_0 = exitcond6_i_i_i_reg_506) and (ap_const_logic_0 = img_V_val_0_V1_status))));
    end process;

        ap_block_pp2_stage0_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1));

    ap_block_pp2_stage0_flag00011001_assign_proc : process(s_axis_video_V_data_V_0_vld_out, ap_enable_reg_pp2_iter1, eol_2_i_i_i_reg_282)
    begin
                ap_block_pp2_stage0_flag00011001 <= ((ap_const_logic_1 = ap_enable_reg_pp2_iter1) and (ap_const_lv1_0 = eol_2_i_i_i_reg_282) and (ap_const_logic_0 = s_axis_video_V_data_V_0_vld_out));
    end process;


    ap_block_pp2_stage0_flag00011011_assign_proc : process(s_axis_video_V_data_V_0_vld_out, ap_enable_reg_pp2_iter1, eol_2_i_i_i_reg_282)
    begin
                ap_block_pp2_stage0_flag00011011 <= ((ap_const_logic_1 = ap_enable_reg_pp2_iter1) and (ap_const_lv1_0 = eol_2_i_i_i_reg_282) and (ap_const_logic_0 = s_axis_video_V_data_V_0_vld_out));
    end process;


    ap_block_state1_assign_proc : process(ap_start, ap_done_reg, HwReg_height_cast8_l_2_empty_n, HwReg_width_cast9_lo_1_empty_n, HwReg_height_cast8_l_1_full_n, HwReg_width_cast9_lo_full_n)
    begin
                ap_block_state1 <= ((ap_const_logic_0 = ap_start) or (ap_done_reg = ap_const_logic_1) or (ap_const_logic_0 = HwReg_height_cast8_l_2_empty_n) or (ap_const_logic_0 = HwReg_width_cast9_lo_1_empty_n) or (ap_const_logic_0 = HwReg_height_cast8_l_1_full_n) or (ap_const_logic_0 = HwReg_width_cast9_lo_full_n));
    end process;


    ap_block_state10_pp2_stage0_iter1_assign_proc : process(s_axis_video_V_data_V_0_vld_out, eol_2_i_i_i_reg_282)
    begin
                ap_block_state10_pp2_stage0_iter1 <= ((ap_const_lv1_0 = eol_2_i_i_i_reg_282) and (ap_const_logic_0 = s_axis_video_V_data_V_0_vld_out));
    end process;


    ap_block_state1_ignore_call21_assign_proc : process(ap_start, ap_done_reg, HwReg_height_cast8_l_2_empty_n, HwReg_width_cast9_lo_1_empty_n, HwReg_height_cast8_l_1_full_n, HwReg_width_cast9_lo_full_n)
    begin
                ap_block_state1_ignore_call21 <= ((ap_const_logic_0 = ap_start) or (ap_done_reg = ap_const_logic_1) or (ap_const_logic_0 = HwReg_height_cast8_l_2_empty_n) or (ap_const_logic_0 = HwReg_width_cast9_lo_1_empty_n) or (ap_const_logic_0 = HwReg_height_cast8_l_1_full_n) or (ap_const_logic_0 = HwReg_width_cast9_lo_full_n));
    end process;


    ap_block_state1_ignore_call22_assign_proc : process(ap_start, ap_done_reg, HwReg_height_cast8_l_2_empty_n, HwReg_width_cast9_lo_1_empty_n, HwReg_height_cast8_l_1_full_n, HwReg_width_cast9_lo_full_n)
    begin
                ap_block_state1_ignore_call22 <= ((ap_const_logic_0 = ap_start) or (ap_done_reg = ap_const_logic_1) or (ap_const_logic_0 = HwReg_height_cast8_l_2_empty_n) or (ap_const_logic_0 = HwReg_width_cast9_lo_1_empty_n) or (ap_const_logic_0 = HwReg_height_cast8_l_1_full_n) or (ap_const_logic_0 = HwReg_width_cast9_lo_full_n));
    end process;


    ap_block_state2_on_subcall_done_assign_proc : process(grp_reg_unsigned_short_s_fu_331_ap_done, grp_reg_unsigned_short_s_fu_337_ap_done)
    begin
                ap_block_state2_on_subcall_done <= ((ap_const_logic_0 = grp_reg_unsigned_short_s_fu_331_ap_done) or (ap_const_logic_0 = grp_reg_unsigned_short_s_fu_337_ap_done));
    end process;

        ap_block_state6_pp1_stage0_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1));

    ap_block_state7_pp1_stage0_iter1_assign_proc : process(s_axis_video_V_data_V_0_vld_out, exitcond6_i_i_i_reg_506, ap_predicate_op80_read_state7, img_V_val_0_V1_status)
    begin
                ap_block_state7_pp1_stage0_iter1 <= (((ap_const_logic_0 = s_axis_video_V_data_V_0_vld_out) and (ap_const_boolean_1 = ap_predicate_op80_read_state7)) or ((ap_const_lv1_0 = exitcond6_i_i_i_reg_506) and (ap_const_logic_0 = img_V_val_0_V1_status)));
    end process;

        ap_block_state9_pp2_stage0_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1));

    ap_condition_511_assign_proc : process(ap_CS_fsm_pp1_stage0, ap_enable_reg_pp1_iter1, ap_block_pp1_stage0_flag00000000, exitcond6_i_i_i_reg_506)
    begin
                ap_condition_511 <= ((ap_const_logic_1 = ap_CS_fsm_pp1_stage0) and (ap_const_logic_1 = ap_enable_reg_pp1_iter1) and (ap_block_pp1_stage0_flag00000000 = ap_const_boolean_0) and (ap_const_lv1_0 = exitcond6_i_i_i_reg_506));
    end process;


    ap_done_assign_proc : process(ap_done_reg, exitcond5_i_i_i_fu_361_p2, ap_CS_fsm_state5)
    begin
        if (((ap_const_logic_1 = ap_CS_fsm_state5) and (ap_const_lv1_1 = exitcond5_i_i_i_fu_361_p2))) then 
            ap_done <= ap_const_logic_1;
        else 
            ap_done <= ap_done_reg;
        end if; 
    end process;

    ap_enable_pp1 <= (ap_idle_pp1 xor ap_const_logic_1);
    ap_enable_pp2 <= (ap_idle_pp2 xor ap_const_logic_1);

    ap_idle_assign_proc : process(ap_start, ap_CS_fsm_state1)
    begin
        if (((ap_const_logic_0 = ap_start) and (ap_const_logic_1 = ap_CS_fsm_state1))) then 
            ap_idle <= ap_const_logic_1;
        else 
            ap_idle <= ap_const_logic_0;
        end if; 
    end process;


    ap_idle_pp1_assign_proc : process(ap_enable_reg_pp1_iter1, ap_enable_reg_pp1_iter0)
    begin
        if (((ap_const_logic_0 = ap_enable_reg_pp1_iter0) and (ap_const_logic_0 = ap_enable_reg_pp1_iter1))) then 
            ap_idle_pp1 <= ap_const_logic_1;
        else 
            ap_idle_pp1 <= ap_const_logic_0;
        end if; 
    end process;


    ap_idle_pp2_assign_proc : process(ap_enable_reg_pp2_iter1, ap_enable_reg_pp2_iter0)
    begin
        if (((ap_const_logic_0 = ap_enable_reg_pp2_iter0) and (ap_const_logic_0 = ap_enable_reg_pp2_iter1))) then 
            ap_idle_pp2 <= ap_const_logic_1;
        else 
            ap_idle_pp2 <= ap_const_logic_0;
        end if; 
    end process;

    ap_phi_precharge_reg_pp1_iter1_axi_last_V_2_i_i_i_reg_257 <= "X";
    ap_phi_precharge_reg_pp1_iter1_p_Val2_s_reg_270 <= "XXXXXXXXXXXXXXXXXXXXXXXX";

    ap_predicate_op80_read_state7_assign_proc : process(exitcond6_i_i_i_reg_506, brmerge_i_i_i_reg_515)
    begin
                ap_predicate_op80_read_state7 <= ((ap_const_lv1_0 = exitcond6_i_i_i_reg_506) and (ap_const_lv1_0 = brmerge_i_i_i_reg_515));
    end process;


    ap_ready_assign_proc : process(exitcond5_i_i_i_fu_361_p2, ap_CS_fsm_state5)
    begin
        if (((ap_const_logic_1 = ap_CS_fsm_state5) and (ap_const_lv1_1 = exitcond5_i_i_i_fu_361_p2))) then 
            ap_ready <= ap_const_logic_1;
        else 
            ap_ready <= ap_const_logic_0;
        end if; 
    end process;


    axi_last_V_2_i_i_i_phi_fu_262_p4_assign_proc : process(s_axis_video_V_last_V_0_data_out, brmerge_i_i_i_reg_515, eol_reg_235, ap_phi_precharge_reg_pp1_iter1_axi_last_V_2_i_i_i_reg_257, ap_condition_511)
    begin
        if ((ap_condition_511 = ap_const_boolean_1)) then
            if ((ap_const_lv1_1 = brmerge_i_i_i_reg_515)) then 
                axi_last_V_2_i_i_i_phi_fu_262_p4 <= eol_reg_235;
            elsif ((ap_const_lv1_0 = brmerge_i_i_i_reg_515)) then 
                axi_last_V_2_i_i_i_phi_fu_262_p4 <= s_axis_video_V_last_V_0_data_out;
            else 
                axi_last_V_2_i_i_i_phi_fu_262_p4 <= ap_phi_precharge_reg_pp1_iter1_axi_last_V_2_i_i_i_reg_257;
            end if;
        else 
            axi_last_V_2_i_i_i_phi_fu_262_p4 <= ap_phi_precharge_reg_pp1_iter1_axi_last_V_2_i_i_i_reg_257;
        end if; 
    end process;

    brmerge_i_i_i_fu_386_p2 <= (sof_1_i_i_i_fu_112 or eol_i_i_i_phi_fu_216_p4);

    eol_2_i_i_i_phi_fu_285_p4_assign_proc : process(s_axis_video_V_last_V_0_data_out, ap_CS_fsm_pp2_stage0, ap_enable_reg_pp2_iter1, ap_block_pp2_stage0_flag00000000, eol_2_i_i_i_reg_282)
    begin
        if (((ap_const_logic_1 = ap_CS_fsm_pp2_stage0) and (ap_const_logic_1 = ap_enable_reg_pp2_iter1) and (ap_block_pp2_stage0_flag00000000 = ap_const_boolean_0) and (ap_const_lv1_0 = eol_2_i_i_i_reg_282))) then 
            eol_2_i_i_i_phi_fu_285_p4 <= s_axis_video_V_last_V_0_data_out;
        else 
            eol_2_i_i_i_phi_fu_285_p4 <= eol_2_i_i_i_reg_282;
        end if; 
    end process;


    eol_i_i_i_phi_fu_216_p4_assign_proc : process(ap_CS_fsm_pp1_stage0, ap_enable_reg_pp1_iter1, ap_block_pp1_stage0_flag00000000, exitcond6_i_i_i_reg_506, eol_i_i_i_reg_212, axi_last_V_2_i_i_i_phi_fu_262_p4)
    begin
        if (((ap_const_logic_1 = ap_CS_fsm_pp1_stage0) and (ap_const_logic_1 = ap_enable_reg_pp1_iter1) and (ap_block_pp1_stage0_flag00000000 = ap_const_boolean_0) and (ap_const_lv1_0 = exitcond6_i_i_i_reg_506))) then 
            eol_i_i_i_phi_fu_216_p4 <= axi_last_V_2_i_i_i_phi_fu_262_p4;
        else 
            eol_i_i_i_phi_fu_216_p4 <= eol_i_i_i_reg_212;
        end if; 
    end process;

    exitcond5_i_i_i_fu_361_p2 <= "1" when (i_cast_i_i_i_fu_357_p1 = tmp_i_i_i_reg_460) else "0";
    exitcond6_i_i_i_fu_372_p2 <= "1" when (j_i_i_i_reg_224 = tmp_i_i_i_235_reg_465) else "0";
    grp_reg_unsigned_short_s_fu_331_ap_start <= ap_reg_grp_reg_unsigned_short_s_fu_331_ap_start;
    grp_reg_unsigned_short_s_fu_337_ap_start <= ap_reg_grp_reg_unsigned_short_s_fu_337_ap_start;
    i_cast_i_i_i_fu_357_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(i_i_i_i_reg_201),10));
    i_fu_366_p2 <= std_logic_vector(unsigned(i_i_i_i_reg_201) + unsigned(ap_const_lv9_1));
    img_V_val_0_V1_status <= (img_V_val_0_V_full_n and img_V_val_1_V_full_n and img_V_val_2_V_full_n);

    img_V_val_0_V1_update_assign_proc : process(ap_CS_fsm_pp1_stage0, ap_enable_reg_pp1_iter1, exitcond6_i_i_i_reg_506, ap_block_pp1_stage0_flag00011001)
    begin
        if (((ap_const_logic_1 = ap_CS_fsm_pp1_stage0) and (ap_const_logic_1 = ap_enable_reg_pp1_iter1) and (ap_const_lv1_0 = exitcond6_i_i_i_reg_506) and (ap_block_pp1_stage0_flag00011001 = ap_const_boolean_0))) then 
            img_V_val_0_V1_update <= ap_const_logic_1;
        else 
            img_V_val_0_V1_update <= ap_const_logic_0;
        end if; 
    end process;


    img_V_val_0_V_blk_n_assign_proc : process(img_V_val_0_V_full_n, ap_CS_fsm_pp1_stage0, ap_enable_reg_pp1_iter1, ap_block_pp1_stage0_flag00000000, exitcond6_i_i_i_reg_506)
    begin
        if (((ap_const_logic_1 = ap_CS_fsm_pp1_stage0) and (ap_const_logic_1 = ap_enable_reg_pp1_iter1) and (ap_block_pp1_stage0_flag00000000 = ap_const_boolean_0) and (ap_const_lv1_0 = exitcond6_i_i_i_reg_506))) then 
            img_V_val_0_V_blk_n <= img_V_val_0_V_full_n;
        else 
            img_V_val_0_V_blk_n <= ap_const_logic_1;
        end if; 
    end process;

    img_V_val_0_V_din <= 
        pix_val_0_V_fu_397_p4 when (sel_tmp2_i_reg_490(0) = '1') else 
        pix_val_1_V_8_fu_407_p1;
    img_V_val_0_V_write <= img_V_val_0_V1_update;

    img_V_val_1_V_blk_n_assign_proc : process(img_V_val_1_V_full_n, ap_CS_fsm_pp1_stage0, ap_enable_reg_pp1_iter1, ap_block_pp1_stage0_flag00000000, exitcond6_i_i_i_reg_506)
    begin
        if (((ap_const_logic_1 = ap_CS_fsm_pp1_stage0) and (ap_const_logic_1 = ap_enable_reg_pp1_iter1) and (ap_block_pp1_stage0_flag00000000 = ap_const_boolean_0) and (ap_const_lv1_0 = exitcond6_i_i_i_reg_506))) then 
            img_V_val_1_V_blk_n <= img_V_val_1_V_full_n;
        else 
            img_V_val_1_V_blk_n <= ap_const_logic_1;
        end if; 
    end process;

    img_V_val_1_V_din <= 
        pix_val_1_V_8_fu_407_p1 when (sel_tmp2_i_reg_490(0) = '1') else 
        pix_val_2_V_fu_411_p4;
    img_V_val_1_V_write <= img_V_val_0_V1_update;

    img_V_val_2_V_blk_n_assign_proc : process(img_V_val_2_V_full_n, ap_CS_fsm_pp1_stage0, ap_enable_reg_pp1_iter1, ap_block_pp1_stage0_flag00000000, exitcond6_i_i_i_reg_506)
    begin
        if (((ap_const_logic_1 = ap_CS_fsm_pp1_stage0) and (ap_const_logic_1 = ap_enable_reg_pp1_iter1) and (ap_block_pp1_stage0_flag00000000 = ap_const_boolean_0) and (ap_const_lv1_0 = exitcond6_i_i_i_reg_506))) then 
            img_V_val_2_V_blk_n <= img_V_val_2_V_full_n;
        else 
            img_V_val_2_V_blk_n <= ap_const_logic_1;
        end if; 
    end process;

    img_V_val_2_V_din <= 
        pix_val_2_V_fu_411_p4 when (sel_tmp2_i_reg_490(0) = '1') else 
        pix_val_0_V_fu_397_p4;
    img_V_val_2_V_write <= img_V_val_0_V1_update;
    j_fu_377_p2 <= std_logic_vector(unsigned(j_i_i_i_reg_224) + unsigned(ap_const_lv10_1));

    p_Val2_s_phi_fu_274_p4_assign_proc : process(s_axis_video_V_data_V_0_data_out, brmerge_i_i_i_reg_515, axi_data_V_1_i_i_i_reg_246, ap_phi_precharge_reg_pp1_iter1_p_Val2_s_reg_270, ap_condition_511)
    begin
        if ((ap_condition_511 = ap_const_boolean_1)) then
            if ((ap_const_lv1_1 = brmerge_i_i_i_reg_515)) then 
                p_Val2_s_phi_fu_274_p4 <= axi_data_V_1_i_i_i_reg_246;
            elsif ((ap_const_lv1_0 = brmerge_i_i_i_reg_515)) then 
                p_Val2_s_phi_fu_274_p4 <= s_axis_video_V_data_V_0_data_out;
            else 
                p_Val2_s_phi_fu_274_p4 <= ap_phi_precharge_reg_pp1_iter1_p_Val2_s_reg_270;
            end if;
        else 
            p_Val2_s_phi_fu_274_p4 <= ap_phi_precharge_reg_pp1_iter1_p_Val2_s_reg_270;
        end if; 
    end process;

    pix_val_0_V_fu_397_p4 <= p_Val2_s_phi_fu_274_p4(23 downto 16);
    pix_val_1_V_8_fu_407_p1 <= p_Val2_s_phi_fu_274_p4(8 - 1 downto 0);
    pix_val_2_V_fu_411_p4 <= p_Val2_s_phi_fu_274_p4(15 downto 8);

    s_axis_video_TDATA_blk_n_assign_proc : process(s_axis_video_V_data_V_0_state, ap_CS_fsm_state3, ap_CS_fsm_pp1_stage0, ap_enable_reg_pp1_iter1, ap_block_pp1_stage0_flag00000000, exitcond6_i_i_i_reg_506, brmerge_i_i_i_reg_515, ap_CS_fsm_pp2_stage0, ap_enable_reg_pp2_iter1, ap_block_pp2_stage0_flag00000000, eol_2_i_i_i_reg_282)
    begin
        if (((ap_const_logic_1 = ap_CS_fsm_state3) or ((ap_const_logic_1 = ap_CS_fsm_pp1_stage0) and (ap_const_logic_1 = ap_enable_reg_pp1_iter1) and (ap_block_pp1_stage0_flag00000000 = ap_const_boolean_0) and (ap_const_lv1_0 = exitcond6_i_i_i_reg_506) and (ap_const_lv1_0 = brmerge_i_i_i_reg_515)) or ((ap_const_logic_1 = ap_CS_fsm_pp2_stage0) and (ap_const_logic_1 = ap_enable_reg_pp2_iter1) and (ap_block_pp2_stage0_flag00000000 = ap_const_boolean_0) and (ap_const_lv1_0 = eol_2_i_i_i_reg_282)))) then 
            s_axis_video_TDATA_blk_n <= s_axis_video_V_data_V_0_state(0);
        else 
            s_axis_video_TDATA_blk_n <= ap_const_logic_1;
        end if; 
    end process;

    s_axis_video_TREADY <= s_axis_video_V_dest_V_0_state(1);
    s_axis_video_V_data_V_0_ack_in <= s_axis_video_V_data_V_0_state(1);

    s_axis_video_V_data_V_0_ack_out_assign_proc : process(s_axis_video_V_data_V_0_vld_out, ap_CS_fsm_state3, ap_CS_fsm_pp1_stage0, ap_enable_reg_pp1_iter1, ap_CS_fsm_pp2_stage0, ap_enable_reg_pp2_iter1, eol_2_i_i_i_reg_282, ap_predicate_op80_read_state7, ap_block_pp1_stage0_flag00011001, ap_block_pp2_stage0_flag00011001)
    begin
        if ((((ap_const_logic_1 = ap_CS_fsm_state3) and (s_axis_video_V_data_V_0_vld_out = ap_const_logic_1)) or ((ap_const_logic_1 = ap_CS_fsm_pp2_stage0) and (ap_const_logic_1 = ap_enable_reg_pp2_iter1) and (ap_const_lv1_0 = eol_2_i_i_i_reg_282) and (ap_block_pp2_stage0_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_CS_fsm_pp1_stage0) and (ap_const_logic_1 = ap_enable_reg_pp1_iter1) and (ap_const_boolean_1 = ap_predicate_op80_read_state7) and (ap_block_pp1_stage0_flag00011001 = ap_const_boolean_0)))) then 
            s_axis_video_V_data_V_0_ack_out <= ap_const_logic_1;
        else 
            s_axis_video_V_data_V_0_ack_out <= ap_const_logic_0;
        end if; 
    end process;


    s_axis_video_V_data_V_0_data_out_assign_proc : process(s_axis_video_V_data_V_0_payload_A, s_axis_video_V_data_V_0_payload_B, s_axis_video_V_data_V_0_sel)
    begin
        if ((ap_const_logic_1 = s_axis_video_V_data_V_0_sel)) then 
            s_axis_video_V_data_V_0_data_out <= s_axis_video_V_data_V_0_payload_B;
        else 
            s_axis_video_V_data_V_0_data_out <= s_axis_video_V_data_V_0_payload_A;
        end if; 
    end process;

    s_axis_video_V_data_V_0_load_A <= (s_axis_video_V_data_V_0_state_cmp_full and not(s_axis_video_V_data_V_0_sel_wr));
    s_axis_video_V_data_V_0_load_B <= (s_axis_video_V_data_V_0_sel_wr and s_axis_video_V_data_V_0_state_cmp_full);
    s_axis_video_V_data_V_0_sel <= s_axis_video_V_data_V_0_sel_rd;
    s_axis_video_V_data_V_0_state_cmp_full <= '0' when (s_axis_video_V_data_V_0_state = ap_const_lv2_1) else '1';
    s_axis_video_V_data_V_0_vld_in <= s_axis_video_TVALID;
    s_axis_video_V_data_V_0_vld_out <= s_axis_video_V_data_V_0_state(0);

    s_axis_video_V_dest_V_0_ack_out_assign_proc : process(s_axis_video_V_data_V_0_vld_out, ap_CS_fsm_state3, ap_CS_fsm_pp1_stage0, ap_enable_reg_pp1_iter1, ap_CS_fsm_pp2_stage0, ap_enable_reg_pp2_iter1, eol_2_i_i_i_reg_282, ap_predicate_op80_read_state7, ap_block_pp1_stage0_flag00011001, ap_block_pp2_stage0_flag00011001)
    begin
        if ((((ap_const_logic_1 = ap_CS_fsm_state3) and (s_axis_video_V_data_V_0_vld_out = ap_const_logic_1)) or ((ap_const_logic_1 = ap_CS_fsm_pp2_stage0) and (ap_const_logic_1 = ap_enable_reg_pp2_iter1) and (ap_const_lv1_0 = eol_2_i_i_i_reg_282) and (ap_block_pp2_stage0_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_CS_fsm_pp1_stage0) and (ap_const_logic_1 = ap_enable_reg_pp1_iter1) and (ap_const_boolean_1 = ap_predicate_op80_read_state7) and (ap_block_pp1_stage0_flag00011001 = ap_const_boolean_0)))) then 
            s_axis_video_V_dest_V_0_ack_out <= ap_const_logic_1;
        else 
            s_axis_video_V_dest_V_0_ack_out <= ap_const_logic_0;
        end if; 
    end process;

    s_axis_video_V_dest_V_0_vld_in <= s_axis_video_TVALID;
    s_axis_video_V_last_V_0_ack_in <= s_axis_video_V_last_V_0_state(1);

    s_axis_video_V_last_V_0_ack_out_assign_proc : process(s_axis_video_V_data_V_0_vld_out, ap_CS_fsm_state3, ap_CS_fsm_pp1_stage0, ap_enable_reg_pp1_iter1, ap_CS_fsm_pp2_stage0, ap_enable_reg_pp2_iter1, eol_2_i_i_i_reg_282, ap_predicate_op80_read_state7, ap_block_pp1_stage0_flag00011001, ap_block_pp2_stage0_flag00011001)
    begin
        if ((((ap_const_logic_1 = ap_CS_fsm_state3) and (s_axis_video_V_data_V_0_vld_out = ap_const_logic_1)) or ((ap_const_logic_1 = ap_CS_fsm_pp2_stage0) and (ap_const_logic_1 = ap_enable_reg_pp2_iter1) and (ap_const_lv1_0 = eol_2_i_i_i_reg_282) and (ap_block_pp2_stage0_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_CS_fsm_pp1_stage0) and (ap_const_logic_1 = ap_enable_reg_pp1_iter1) and (ap_const_boolean_1 = ap_predicate_op80_read_state7) and (ap_block_pp1_stage0_flag00011001 = ap_const_boolean_0)))) then 
            s_axis_video_V_last_V_0_ack_out <= ap_const_logic_1;
        else 
            s_axis_video_V_last_V_0_ack_out <= ap_const_logic_0;
        end if; 
    end process;


    s_axis_video_V_last_V_0_data_out_assign_proc : process(s_axis_video_V_last_V_0_payload_A, s_axis_video_V_last_V_0_payload_B, s_axis_video_V_last_V_0_sel)
    begin
        if ((ap_const_logic_1 = s_axis_video_V_last_V_0_sel)) then 
            s_axis_video_V_last_V_0_data_out <= s_axis_video_V_last_V_0_payload_B;
        else 
            s_axis_video_V_last_V_0_data_out <= s_axis_video_V_last_V_0_payload_A;
        end if; 
    end process;

    s_axis_video_V_last_V_0_load_A <= (s_axis_video_V_last_V_0_state_cmp_full and not(s_axis_video_V_last_V_0_sel_wr));
    s_axis_video_V_last_V_0_load_B <= (s_axis_video_V_last_V_0_sel_wr and s_axis_video_V_last_V_0_state_cmp_full);
    s_axis_video_V_last_V_0_sel <= s_axis_video_V_last_V_0_sel_rd;
    s_axis_video_V_last_V_0_state_cmp_full <= '0' when (s_axis_video_V_last_V_0_state = ap_const_lv2_1) else '1';
    s_axis_video_V_last_V_0_vld_in <= s_axis_video_TVALID;
    s_axis_video_V_last_V_0_vld_out <= s_axis_video_V_last_V_0_state(0);
    s_axis_video_V_user_V_0_ack_in <= s_axis_video_V_user_V_0_state(1);

    s_axis_video_V_user_V_0_ack_out_assign_proc : process(s_axis_video_V_data_V_0_vld_out, ap_CS_fsm_state3, ap_CS_fsm_pp1_stage0, ap_enable_reg_pp1_iter1, ap_CS_fsm_pp2_stage0, ap_enable_reg_pp2_iter1, eol_2_i_i_i_reg_282, ap_predicate_op80_read_state7, ap_block_pp1_stage0_flag00011001, ap_block_pp2_stage0_flag00011001)
    begin
        if ((((ap_const_logic_1 = ap_CS_fsm_state3) and (s_axis_video_V_data_V_0_vld_out = ap_const_logic_1)) or ((ap_const_logic_1 = ap_CS_fsm_pp2_stage0) and (ap_const_logic_1 = ap_enable_reg_pp2_iter1) and (ap_const_lv1_0 = eol_2_i_i_i_reg_282) and (ap_block_pp2_stage0_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_CS_fsm_pp1_stage0) and (ap_const_logic_1 = ap_enable_reg_pp1_iter1) and (ap_const_boolean_1 = ap_predicate_op80_read_state7) and (ap_block_pp1_stage0_flag00011001 = ap_const_boolean_0)))) then 
            s_axis_video_V_user_V_0_ack_out <= ap_const_logic_1;
        else 
            s_axis_video_V_user_V_0_ack_out <= ap_const_logic_0;
        end if; 
    end process;


    s_axis_video_V_user_V_0_data_out_assign_proc : process(s_axis_video_V_user_V_0_payload_A, s_axis_video_V_user_V_0_payload_B, s_axis_video_V_user_V_0_sel)
    begin
        if ((ap_const_logic_1 = s_axis_video_V_user_V_0_sel)) then 
            s_axis_video_V_user_V_0_data_out <= s_axis_video_V_user_V_0_payload_B;
        else 
            s_axis_video_V_user_V_0_data_out <= s_axis_video_V_user_V_0_payload_A;
        end if; 
    end process;

    s_axis_video_V_user_V_0_load_A <= (s_axis_video_V_user_V_0_state_cmp_full and not(s_axis_video_V_user_V_0_sel_wr));
    s_axis_video_V_user_V_0_load_B <= (s_axis_video_V_user_V_0_sel_wr and s_axis_video_V_user_V_0_state_cmp_full);
    s_axis_video_V_user_V_0_sel <= s_axis_video_V_user_V_0_sel_rd;
    s_axis_video_V_user_V_0_state_cmp_full <= '0' when (s_axis_video_V_user_V_0_state = ap_const_lv2_1) else '1';
    s_axis_video_V_user_V_0_vld_in <= s_axis_video_TVALID;
    s_axis_video_V_user_V_0_vld_out <= s_axis_video_V_user_V_0_state(0);
    sel_tmp2_i_fu_347_p2 <= "1" when (tmp_2_loc_channel = ap_const_lv2_0) else "0";
    tmp_user_V_fu_343_p1 <= s_axis_video_V_user_V_0_data_out;
end behav;
