// ==============================================================
// RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2017.2
// Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved.
// 
// ===========================================================

`timescale 1 ns / 1 ps 

module design_1_v_frmbuf_wr_0_0_AXIvideo2MultiPixStr (
        ap_clk,
        ap_rst,
        ap_start,
        ap_done,
        ap_continue,
        ap_idle,
        ap_ready,
        s_axis_video_TDATA,
        s_axis_video_TVALID,
        s_axis_video_TREADY,
        s_axis_video_TKEEP,
        s_axis_video_TSTRB,
        s_axis_video_TUSER,
        s_axis_video_TLAST,
        s_axis_video_TID,
        s_axis_video_TDEST,
        img_V_val_0_V_din,
        img_V_val_0_V_full_n,
        img_V_val_0_V_write,
        img_V_val_1_V_din,
        img_V_val_1_V_full_n,
        img_V_val_1_V_write,
        img_V_val_2_V_din,
        img_V_val_2_V_full_n,
        img_V_val_2_V_write,
        HwReg_height_cast8_l_2_dout,
        HwReg_height_cast8_l_2_empty_n,
        HwReg_height_cast8_l_2_read,
        HwReg_width_cast9_lo_1_dout,
        HwReg_width_cast9_lo_1_empty_n,
        HwReg_width_cast9_lo_1_read,
        tmp_2_loc_channel,
        HwReg_height_cast8_l_1_din,
        HwReg_height_cast8_l_1_full_n,
        HwReg_height_cast8_l_1_write,
        HwReg_width_cast9_lo_din,
        HwReg_width_cast9_lo_full_n,
        HwReg_width_cast9_lo_write
);

parameter    ap_ST_fsm_state1 = 9'd1;
parameter    ap_ST_fsm_state2 = 9'd2;
parameter    ap_ST_fsm_state3 = 9'd4;
parameter    ap_ST_fsm_state4 = 9'd8;
parameter    ap_ST_fsm_state5 = 9'd16;
parameter    ap_ST_fsm_pp1_stage0 = 9'd32;
parameter    ap_ST_fsm_state8 = 9'd64;
parameter    ap_ST_fsm_pp2_stage0 = 9'd128;
parameter    ap_ST_fsm_state11 = 9'd256;

input   ap_clk;
input   ap_rst;
input   ap_start;
output   ap_done;
input   ap_continue;
output   ap_idle;
output   ap_ready;
input  [23:0] s_axis_video_TDATA;
input   s_axis_video_TVALID;
output   s_axis_video_TREADY;
input  [2:0] s_axis_video_TKEEP;
input  [2:0] s_axis_video_TSTRB;
input  [0:0] s_axis_video_TUSER;
input  [0:0] s_axis_video_TLAST;
input  [0:0] s_axis_video_TID;
input  [0:0] s_axis_video_TDEST;
output  [7:0] img_V_val_0_V_din;
input   img_V_val_0_V_full_n;
output   img_V_val_0_V_write;
output  [7:0] img_V_val_1_V_din;
input   img_V_val_1_V_full_n;
output   img_V_val_1_V_write;
output  [7:0] img_V_val_2_V_din;
input   img_V_val_2_V_full_n;
output   img_V_val_2_V_write;
input  [8:0] HwReg_height_cast8_l_2_dout;
input   HwReg_height_cast8_l_2_empty_n;
output   HwReg_height_cast8_l_2_read;
input  [9:0] HwReg_width_cast9_lo_1_dout;
input   HwReg_width_cast9_lo_1_empty_n;
output   HwReg_width_cast9_lo_1_read;
input  [1:0] tmp_2_loc_channel;
output  [8:0] HwReg_height_cast8_l_1_din;
input   HwReg_height_cast8_l_1_full_n;
output   HwReg_height_cast8_l_1_write;
output  [9:0] HwReg_width_cast9_lo_din;
input   HwReg_width_cast9_lo_full_n;
output   HwReg_width_cast9_lo_write;

reg ap_done;
reg ap_idle;
reg ap_ready;
reg HwReg_height_cast8_l_2_read;
reg HwReg_width_cast9_lo_1_read;
reg HwReg_height_cast8_l_1_write;
reg HwReg_width_cast9_lo_write;

reg    ap_done_reg;
(* fsm_encoding = "none" *) reg   [8:0] ap_CS_fsm;
wire    ap_CS_fsm_state1;
reg   [23:0] s_axis_video_V_data_V_0_data_out;
wire    s_axis_video_V_data_V_0_vld_in;
wire    s_axis_video_V_data_V_0_vld_out;
wire    s_axis_video_V_data_V_0_ack_in;
reg    s_axis_video_V_data_V_0_ack_out;
reg   [23:0] s_axis_video_V_data_V_0_payload_A;
reg   [23:0] s_axis_video_V_data_V_0_payload_B;
reg    s_axis_video_V_data_V_0_sel_rd;
reg    s_axis_video_V_data_V_0_sel_wr;
wire    s_axis_video_V_data_V_0_sel;
wire    s_axis_video_V_data_V_0_load_A;
wire    s_axis_video_V_data_V_0_load_B;
reg   [1:0] s_axis_video_V_data_V_0_state;
wire    s_axis_video_V_data_V_0_state_cmp_full;
reg   [0:0] s_axis_video_V_user_V_0_data_out;
wire    s_axis_video_V_user_V_0_vld_in;
wire    s_axis_video_V_user_V_0_vld_out;
wire    s_axis_video_V_user_V_0_ack_in;
reg    s_axis_video_V_user_V_0_ack_out;
reg   [0:0] s_axis_video_V_user_V_0_payload_A;
reg   [0:0] s_axis_video_V_user_V_0_payload_B;
reg    s_axis_video_V_user_V_0_sel_rd;
reg    s_axis_video_V_user_V_0_sel_wr;
wire    s_axis_video_V_user_V_0_sel;
wire    s_axis_video_V_user_V_0_load_A;
wire    s_axis_video_V_user_V_0_load_B;
reg   [1:0] s_axis_video_V_user_V_0_state;
wire    s_axis_video_V_user_V_0_state_cmp_full;
reg   [0:0] s_axis_video_V_last_V_0_data_out;
wire    s_axis_video_V_last_V_0_vld_in;
wire    s_axis_video_V_last_V_0_vld_out;
wire    s_axis_video_V_last_V_0_ack_in;
reg    s_axis_video_V_last_V_0_ack_out;
reg   [0:0] s_axis_video_V_last_V_0_payload_A;
reg   [0:0] s_axis_video_V_last_V_0_payload_B;
reg    s_axis_video_V_last_V_0_sel_rd;
reg    s_axis_video_V_last_V_0_sel_wr;
wire    s_axis_video_V_last_V_0_sel;
wire    s_axis_video_V_last_V_0_load_A;
wire    s_axis_video_V_last_V_0_load_B;
reg   [1:0] s_axis_video_V_last_V_0_state;
wire    s_axis_video_V_last_V_0_state_cmp_full;
wire    s_axis_video_V_dest_V_0_vld_in;
reg    s_axis_video_V_dest_V_0_ack_out;
reg   [1:0] s_axis_video_V_dest_V_0_state;
reg    s_axis_video_TDATA_blk_n;
wire    ap_CS_fsm_state3;
wire    ap_CS_fsm_pp1_stage0;
reg    ap_enable_reg_pp1_iter1;
wire    ap_block_pp1_stage0_flag00000000;
reg   [0:0] exitcond6_i_i_i_reg_506;
reg   [0:0] brmerge_i_i_i_reg_515;
wire    ap_CS_fsm_pp2_stage0;
reg    ap_enable_reg_pp2_iter1;
wire    ap_block_pp2_stage0_flag00000000;
reg   [0:0] eol_2_i_i_i_reg_282;
reg    img_V_val_0_V_blk_n;
reg    img_V_val_1_V_blk_n;
reg    img_V_val_2_V_blk_n;
reg    HwReg_height_cast8_l_2_blk_n;
reg    HwReg_width_cast9_lo_1_blk_n;
reg    HwReg_height_cast8_l_1_blk_n;
reg    HwReg_width_cast9_lo_blk_n;
reg   [0:0] eol_i_i_i_reg_212;
reg   [9:0] j_i_i_i_reg_224;
reg   [0:0] eol_reg_235;
reg   [23:0] axi_data_V_1_i_i_i_reg_246;
reg   [0:0] axi_last_V_3_i_i_i_reg_293;
reg   [23:0] axi_data_V_3_i_i_i_reg_305;
reg   [9:0] HwReg_width_cast9_lo_2_reg_445;
reg    ap_block_state1;
wire   [9:0] Height_cast_i_i_i_fu_327_p1;
reg   [9:0] Height_cast_i_i_i_reg_450;
wire    ap_CS_fsm_state2;
wire    grp_reg_unsigned_short_s_fu_331_ap_done;
wire    grp_reg_unsigned_short_s_fu_337_ap_done;
reg    ap_block_state2_on_subcall_done;
wire   [9:0] grp_reg_unsigned_short_s_fu_331_ap_return;
reg   [9:0] tmp_i_i_i_reg_460;
wire   [9:0] grp_reg_unsigned_short_s_fu_337_ap_return;
reg   [9:0] tmp_i_i_i_235_reg_465;
reg   [23:0] tmp_data_V_reg_470;
reg   [0:0] tmp_last_V_reg_478;
wire   [0:0] sel_tmp2_i_fu_347_p2;
reg   [0:0] sel_tmp2_i_reg_490;
wire    ap_CS_fsm_state4;
wire   [0:0] exitcond5_i_i_i_fu_361_p2;
wire    ap_CS_fsm_state5;
wire   [8:0] i_fu_366_p2;
reg   [8:0] i_reg_501;
wire   [0:0] exitcond6_i_i_i_fu_372_p2;
wire    ap_block_state6_pp1_stage0_iter0;
reg    ap_predicate_op80_read_state7;
wire    img_V_val_0_V1_status;
reg    ap_block_state7_pp1_stage0_iter1;
reg    ap_block_pp1_stage0_flag00011001;
wire   [9:0] j_fu_377_p2;
reg    ap_enable_reg_pp1_iter0;
wire   [0:0] brmerge_i_i_i_fu_386_p2;
wire    ap_block_state9_pp2_stage0_iter0;
reg    ap_block_state10_pp2_stage0_iter1;
reg    ap_block_pp2_stage0_flag00011001;
reg    ap_block_pp1_stage0_flag00011011;
reg    ap_enable_reg_pp2_iter0;
wire    ap_CS_fsm_state8;
reg    ap_block_pp2_stage0_flag00011011;
reg   [0:0] eol_2_i_i_i_phi_fu_285_p4;
wire    grp_reg_unsigned_short_s_fu_331_ap_start;
wire    grp_reg_unsigned_short_s_fu_331_ap_idle;
wire    grp_reg_unsigned_short_s_fu_331_ap_ready;
wire    grp_reg_unsigned_short_s_fu_337_ap_start;
wire    grp_reg_unsigned_short_s_fu_337_ap_idle;
wire    grp_reg_unsigned_short_s_fu_337_ap_ready;
reg   [0:0] axi_last_V1_i_i_i_reg_181;
wire    ap_CS_fsm_state11;
reg   [23:0] axi_data_V1_i_i_i_reg_191;
reg   [8:0] i_i_i_i_reg_201;
reg   [0:0] eol_i_i_i_phi_fu_216_p4;
reg   [0:0] axi_last_V_2_i_i_i_phi_fu_262_p4;
reg   [23:0] p_Val2_s_phi_fu_274_p4;
wire   [0:0] ap_phi_precharge_reg_pp1_iter1_axi_last_V_2_i_i_i_reg_257;
wire   [23:0] ap_phi_precharge_reg_pp1_iter1_p_Val2_s_reg_270;
reg    ap_reg_grp_reg_unsigned_short_s_fu_331_ap_start;
reg    ap_block_state1_ignore_call21;
reg    ap_reg_grp_reg_unsigned_short_s_fu_337_ap_start;
reg    ap_block_state1_ignore_call22;
reg    img_V_val_0_V1_update;
reg    ap_block_pp1_stage0_flag00001001;
reg   [0:0] sof_1_i_i_i_fu_112;
wire   [9:0] i_cast_i_i_i_fu_357_p1;
wire   [7:0] pix_val_2_V_fu_411_p4;
wire   [7:0] pix_val_0_V_fu_397_p4;
wire   [7:0] pix_val_1_V_8_fu_407_p1;
wire   [0:0] tmp_user_V_fu_343_p1;
reg   [8:0] ap_NS_fsm;
reg    ap_idle_pp1;
wire    ap_enable_pp1;
reg    ap_idle_pp2;
wire    ap_enable_pp2;
reg    ap_condition_511;

// power-on initialization
initial begin
#0 ap_done_reg = 1'b0;
#0 ap_CS_fsm = 9'd1;
#0 s_axis_video_V_data_V_0_sel_rd = 1'b0;
#0 s_axis_video_V_data_V_0_sel_wr = 1'b0;
#0 s_axis_video_V_data_V_0_state = 2'd0;
#0 s_axis_video_V_user_V_0_sel_rd = 1'b0;
#0 s_axis_video_V_user_V_0_sel_wr = 1'b0;
#0 s_axis_video_V_user_V_0_state = 2'd0;
#0 s_axis_video_V_last_V_0_sel_rd = 1'b0;
#0 s_axis_video_V_last_V_0_sel_wr = 1'b0;
#0 s_axis_video_V_last_V_0_state = 2'd0;
#0 s_axis_video_V_dest_V_0_state = 2'd0;
#0 ap_enable_reg_pp1_iter1 = 1'b0;
#0 ap_enable_reg_pp2_iter1 = 1'b0;
#0 ap_enable_reg_pp1_iter0 = 1'b0;
#0 ap_enable_reg_pp2_iter0 = 1'b0;
#0 ap_reg_grp_reg_unsigned_short_s_fu_331_ap_start = 1'b0;
#0 ap_reg_grp_reg_unsigned_short_s_fu_337_ap_start = 1'b0;
end

design_1_v_frmbuf_wr_0_0_reg_unsigned_short_s grp_reg_unsigned_short_s_fu_331(
    .ap_clk(ap_clk),
    .ap_rst(ap_rst),
    .ap_start(grp_reg_unsigned_short_s_fu_331_ap_start),
    .ap_done(grp_reg_unsigned_short_s_fu_331_ap_done),
    .ap_idle(grp_reg_unsigned_short_s_fu_331_ap_idle),
    .ap_ready(grp_reg_unsigned_short_s_fu_331_ap_ready),
    .in_r(Height_cast_i_i_i_reg_450),
    .ap_return(grp_reg_unsigned_short_s_fu_331_ap_return)
);

design_1_v_frmbuf_wr_0_0_reg_unsigned_short_s grp_reg_unsigned_short_s_fu_337(
    .ap_clk(ap_clk),
    .ap_rst(ap_rst),
    .ap_start(grp_reg_unsigned_short_s_fu_337_ap_start),
    .ap_done(grp_reg_unsigned_short_s_fu_337_ap_done),
    .ap_idle(grp_reg_unsigned_short_s_fu_337_ap_idle),
    .ap_ready(grp_reg_unsigned_short_s_fu_337_ap_ready),
    .in_r(HwReg_width_cast9_lo_2_reg_445),
    .ap_return(grp_reg_unsigned_short_s_fu_337_ap_return)
);

always @ (posedge ap_clk) begin
    if (ap_rst == 1'b1) begin
        ap_CS_fsm <= ap_ST_fsm_state1;
    end else begin
        ap_CS_fsm <= ap_NS_fsm;
    end
end

always @ (posedge ap_clk) begin
    if (ap_rst == 1'b1) begin
        ap_done_reg <= 1'b0;
    end else begin
        if ((1'b1 == ap_continue)) begin
            ap_done_reg <= 1'b0;
        end else if (((1'b1 == ap_CS_fsm_state5) & (1'd1 == exitcond5_i_i_i_fu_361_p2))) begin
            ap_done_reg <= 1'b1;
        end
    end
end

always @ (posedge ap_clk) begin
    if (ap_rst == 1'b1) begin
        ap_enable_reg_pp1_iter0 <= 1'b0;
    end else begin
        if (((1'b1 == ap_CS_fsm_pp1_stage0) & (ap_block_pp1_stage0_flag00011011 == 1'b0) & (1'd1 == exitcond6_i_i_i_fu_372_p2))) begin
            ap_enable_reg_pp1_iter0 <= 1'b0;
        end else if (((1'b1 == ap_CS_fsm_state5) & (1'd0 == exitcond5_i_i_i_fu_361_p2))) begin
            ap_enable_reg_pp1_iter0 <= 1'b1;
        end
    end
end

always @ (posedge ap_clk) begin
    if (ap_rst == 1'b1) begin
        ap_enable_reg_pp1_iter1 <= 1'b0;
    end else begin
        if ((ap_block_pp1_stage0_flag00011011 == 1'b0)) begin
            ap_enable_reg_pp1_iter1 <= ap_enable_reg_pp1_iter0;
        end else if (((1'b1 == ap_CS_fsm_state5) & (1'd0 == exitcond5_i_i_i_fu_361_p2))) begin
            ap_enable_reg_pp1_iter1 <= 1'b0;
        end
    end
end

always @ (posedge ap_clk) begin
    if (ap_rst == 1'b1) begin
        ap_enable_reg_pp2_iter0 <= 1'b0;
    end else begin
        if (((1'b1 == ap_CS_fsm_pp2_stage0) & (ap_block_pp2_stage0_flag00011011 == 1'b0) & (1'd1 == eol_2_i_i_i_phi_fu_285_p4))) begin
            ap_enable_reg_pp2_iter0 <= 1'b0;
        end else if ((1'b1 == ap_CS_fsm_state8)) begin
            ap_enable_reg_pp2_iter0 <= 1'b1;
        end
    end
end

always @ (posedge ap_clk) begin
    if (ap_rst == 1'b1) begin
        ap_enable_reg_pp2_iter1 <= 1'b0;
    end else begin
        if ((ap_block_pp2_stage0_flag00011011 == 1'b0)) begin
            ap_enable_reg_pp2_iter1 <= ap_enable_reg_pp2_iter0;
        end else if ((1'b1 == ap_CS_fsm_state8)) begin
            ap_enable_reg_pp2_iter1 <= 1'b0;
        end
    end
end

always @ (posedge ap_clk) begin
    if (ap_rst == 1'b1) begin
        ap_reg_grp_reg_unsigned_short_s_fu_331_ap_start <= 1'b0;
    end else begin
        if (((1'b1 == ap_CS_fsm_state1) & ~((1'b0 == ap_start) | (ap_done_reg == 1'b1) | (1'b0 == HwReg_height_cast8_l_2_empty_n) | (1'b0 == HwReg_width_cast9_lo_1_empty_n) | (1'b0 == HwReg_height_cast8_l_1_full_n) | (1'b0 == HwReg_width_cast9_lo_full_n)))) begin
            ap_reg_grp_reg_unsigned_short_s_fu_331_ap_start <= 1'b1;
        end else if ((1'b1 == grp_reg_unsigned_short_s_fu_331_ap_ready)) begin
            ap_reg_grp_reg_unsigned_short_s_fu_331_ap_start <= 1'b0;
        end
    end
end

always @ (posedge ap_clk) begin
    if (ap_rst == 1'b1) begin
        ap_reg_grp_reg_unsigned_short_s_fu_337_ap_start <= 1'b0;
    end else begin
        if (((1'b1 == ap_CS_fsm_state1) & ~((1'b0 == ap_start) | (ap_done_reg == 1'b1) | (1'b0 == HwReg_height_cast8_l_2_empty_n) | (1'b0 == HwReg_width_cast9_lo_1_empty_n) | (1'b0 == HwReg_height_cast8_l_1_full_n) | (1'b0 == HwReg_width_cast9_lo_full_n)))) begin
            ap_reg_grp_reg_unsigned_short_s_fu_337_ap_start <= 1'b1;
        end else if ((1'b1 == grp_reg_unsigned_short_s_fu_337_ap_ready)) begin
            ap_reg_grp_reg_unsigned_short_s_fu_337_ap_start <= 1'b0;
        end
    end
end

always @ (posedge ap_clk) begin
    if (ap_rst == 1'b1) begin
        s_axis_video_V_data_V_0_sel_rd <= 1'b0;
    end else begin
        if (((1'b1 == s_axis_video_V_data_V_0_ack_out) & (1'b1 == s_axis_video_V_data_V_0_vld_out))) begin
            s_axis_video_V_data_V_0_sel_rd <= ~s_axis_video_V_data_V_0_sel_rd;
        end
    end
end

always @ (posedge ap_clk) begin
    if (ap_rst == 1'b1) begin
        s_axis_video_V_data_V_0_sel_wr <= 1'b0;
    end else begin
        if (((1'b1 == s_axis_video_V_data_V_0_vld_in) & (1'b1 == s_axis_video_V_data_V_0_ack_in))) begin
            s_axis_video_V_data_V_0_sel_wr <= ~s_axis_video_V_data_V_0_sel_wr;
        end
    end
end

always @ (posedge ap_clk) begin
    if (ap_rst == 1'b1) begin
        s_axis_video_V_data_V_0_state <= 2'd0;
    end else begin
        if ((((1'b0 == s_axis_video_V_data_V_0_vld_in) & (1'b1 == s_axis_video_V_data_V_0_ack_out) & (s_axis_video_V_data_V_0_state == 2'd3)) | ((1'b0 == s_axis_video_V_data_V_0_vld_in) & (s_axis_video_V_data_V_0_state == 2'd2)))) begin
            s_axis_video_V_data_V_0_state <= 2'd2;
        end else if ((((1'b1 == s_axis_video_V_data_V_0_vld_in) & (1'b0 == s_axis_video_V_data_V_0_ack_out) & (s_axis_video_V_data_V_0_state == 2'd3)) | ((1'b0 == s_axis_video_V_data_V_0_ack_out) & (s_axis_video_V_data_V_0_state == 2'd1)))) begin
            s_axis_video_V_data_V_0_state <= 2'd1;
        end else if ((((1'b1 == s_axis_video_V_data_V_0_vld_in) & (s_axis_video_V_data_V_0_state == 2'd2)) | ((1'b1 == s_axis_video_V_data_V_0_ack_out) & (s_axis_video_V_data_V_0_state == 2'd1)) | ((s_axis_video_V_data_V_0_state == 2'd3) & ~((1'b1 == s_axis_video_V_data_V_0_vld_in) & (1'b0 == s_axis_video_V_data_V_0_ack_out)) & ~((1'b0 == s_axis_video_V_data_V_0_vld_in) & (1'b1 == s_axis_video_V_data_V_0_ack_out))))) begin
            s_axis_video_V_data_V_0_state <= 2'd3;
        end else begin
            s_axis_video_V_data_V_0_state <= 2'd2;
        end
    end
end

always @ (posedge ap_clk) begin
    if (ap_rst == 1'b1) begin
        s_axis_video_V_dest_V_0_state <= 2'd0;
    end else begin
        if ((((1'b0 == s_axis_video_V_dest_V_0_vld_in) & (1'b1 == s_axis_video_V_dest_V_0_ack_out) & (2'd3 == s_axis_video_V_dest_V_0_state)) | ((1'b0 == s_axis_video_V_dest_V_0_vld_in) & (2'd2 == s_axis_video_V_dest_V_0_state)))) begin
            s_axis_video_V_dest_V_0_state <= 2'd2;
        end else if ((((1'b1 == s_axis_video_V_dest_V_0_vld_in) & (1'b0 == s_axis_video_V_dest_V_0_ack_out) & (2'd3 == s_axis_video_V_dest_V_0_state)) | ((1'b0 == s_axis_video_V_dest_V_0_ack_out) & (2'd1 == s_axis_video_V_dest_V_0_state)))) begin
            s_axis_video_V_dest_V_0_state <= 2'd1;
        end else if ((((1'b1 == s_axis_video_V_dest_V_0_vld_in) & (2'd2 == s_axis_video_V_dest_V_0_state)) | ((1'b1 == s_axis_video_V_dest_V_0_ack_out) & (2'd1 == s_axis_video_V_dest_V_0_state)) | ((2'd3 == s_axis_video_V_dest_V_0_state) & ~((1'b1 == s_axis_video_V_dest_V_0_vld_in) & (1'b0 == s_axis_video_V_dest_V_0_ack_out)) & ~((1'b0 == s_axis_video_V_dest_V_0_vld_in) & (1'b1 == s_axis_video_V_dest_V_0_ack_out))))) begin
            s_axis_video_V_dest_V_0_state <= 2'd3;
        end else begin
            s_axis_video_V_dest_V_0_state <= 2'd2;
        end
    end
end

always @ (posedge ap_clk) begin
    if (ap_rst == 1'b1) begin
        s_axis_video_V_last_V_0_sel_rd <= 1'b0;
    end else begin
        if (((1'b1 == s_axis_video_V_last_V_0_ack_out) & (1'b1 == s_axis_video_V_last_V_0_vld_out))) begin
            s_axis_video_V_last_V_0_sel_rd <= ~s_axis_video_V_last_V_0_sel_rd;
        end
    end
end

always @ (posedge ap_clk) begin
    if (ap_rst == 1'b1) begin
        s_axis_video_V_last_V_0_sel_wr <= 1'b0;
    end else begin
        if (((1'b1 == s_axis_video_V_last_V_0_vld_in) & (1'b1 == s_axis_video_V_last_V_0_ack_in))) begin
            s_axis_video_V_last_V_0_sel_wr <= ~s_axis_video_V_last_V_0_sel_wr;
        end
    end
end

always @ (posedge ap_clk) begin
    if (ap_rst == 1'b1) begin
        s_axis_video_V_last_V_0_state <= 2'd0;
    end else begin
        if ((((1'b0 == s_axis_video_V_last_V_0_vld_in) & (1'b1 == s_axis_video_V_last_V_0_ack_out) & (2'd3 == s_axis_video_V_last_V_0_state)) | ((1'b0 == s_axis_video_V_last_V_0_vld_in) & (2'd2 == s_axis_video_V_last_V_0_state)))) begin
            s_axis_video_V_last_V_0_state <= 2'd2;
        end else if ((((1'b1 == s_axis_video_V_last_V_0_vld_in) & (1'b0 == s_axis_video_V_last_V_0_ack_out) & (2'd3 == s_axis_video_V_last_V_0_state)) | ((1'b0 == s_axis_video_V_last_V_0_ack_out) & (2'd1 == s_axis_video_V_last_V_0_state)))) begin
            s_axis_video_V_last_V_0_state <= 2'd1;
        end else if ((((1'b1 == s_axis_video_V_last_V_0_vld_in) & (2'd2 == s_axis_video_V_last_V_0_state)) | ((1'b1 == s_axis_video_V_last_V_0_ack_out) & (2'd1 == s_axis_video_V_last_V_0_state)) | ((2'd3 == s_axis_video_V_last_V_0_state) & ~((1'b1 == s_axis_video_V_last_V_0_vld_in) & (1'b0 == s_axis_video_V_last_V_0_ack_out)) & ~((1'b0 == s_axis_video_V_last_V_0_vld_in) & (1'b1 == s_axis_video_V_last_V_0_ack_out))))) begin
            s_axis_video_V_last_V_0_state <= 2'd3;
        end else begin
            s_axis_video_V_last_V_0_state <= 2'd2;
        end
    end
end

always @ (posedge ap_clk) begin
    if (ap_rst == 1'b1) begin
        s_axis_video_V_user_V_0_sel_rd <= 1'b0;
    end else begin
        if (((1'b1 == s_axis_video_V_user_V_0_ack_out) & (1'b1 == s_axis_video_V_user_V_0_vld_out))) begin
            s_axis_video_V_user_V_0_sel_rd <= ~s_axis_video_V_user_V_0_sel_rd;
        end
    end
end

always @ (posedge ap_clk) begin
    if (ap_rst == 1'b1) begin
        s_axis_video_V_user_V_0_sel_wr <= 1'b0;
    end else begin
        if (((1'b1 == s_axis_video_V_user_V_0_vld_in) & (1'b1 == s_axis_video_V_user_V_0_ack_in))) begin
            s_axis_video_V_user_V_0_sel_wr <= ~s_axis_video_V_user_V_0_sel_wr;
        end
    end
end

always @ (posedge ap_clk) begin
    if (ap_rst == 1'b1) begin
        s_axis_video_V_user_V_0_state <= 2'd0;
    end else begin
        if ((((1'b0 == s_axis_video_V_user_V_0_vld_in) & (1'b1 == s_axis_video_V_user_V_0_ack_out) & (2'd3 == s_axis_video_V_user_V_0_state)) | ((1'b0 == s_axis_video_V_user_V_0_vld_in) & (2'd2 == s_axis_video_V_user_V_0_state)))) begin
            s_axis_video_V_user_V_0_state <= 2'd2;
        end else if ((((1'b1 == s_axis_video_V_user_V_0_vld_in) & (1'b0 == s_axis_video_V_user_V_0_ack_out) & (2'd3 == s_axis_video_V_user_V_0_state)) | ((1'b0 == s_axis_video_V_user_V_0_ack_out) & (2'd1 == s_axis_video_V_user_V_0_state)))) begin
            s_axis_video_V_user_V_0_state <= 2'd1;
        end else if ((((1'b1 == s_axis_video_V_user_V_0_vld_in) & (2'd2 == s_axis_video_V_user_V_0_state)) | ((1'b1 == s_axis_video_V_user_V_0_ack_out) & (2'd1 == s_axis_video_V_user_V_0_state)) | ((2'd3 == s_axis_video_V_user_V_0_state) & ~((1'b1 == s_axis_video_V_user_V_0_vld_in) & (1'b0 == s_axis_video_V_user_V_0_ack_out)) & ~((1'b0 == s_axis_video_V_user_V_0_vld_in) & (1'b1 == s_axis_video_V_user_V_0_ack_out))))) begin
            s_axis_video_V_user_V_0_state <= 2'd3;
        end else begin
            s_axis_video_V_user_V_0_state <= 2'd2;
        end
    end
end

always @ (posedge ap_clk) begin
    if ((1'b1 == ap_CS_fsm_state4)) begin
        axi_data_V1_i_i_i_reg_191 <= tmp_data_V_reg_470;
    end else if ((1'b1 == ap_CS_fsm_state11)) begin
        axi_data_V1_i_i_i_reg_191 <= axi_data_V_3_i_i_i_reg_305;
    end
end

always @ (posedge ap_clk) begin
    if (((1'b1 == ap_CS_fsm_pp1_stage0) & (1'b1 == ap_enable_reg_pp1_iter1) & (1'd0 == exitcond6_i_i_i_reg_506) & (ap_block_pp1_stage0_flag00011001 == 1'b0))) begin
        axi_data_V_1_i_i_i_reg_246 <= p_Val2_s_phi_fu_274_p4;
    end else if (((1'b1 == ap_CS_fsm_state5) & (1'd0 == exitcond5_i_i_i_fu_361_p2))) begin
        axi_data_V_1_i_i_i_reg_246 <= axi_data_V1_i_i_i_reg_191;
    end
end

always @ (posedge ap_clk) begin
    if ((1'b1 == ap_CS_fsm_state8)) begin
        axi_data_V_3_i_i_i_reg_305 <= axi_data_V_1_i_i_i_reg_246;
    end else if (((1'b1 == ap_CS_fsm_pp2_stage0) & (1'b1 == ap_enable_reg_pp2_iter1) & (1'd0 == eol_2_i_i_i_reg_282) & (ap_block_pp2_stage0_flag00011001 == 1'b0))) begin
        axi_data_V_3_i_i_i_reg_305 <= s_axis_video_V_data_V_0_data_out;
    end
end

always @ (posedge ap_clk) begin
    if ((1'b1 == ap_CS_fsm_state4)) begin
        axi_last_V1_i_i_i_reg_181 <= tmp_last_V_reg_478;
    end else if ((1'b1 == ap_CS_fsm_state11)) begin
        axi_last_V1_i_i_i_reg_181 <= axi_last_V_3_i_i_i_reg_293;
    end
end

always @ (posedge ap_clk) begin
    if ((1'b1 == ap_CS_fsm_state8)) begin
        axi_last_V_3_i_i_i_reg_293 <= eol_reg_235;
    end else if (((1'b1 == ap_CS_fsm_pp2_stage0) & (1'b1 == ap_enable_reg_pp2_iter1) & (1'd0 == eol_2_i_i_i_reg_282) & (ap_block_pp2_stage0_flag00011001 == 1'b0))) begin
        axi_last_V_3_i_i_i_reg_293 <= s_axis_video_V_last_V_0_data_out;
    end
end

always @ (posedge ap_clk) begin
    if ((1'b1 == ap_CS_fsm_state8)) begin
        eol_2_i_i_i_reg_282 <= eol_i_i_i_reg_212;
    end else if (((1'b1 == ap_CS_fsm_pp2_stage0) & (1'b1 == ap_enable_reg_pp2_iter1) & (1'd0 == eol_2_i_i_i_reg_282) & (ap_block_pp2_stage0_flag00011001 == 1'b0))) begin
        eol_2_i_i_i_reg_282 <= s_axis_video_V_last_V_0_data_out;
    end
end

always @ (posedge ap_clk) begin
    if (((1'b1 == ap_CS_fsm_pp1_stage0) & (1'b1 == ap_enable_reg_pp1_iter1) & (1'd0 == exitcond6_i_i_i_reg_506) & (ap_block_pp1_stage0_flag00011001 == 1'b0))) begin
        eol_i_i_i_reg_212 <= axi_last_V_2_i_i_i_phi_fu_262_p4;
    end else if (((1'b1 == ap_CS_fsm_state5) & (1'd0 == exitcond5_i_i_i_fu_361_p2))) begin
        eol_i_i_i_reg_212 <= 1'd0;
    end
end

always @ (posedge ap_clk) begin
    if (((1'b1 == ap_CS_fsm_pp1_stage0) & (1'b1 == ap_enable_reg_pp1_iter1) & (1'd0 == exitcond6_i_i_i_reg_506) & (ap_block_pp1_stage0_flag00011001 == 1'b0))) begin
        eol_reg_235 <= axi_last_V_2_i_i_i_phi_fu_262_p4;
    end else if (((1'b1 == ap_CS_fsm_state5) & (1'd0 == exitcond5_i_i_i_fu_361_p2))) begin
        eol_reg_235 <= axi_last_V1_i_i_i_reg_181;
    end
end

always @ (posedge ap_clk) begin
    if ((1'b1 == ap_CS_fsm_state4)) begin
        i_i_i_i_reg_201 <= 9'd0;
    end else if ((1'b1 == ap_CS_fsm_state11)) begin
        i_i_i_i_reg_201 <= i_reg_501;
    end
end

always @ (posedge ap_clk) begin
    if (((1'b1 == ap_CS_fsm_pp1_stage0) & (ap_block_pp1_stage0_flag00011001 == 1'b0) & (1'b1 == ap_enable_reg_pp1_iter0) & (1'd0 == exitcond6_i_i_i_fu_372_p2))) begin
        j_i_i_i_reg_224 <= j_fu_377_p2;
    end else if (((1'b1 == ap_CS_fsm_state5) & (1'd0 == exitcond5_i_i_i_fu_361_p2))) begin
        j_i_i_i_reg_224 <= 10'd0;
    end
end

always @ (posedge ap_clk) begin
    if (((1'b1 == ap_CS_fsm_pp1_stage0) & (ap_block_pp1_stage0_flag00011001 == 1'b0) & (1'b1 == ap_enable_reg_pp1_iter0) & (1'd0 == exitcond6_i_i_i_fu_372_p2))) begin
        sof_1_i_i_i_fu_112 <= 1'd0;
    end else if ((1'b1 == ap_CS_fsm_state4)) begin
        sof_1_i_i_i_fu_112 <= 1'd1;
    end
end

always @ (posedge ap_clk) begin
    if (((1'b1 == ap_CS_fsm_state1) & ~((1'b0 == ap_start) | (ap_done_reg == 1'b1) | (1'b0 == HwReg_height_cast8_l_2_empty_n) | (1'b0 == HwReg_width_cast9_lo_1_empty_n) | (1'b0 == HwReg_height_cast8_l_1_full_n) | (1'b0 == HwReg_width_cast9_lo_full_n)))) begin
        Height_cast_i_i_i_reg_450[8 : 0] <= Height_cast_i_i_i_fu_327_p1[8 : 0];
        HwReg_width_cast9_lo_2_reg_445 <= HwReg_width_cast9_lo_1_dout;
    end
end

always @ (posedge ap_clk) begin
    if (((1'b1 == ap_CS_fsm_pp1_stage0) & (ap_block_pp1_stage0_flag00011001 == 1'b0) & (1'd0 == exitcond6_i_i_i_fu_372_p2))) begin
        brmerge_i_i_i_reg_515 <= brmerge_i_i_i_fu_386_p2;
    end
end

always @ (posedge ap_clk) begin
    if (((1'b1 == ap_CS_fsm_pp1_stage0) & (ap_block_pp1_stage0_flag00011001 == 1'b0))) begin
        exitcond6_i_i_i_reg_506 <= exitcond6_i_i_i_fu_372_p2;
    end
end

always @ (posedge ap_clk) begin
    if ((1'b1 == ap_CS_fsm_state5)) begin
        i_reg_501 <= i_fu_366_p2;
    end
end

always @ (posedge ap_clk) begin
    if ((1'b1 == s_axis_video_V_data_V_0_load_A)) begin
        s_axis_video_V_data_V_0_payload_A <= s_axis_video_TDATA;
    end
end

always @ (posedge ap_clk) begin
    if ((1'b1 == s_axis_video_V_data_V_0_load_B)) begin
        s_axis_video_V_data_V_0_payload_B <= s_axis_video_TDATA;
    end
end

always @ (posedge ap_clk) begin
    if ((1'b1 == s_axis_video_V_last_V_0_load_A)) begin
        s_axis_video_V_last_V_0_payload_A <= s_axis_video_TLAST;
    end
end

always @ (posedge ap_clk) begin
    if ((1'b1 == s_axis_video_V_last_V_0_load_B)) begin
        s_axis_video_V_last_V_0_payload_B <= s_axis_video_TLAST;
    end
end

always @ (posedge ap_clk) begin
    if ((1'b1 == s_axis_video_V_user_V_0_load_A)) begin
        s_axis_video_V_user_V_0_payload_A <= s_axis_video_TUSER;
    end
end

always @ (posedge ap_clk) begin
    if ((1'b1 == s_axis_video_V_user_V_0_load_B)) begin
        s_axis_video_V_user_V_0_payload_B <= s_axis_video_TUSER;
    end
end

always @ (posedge ap_clk) begin
    if ((1'b1 == ap_CS_fsm_state4)) begin
        sel_tmp2_i_reg_490 <= sel_tmp2_i_fu_347_p2;
    end
end

always @ (posedge ap_clk) begin
    if (((1'b1 == ap_CS_fsm_state3) & (s_axis_video_V_data_V_0_vld_out == 1'b1))) begin
        tmp_data_V_reg_470 <= s_axis_video_V_data_V_0_data_out;
        tmp_last_V_reg_478 <= s_axis_video_V_last_V_0_data_out;
    end
end

always @ (posedge ap_clk) begin
    if (((1'b1 == ap_CS_fsm_state2) & (ap_block_state2_on_subcall_done == 1'b0))) begin
        tmp_i_i_i_235_reg_465 <= grp_reg_unsigned_short_s_fu_337_ap_return;
        tmp_i_i_i_reg_460 <= grp_reg_unsigned_short_s_fu_331_ap_return;
    end
end

always @ (*) begin
    if (((1'b1 == ap_CS_fsm_state1) & ~((1'b0 == ap_start) | (ap_done_reg == 1'b1)))) begin
        HwReg_height_cast8_l_1_blk_n = HwReg_height_cast8_l_1_full_n;
    end else begin
        HwReg_height_cast8_l_1_blk_n = 1'b1;
    end
end

always @ (*) begin
    if (((1'b1 == ap_CS_fsm_state1) & ~((1'b0 == ap_start) | (ap_done_reg == 1'b1) | (1'b0 == HwReg_height_cast8_l_2_empty_n) | (1'b0 == HwReg_width_cast9_lo_1_empty_n) | (1'b0 == HwReg_height_cast8_l_1_full_n) | (1'b0 == HwReg_width_cast9_lo_full_n)))) begin
        HwReg_height_cast8_l_1_write = 1'b1;
    end else begin
        HwReg_height_cast8_l_1_write = 1'b0;
    end
end

always @ (*) begin
    if (((1'b1 == ap_CS_fsm_state1) & ~((1'b0 == ap_start) | (ap_done_reg == 1'b1)))) begin
        HwReg_height_cast8_l_2_blk_n = HwReg_height_cast8_l_2_empty_n;
    end else begin
        HwReg_height_cast8_l_2_blk_n = 1'b1;
    end
end

always @ (*) begin
    if (((1'b1 == ap_CS_fsm_state1) & ~((1'b0 == ap_start) | (ap_done_reg == 1'b1) | (1'b0 == HwReg_height_cast8_l_2_empty_n) | (1'b0 == HwReg_width_cast9_lo_1_empty_n) | (1'b0 == HwReg_height_cast8_l_1_full_n) | (1'b0 == HwReg_width_cast9_lo_full_n)))) begin
        HwReg_height_cast8_l_2_read = 1'b1;
    end else begin
        HwReg_height_cast8_l_2_read = 1'b0;
    end
end

always @ (*) begin
    if (((1'b1 == ap_CS_fsm_state1) & ~((1'b0 == ap_start) | (ap_done_reg == 1'b1)))) begin
        HwReg_width_cast9_lo_1_blk_n = HwReg_width_cast9_lo_1_empty_n;
    end else begin
        HwReg_width_cast9_lo_1_blk_n = 1'b1;
    end
end

always @ (*) begin
    if (((1'b1 == ap_CS_fsm_state1) & ~((1'b0 == ap_start) | (ap_done_reg == 1'b1) | (1'b0 == HwReg_height_cast8_l_2_empty_n) | (1'b0 == HwReg_width_cast9_lo_1_empty_n) | (1'b0 == HwReg_height_cast8_l_1_full_n) | (1'b0 == HwReg_width_cast9_lo_full_n)))) begin
        HwReg_width_cast9_lo_1_read = 1'b1;
    end else begin
        HwReg_width_cast9_lo_1_read = 1'b0;
    end
end

always @ (*) begin
    if (((1'b1 == ap_CS_fsm_state1) & ~((1'b0 == ap_start) | (ap_done_reg == 1'b1)))) begin
        HwReg_width_cast9_lo_blk_n = HwReg_width_cast9_lo_full_n;
    end else begin
        HwReg_width_cast9_lo_blk_n = 1'b1;
    end
end

always @ (*) begin
    if (((1'b1 == ap_CS_fsm_state1) & ~((1'b0 == ap_start) | (ap_done_reg == 1'b1) | (1'b0 == HwReg_height_cast8_l_2_empty_n) | (1'b0 == HwReg_width_cast9_lo_1_empty_n) | (1'b0 == HwReg_height_cast8_l_1_full_n) | (1'b0 == HwReg_width_cast9_lo_full_n)))) begin
        HwReg_width_cast9_lo_write = 1'b1;
    end else begin
        HwReg_width_cast9_lo_write = 1'b0;
    end
end

always @ (*) begin
    if (((1'b1 == ap_CS_fsm_state5) & (1'd1 == exitcond5_i_i_i_fu_361_p2))) begin
        ap_done = 1'b1;
    end else begin
        ap_done = ap_done_reg;
    end
end

always @ (*) begin
    if (((1'b0 == ap_start) & (1'b1 == ap_CS_fsm_state1))) begin
        ap_idle = 1'b1;
    end else begin
        ap_idle = 1'b0;
    end
end

always @ (*) begin
    if (((1'b0 == ap_enable_reg_pp1_iter0) & (1'b0 == ap_enable_reg_pp1_iter1))) begin
        ap_idle_pp1 = 1'b1;
    end else begin
        ap_idle_pp1 = 1'b0;
    end
end

always @ (*) begin
    if (((1'b0 == ap_enable_reg_pp2_iter0) & (1'b0 == ap_enable_reg_pp2_iter1))) begin
        ap_idle_pp2 = 1'b1;
    end else begin
        ap_idle_pp2 = 1'b0;
    end
end

always @ (*) begin
    if (((1'b1 == ap_CS_fsm_state5) & (1'd1 == exitcond5_i_i_i_fu_361_p2))) begin
        ap_ready = 1'b1;
    end else begin
        ap_ready = 1'b0;
    end
end

always @ (*) begin
    if ((ap_condition_511 == 1'b1)) begin
        if ((1'd1 == brmerge_i_i_i_reg_515)) begin
            axi_last_V_2_i_i_i_phi_fu_262_p4 = eol_reg_235;
        end else if ((1'd0 == brmerge_i_i_i_reg_515)) begin
            axi_last_V_2_i_i_i_phi_fu_262_p4 = s_axis_video_V_last_V_0_data_out;
        end else begin
            axi_last_V_2_i_i_i_phi_fu_262_p4 = ap_phi_precharge_reg_pp1_iter1_axi_last_V_2_i_i_i_reg_257;
        end
    end else begin
        axi_last_V_2_i_i_i_phi_fu_262_p4 = ap_phi_precharge_reg_pp1_iter1_axi_last_V_2_i_i_i_reg_257;
    end
end

always @ (*) begin
    if (((1'b1 == ap_CS_fsm_pp2_stage0) & (1'b1 == ap_enable_reg_pp2_iter1) & (ap_block_pp2_stage0_flag00000000 == 1'b0) & (1'd0 == eol_2_i_i_i_reg_282))) begin
        eol_2_i_i_i_phi_fu_285_p4 = s_axis_video_V_last_V_0_data_out;
    end else begin
        eol_2_i_i_i_phi_fu_285_p4 = eol_2_i_i_i_reg_282;
    end
end

always @ (*) begin
    if (((1'b1 == ap_CS_fsm_pp1_stage0) & (1'b1 == ap_enable_reg_pp1_iter1) & (ap_block_pp1_stage0_flag00000000 == 1'b0) & (1'd0 == exitcond6_i_i_i_reg_506))) begin
        eol_i_i_i_phi_fu_216_p4 = axi_last_V_2_i_i_i_phi_fu_262_p4;
    end else begin
        eol_i_i_i_phi_fu_216_p4 = eol_i_i_i_reg_212;
    end
end

always @ (*) begin
    if (((1'b1 == ap_CS_fsm_pp1_stage0) & (1'b1 == ap_enable_reg_pp1_iter1) & (1'd0 == exitcond6_i_i_i_reg_506) & (ap_block_pp1_stage0_flag00011001 == 1'b0))) begin
        img_V_val_0_V1_update = 1'b1;
    end else begin
        img_V_val_0_V1_update = 1'b0;
    end
end

always @ (*) begin
    if (((1'b1 == ap_CS_fsm_pp1_stage0) & (1'b1 == ap_enable_reg_pp1_iter1) & (ap_block_pp1_stage0_flag00000000 == 1'b0) & (1'd0 == exitcond6_i_i_i_reg_506))) begin
        img_V_val_0_V_blk_n = img_V_val_0_V_full_n;
    end else begin
        img_V_val_0_V_blk_n = 1'b1;
    end
end

always @ (*) begin
    if (((1'b1 == ap_CS_fsm_pp1_stage0) & (1'b1 == ap_enable_reg_pp1_iter1) & (ap_block_pp1_stage0_flag00000000 == 1'b0) & (1'd0 == exitcond6_i_i_i_reg_506))) begin
        img_V_val_1_V_blk_n = img_V_val_1_V_full_n;
    end else begin
        img_V_val_1_V_blk_n = 1'b1;
    end
end

always @ (*) begin
    if (((1'b1 == ap_CS_fsm_pp1_stage0) & (1'b1 == ap_enable_reg_pp1_iter1) & (ap_block_pp1_stage0_flag00000000 == 1'b0) & (1'd0 == exitcond6_i_i_i_reg_506))) begin
        img_V_val_2_V_blk_n = img_V_val_2_V_full_n;
    end else begin
        img_V_val_2_V_blk_n = 1'b1;
    end
end

always @ (*) begin
    if ((ap_condition_511 == 1'b1)) begin
        if ((1'd1 == brmerge_i_i_i_reg_515)) begin
            p_Val2_s_phi_fu_274_p4 = axi_data_V_1_i_i_i_reg_246;
        end else if ((1'd0 == brmerge_i_i_i_reg_515)) begin
            p_Val2_s_phi_fu_274_p4 = s_axis_video_V_data_V_0_data_out;
        end else begin
            p_Val2_s_phi_fu_274_p4 = ap_phi_precharge_reg_pp1_iter1_p_Val2_s_reg_270;
        end
    end else begin
        p_Val2_s_phi_fu_274_p4 = ap_phi_precharge_reg_pp1_iter1_p_Val2_s_reg_270;
    end
end

always @ (*) begin
    if (((1'b1 == ap_CS_fsm_state3) | ((1'b1 == ap_CS_fsm_pp1_stage0) & (1'b1 == ap_enable_reg_pp1_iter1) & (ap_block_pp1_stage0_flag00000000 == 1'b0) & (1'd0 == exitcond6_i_i_i_reg_506) & (1'd0 == brmerge_i_i_i_reg_515)) | ((1'b1 == ap_CS_fsm_pp2_stage0) & (1'b1 == ap_enable_reg_pp2_iter1) & (ap_block_pp2_stage0_flag00000000 == 1'b0) & (1'd0 == eol_2_i_i_i_reg_282)))) begin
        s_axis_video_TDATA_blk_n = s_axis_video_V_data_V_0_state[1'd0];
    end else begin
        s_axis_video_TDATA_blk_n = 1'b1;
    end
end

always @ (*) begin
    if ((((1'b1 == ap_CS_fsm_state3) & (s_axis_video_V_data_V_0_vld_out == 1'b1)) | ((1'b1 == ap_CS_fsm_pp2_stage0) & (1'b1 == ap_enable_reg_pp2_iter1) & (1'd0 == eol_2_i_i_i_reg_282) & (ap_block_pp2_stage0_flag00011001 == 1'b0)) | ((1'b1 == ap_CS_fsm_pp1_stage0) & (1'b1 == ap_enable_reg_pp1_iter1) & (1'b1 == ap_predicate_op80_read_state7) & (ap_block_pp1_stage0_flag00011001 == 1'b0)))) begin
        s_axis_video_V_data_V_0_ack_out = 1'b1;
    end else begin
        s_axis_video_V_data_V_0_ack_out = 1'b0;
    end
end

always @ (*) begin
    if ((1'b1 == s_axis_video_V_data_V_0_sel)) begin
        s_axis_video_V_data_V_0_data_out = s_axis_video_V_data_V_0_payload_B;
    end else begin
        s_axis_video_V_data_V_0_data_out = s_axis_video_V_data_V_0_payload_A;
    end
end

always @ (*) begin
    if ((((1'b1 == ap_CS_fsm_state3) & (s_axis_video_V_data_V_0_vld_out == 1'b1)) | ((1'b1 == ap_CS_fsm_pp2_stage0) & (1'b1 == ap_enable_reg_pp2_iter1) & (1'd0 == eol_2_i_i_i_reg_282) & (ap_block_pp2_stage0_flag00011001 == 1'b0)) | ((1'b1 == ap_CS_fsm_pp1_stage0) & (1'b1 == ap_enable_reg_pp1_iter1) & (1'b1 == ap_predicate_op80_read_state7) & (ap_block_pp1_stage0_flag00011001 == 1'b0)))) begin
        s_axis_video_V_dest_V_0_ack_out = 1'b1;
    end else begin
        s_axis_video_V_dest_V_0_ack_out = 1'b0;
    end
end

always @ (*) begin
    if ((((1'b1 == ap_CS_fsm_state3) & (s_axis_video_V_data_V_0_vld_out == 1'b1)) | ((1'b1 == ap_CS_fsm_pp2_stage0) & (1'b1 == ap_enable_reg_pp2_iter1) & (1'd0 == eol_2_i_i_i_reg_282) & (ap_block_pp2_stage0_flag00011001 == 1'b0)) | ((1'b1 == ap_CS_fsm_pp1_stage0) & (1'b1 == ap_enable_reg_pp1_iter1) & (1'b1 == ap_predicate_op80_read_state7) & (ap_block_pp1_stage0_flag00011001 == 1'b0)))) begin
        s_axis_video_V_last_V_0_ack_out = 1'b1;
    end else begin
        s_axis_video_V_last_V_0_ack_out = 1'b0;
    end
end

always @ (*) begin
    if ((1'b1 == s_axis_video_V_last_V_0_sel)) begin
        s_axis_video_V_last_V_0_data_out = s_axis_video_V_last_V_0_payload_B;
    end else begin
        s_axis_video_V_last_V_0_data_out = s_axis_video_V_last_V_0_payload_A;
    end
end

always @ (*) begin
    if ((((1'b1 == ap_CS_fsm_state3) & (s_axis_video_V_data_V_0_vld_out == 1'b1)) | ((1'b1 == ap_CS_fsm_pp2_stage0) & (1'b1 == ap_enable_reg_pp2_iter1) & (1'd0 == eol_2_i_i_i_reg_282) & (ap_block_pp2_stage0_flag00011001 == 1'b0)) | ((1'b1 == ap_CS_fsm_pp1_stage0) & (1'b1 == ap_enable_reg_pp1_iter1) & (1'b1 == ap_predicate_op80_read_state7) & (ap_block_pp1_stage0_flag00011001 == 1'b0)))) begin
        s_axis_video_V_user_V_0_ack_out = 1'b1;
    end else begin
        s_axis_video_V_user_V_0_ack_out = 1'b0;
    end
end

always @ (*) begin
    if ((1'b1 == s_axis_video_V_user_V_0_sel)) begin
        s_axis_video_V_user_V_0_data_out = s_axis_video_V_user_V_0_payload_B;
    end else begin
        s_axis_video_V_user_V_0_data_out = s_axis_video_V_user_V_0_payload_A;
    end
end

always @ (*) begin
    case (ap_CS_fsm)
        ap_ST_fsm_state1 : begin
            if (((1'b1 == ap_CS_fsm_state1) & ~((1'b0 == ap_start) | (ap_done_reg == 1'b1) | (1'b0 == HwReg_height_cast8_l_2_empty_n) | (1'b0 == HwReg_width_cast9_lo_1_empty_n) | (1'b0 == HwReg_height_cast8_l_1_full_n) | (1'b0 == HwReg_width_cast9_lo_full_n)))) begin
                ap_NS_fsm = ap_ST_fsm_state2;
            end else begin
                ap_NS_fsm = ap_ST_fsm_state1;
            end
        end
        ap_ST_fsm_state2 : begin
            if (((1'b1 == ap_CS_fsm_state2) & (ap_block_state2_on_subcall_done == 1'b0))) begin
                ap_NS_fsm = ap_ST_fsm_state3;
            end else begin
                ap_NS_fsm = ap_ST_fsm_state2;
            end
        end
        ap_ST_fsm_state3 : begin
            if (((1'b1 == ap_CS_fsm_state3) & (s_axis_video_V_data_V_0_vld_out == 1'b1) & (1'd0 == tmp_user_V_fu_343_p1))) begin
                ap_NS_fsm = ap_ST_fsm_state3;
            end else if (((1'b1 == ap_CS_fsm_state3) & (s_axis_video_V_data_V_0_vld_out == 1'b1) & (1'd1 == tmp_user_V_fu_343_p1))) begin
                ap_NS_fsm = ap_ST_fsm_state4;
            end else begin
                ap_NS_fsm = ap_ST_fsm_state3;
            end
        end
        ap_ST_fsm_state4 : begin
            ap_NS_fsm = ap_ST_fsm_state5;
        end
        ap_ST_fsm_state5 : begin
            if (((1'b1 == ap_CS_fsm_state5) & (1'd1 == exitcond5_i_i_i_fu_361_p2))) begin
                ap_NS_fsm = ap_ST_fsm_state1;
            end else begin
                ap_NS_fsm = ap_ST_fsm_pp1_stage0;
            end
        end
        ap_ST_fsm_pp1_stage0 : begin
            if (~((1'b1 == ap_CS_fsm_pp1_stage0) & (1'b1 == ap_enable_reg_pp1_iter1) & (ap_block_pp1_stage0_flag00011011 == 1'b0) & (ap_enable_reg_pp1_iter0 == 1'b0))) begin
                ap_NS_fsm = ap_ST_fsm_pp1_stage0;
            end else if (((1'b1 == ap_CS_fsm_pp1_stage0) & (1'b1 == ap_enable_reg_pp1_iter1) & (ap_block_pp1_stage0_flag00011011 == 1'b0) & (ap_enable_reg_pp1_iter0 == 1'b0))) begin
                ap_NS_fsm = ap_ST_fsm_state8;
            end else begin
                ap_NS_fsm = ap_ST_fsm_pp1_stage0;
            end
        end
        ap_ST_fsm_state8 : begin
            ap_NS_fsm = ap_ST_fsm_pp2_stage0;
        end
        ap_ST_fsm_pp2_stage0 : begin
            if (~((1'b1 == ap_CS_fsm_pp2_stage0) & (1'b1 == ap_enable_reg_pp2_iter1) & (ap_block_pp2_stage0_flag00011011 == 1'b0) & (ap_enable_reg_pp2_iter0 == 1'b0))) begin
                ap_NS_fsm = ap_ST_fsm_pp2_stage0;
            end else if (((1'b1 == ap_CS_fsm_pp2_stage0) & (1'b1 == ap_enable_reg_pp2_iter1) & (ap_block_pp2_stage0_flag00011011 == 1'b0) & (ap_enable_reg_pp2_iter0 == 1'b0))) begin
                ap_NS_fsm = ap_ST_fsm_state11;
            end else begin
                ap_NS_fsm = ap_ST_fsm_pp2_stage0;
            end
        end
        ap_ST_fsm_state11 : begin
            ap_NS_fsm = ap_ST_fsm_state5;
        end
        default : begin
            ap_NS_fsm = 'bx;
        end
    endcase
end

assign Height_cast_i_i_i_fu_327_p1 = HwReg_height_cast8_l_2_dout;

assign HwReg_height_cast8_l_1_din = HwReg_height_cast8_l_2_dout;

assign HwReg_width_cast9_lo_din = HwReg_width_cast9_lo_1_dout;

assign ap_CS_fsm_pp1_stage0 = ap_CS_fsm[32'd5];

assign ap_CS_fsm_pp2_stage0 = ap_CS_fsm[32'd7];

assign ap_CS_fsm_state1 = ap_CS_fsm[32'd0];

assign ap_CS_fsm_state11 = ap_CS_fsm[32'd8];

assign ap_CS_fsm_state2 = ap_CS_fsm[32'd1];

assign ap_CS_fsm_state3 = ap_CS_fsm[32'd2];

assign ap_CS_fsm_state4 = ap_CS_fsm[32'd3];

assign ap_CS_fsm_state5 = ap_CS_fsm[32'd4];

assign ap_CS_fsm_state8 = ap_CS_fsm[32'd6];

assign ap_block_pp1_stage0_flag00000000 = ~(1'b1 == 1'b1);

always @ (*) begin
    ap_block_pp1_stage0_flag00001001 = ((1'b1 == ap_enable_reg_pp1_iter1) & (((1'b0 == s_axis_video_V_data_V_0_vld_out) & (1'b1 == ap_predicate_op80_read_state7)) | ((1'd0 == exitcond6_i_i_i_reg_506) & (1'b0 == img_V_val_0_V1_status))));
end

always @ (*) begin
    ap_block_pp1_stage0_flag00011001 = ((1'b1 == ap_enable_reg_pp1_iter1) & (((1'b0 == s_axis_video_V_data_V_0_vld_out) & (1'b1 == ap_predicate_op80_read_state7)) | ((1'd0 == exitcond6_i_i_i_reg_506) & (1'b0 == img_V_val_0_V1_status))));
end

always @ (*) begin
    ap_block_pp1_stage0_flag00011011 = ((1'b1 == ap_enable_reg_pp1_iter1) & (((1'b0 == s_axis_video_V_data_V_0_vld_out) & (1'b1 == ap_predicate_op80_read_state7)) | ((1'd0 == exitcond6_i_i_i_reg_506) & (1'b0 == img_V_val_0_V1_status))));
end

assign ap_block_pp2_stage0_flag00000000 = ~(1'b1 == 1'b1);

always @ (*) begin
    ap_block_pp2_stage0_flag00011001 = ((1'b1 == ap_enable_reg_pp2_iter1) & (1'd0 == eol_2_i_i_i_reg_282) & (1'b0 == s_axis_video_V_data_V_0_vld_out));
end

always @ (*) begin
    ap_block_pp2_stage0_flag00011011 = ((1'b1 == ap_enable_reg_pp2_iter1) & (1'd0 == eol_2_i_i_i_reg_282) & (1'b0 == s_axis_video_V_data_V_0_vld_out));
end

always @ (*) begin
    ap_block_state1 = ((1'b0 == ap_start) | (ap_done_reg == 1'b1) | (1'b0 == HwReg_height_cast8_l_2_empty_n) | (1'b0 == HwReg_width_cast9_lo_1_empty_n) | (1'b0 == HwReg_height_cast8_l_1_full_n) | (1'b0 == HwReg_width_cast9_lo_full_n));
end

always @ (*) begin
    ap_block_state10_pp2_stage0_iter1 = ((1'd0 == eol_2_i_i_i_reg_282) & (1'b0 == s_axis_video_V_data_V_0_vld_out));
end

always @ (*) begin
    ap_block_state1_ignore_call21 = ((1'b0 == ap_start) | (ap_done_reg == 1'b1) | (1'b0 == HwReg_height_cast8_l_2_empty_n) | (1'b0 == HwReg_width_cast9_lo_1_empty_n) | (1'b0 == HwReg_height_cast8_l_1_full_n) | (1'b0 == HwReg_width_cast9_lo_full_n));
end

always @ (*) begin
    ap_block_state1_ignore_call22 = ((1'b0 == ap_start) | (ap_done_reg == 1'b1) | (1'b0 == HwReg_height_cast8_l_2_empty_n) | (1'b0 == HwReg_width_cast9_lo_1_empty_n) | (1'b0 == HwReg_height_cast8_l_1_full_n) | (1'b0 == HwReg_width_cast9_lo_full_n));
end

always @ (*) begin
    ap_block_state2_on_subcall_done = ((1'b0 == grp_reg_unsigned_short_s_fu_331_ap_done) | (1'b0 == grp_reg_unsigned_short_s_fu_337_ap_done));
end

assign ap_block_state6_pp1_stage0_iter0 = ~(1'b1 == 1'b1);

always @ (*) begin
    ap_block_state7_pp1_stage0_iter1 = (((1'b0 == s_axis_video_V_data_V_0_vld_out) & (1'b1 == ap_predicate_op80_read_state7)) | ((1'd0 == exitcond6_i_i_i_reg_506) & (1'b0 == img_V_val_0_V1_status)));
end

assign ap_block_state9_pp2_stage0_iter0 = ~(1'b1 == 1'b1);

always @ (*) begin
    ap_condition_511 = ((1'b1 == ap_CS_fsm_pp1_stage0) & (1'b1 == ap_enable_reg_pp1_iter1) & (ap_block_pp1_stage0_flag00000000 == 1'b0) & (1'd0 == exitcond6_i_i_i_reg_506));
end

assign ap_enable_pp1 = (ap_idle_pp1 ^ 1'b1);

assign ap_enable_pp2 = (ap_idle_pp2 ^ 1'b1);

assign ap_phi_precharge_reg_pp1_iter1_axi_last_V_2_i_i_i_reg_257 = 'bx;

assign ap_phi_precharge_reg_pp1_iter1_p_Val2_s_reg_270 = 'bx;

always @ (*) begin
    ap_predicate_op80_read_state7 = ((1'd0 == exitcond6_i_i_i_reg_506) & (1'd0 == brmerge_i_i_i_reg_515));
end

assign brmerge_i_i_i_fu_386_p2 = (sof_1_i_i_i_fu_112 | eol_i_i_i_phi_fu_216_p4);

assign exitcond5_i_i_i_fu_361_p2 = ((i_cast_i_i_i_fu_357_p1 == tmp_i_i_i_reg_460) ? 1'b1 : 1'b0);

assign exitcond6_i_i_i_fu_372_p2 = ((j_i_i_i_reg_224 == tmp_i_i_i_235_reg_465) ? 1'b1 : 1'b0);

assign grp_reg_unsigned_short_s_fu_331_ap_start = ap_reg_grp_reg_unsigned_short_s_fu_331_ap_start;

assign grp_reg_unsigned_short_s_fu_337_ap_start = ap_reg_grp_reg_unsigned_short_s_fu_337_ap_start;

assign i_cast_i_i_i_fu_357_p1 = i_i_i_i_reg_201;

assign i_fu_366_p2 = (i_i_i_i_reg_201 + 9'd1);

assign img_V_val_0_V1_status = (img_V_val_0_V_full_n & img_V_val_1_V_full_n & img_V_val_2_V_full_n);

assign img_V_val_0_V_din = ((sel_tmp2_i_reg_490[0:0] === 1'b1) ? pix_val_0_V_fu_397_p4 : pix_val_1_V_8_fu_407_p1);

assign img_V_val_0_V_write = img_V_val_0_V1_update;

assign img_V_val_1_V_din = ((sel_tmp2_i_reg_490[0:0] === 1'b1) ? pix_val_1_V_8_fu_407_p1 : pix_val_2_V_fu_411_p4);

assign img_V_val_1_V_write = img_V_val_0_V1_update;

assign img_V_val_2_V_din = ((sel_tmp2_i_reg_490[0:0] === 1'b1) ? pix_val_2_V_fu_411_p4 : pix_val_0_V_fu_397_p4);

assign img_V_val_2_V_write = img_V_val_0_V1_update;

assign j_fu_377_p2 = (j_i_i_i_reg_224 + 10'd1);

assign pix_val_0_V_fu_397_p4 = {{p_Val2_s_phi_fu_274_p4[23:16]}};

assign pix_val_1_V_8_fu_407_p1 = p_Val2_s_phi_fu_274_p4[7:0];

assign pix_val_2_V_fu_411_p4 = {{p_Val2_s_phi_fu_274_p4[15:8]}};

assign s_axis_video_TREADY = s_axis_video_V_dest_V_0_state[1'd1];

assign s_axis_video_V_data_V_0_ack_in = s_axis_video_V_data_V_0_state[1'd1];

assign s_axis_video_V_data_V_0_load_A = (s_axis_video_V_data_V_0_state_cmp_full & ~s_axis_video_V_data_V_0_sel_wr);

assign s_axis_video_V_data_V_0_load_B = (s_axis_video_V_data_V_0_sel_wr & s_axis_video_V_data_V_0_state_cmp_full);

assign s_axis_video_V_data_V_0_sel = s_axis_video_V_data_V_0_sel_rd;

assign s_axis_video_V_data_V_0_state_cmp_full = ((s_axis_video_V_data_V_0_state != 2'd1) ? 1'b1 : 1'b0);

assign s_axis_video_V_data_V_0_vld_in = s_axis_video_TVALID;

assign s_axis_video_V_data_V_0_vld_out = s_axis_video_V_data_V_0_state[1'd0];

assign s_axis_video_V_dest_V_0_vld_in = s_axis_video_TVALID;

assign s_axis_video_V_last_V_0_ack_in = s_axis_video_V_last_V_0_state[1'd1];

assign s_axis_video_V_last_V_0_load_A = (s_axis_video_V_last_V_0_state_cmp_full & ~s_axis_video_V_last_V_0_sel_wr);

assign s_axis_video_V_last_V_0_load_B = (s_axis_video_V_last_V_0_sel_wr & s_axis_video_V_last_V_0_state_cmp_full);

assign s_axis_video_V_last_V_0_sel = s_axis_video_V_last_V_0_sel_rd;

assign s_axis_video_V_last_V_0_state_cmp_full = ((s_axis_video_V_last_V_0_state != 2'd1) ? 1'b1 : 1'b0);

assign s_axis_video_V_last_V_0_vld_in = s_axis_video_TVALID;

assign s_axis_video_V_last_V_0_vld_out = s_axis_video_V_last_V_0_state[1'd0];

assign s_axis_video_V_user_V_0_ack_in = s_axis_video_V_user_V_0_state[1'd1];

assign s_axis_video_V_user_V_0_load_A = (s_axis_video_V_user_V_0_state_cmp_full & ~s_axis_video_V_user_V_0_sel_wr);

assign s_axis_video_V_user_V_0_load_B = (s_axis_video_V_user_V_0_sel_wr & s_axis_video_V_user_V_0_state_cmp_full);

assign s_axis_video_V_user_V_0_sel = s_axis_video_V_user_V_0_sel_rd;

assign s_axis_video_V_user_V_0_state_cmp_full = ((s_axis_video_V_user_V_0_state != 2'd1) ? 1'b1 : 1'b0);

assign s_axis_video_V_user_V_0_vld_in = s_axis_video_TVALID;

assign s_axis_video_V_user_V_0_vld_out = s_axis_video_V_user_V_0_state[1'd0];

assign sel_tmp2_i_fu_347_p2 = ((tmp_2_loc_channel == 2'd0) ? 1'b1 : 1'b0);

assign tmp_user_V_fu_343_p1 = s_axis_video_V_user_V_0_data_out;

always @ (posedge ap_clk) begin
    Height_cast_i_i_i_reg_450[9] <= 1'b0;
end

endmodule //design_1_v_frmbuf_wr_0_0_AXIvideo2MultiPixStr
