-- ==============================================================
-- RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2017.2
-- Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved.
-- 
-- ===========================================================

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;

entity design_1_v_frmbuf_wr_0_0_MultiPixStream2Bytes is
port (
    ap_clk : IN STD_LOGIC;
    ap_rst : IN STD_LOGIC;
    ap_start : IN STD_LOGIC;
    ap_done : OUT STD_LOGIC;
    ap_continue : IN STD_LOGIC;
    ap_idle : OUT STD_LOGIC;
    ap_ready : OUT STD_LOGIC;
    StrmMPix_V_val_0_V_dout : IN STD_LOGIC_VECTOR (7 downto 0);
    StrmMPix_V_val_0_V_empty_n : IN STD_LOGIC;
    StrmMPix_V_val_0_V_read : OUT STD_LOGIC;
    StrmMPix_V_val_1_V_dout : IN STD_LOGIC_VECTOR (7 downto 0);
    StrmMPix_V_val_1_V_empty_n : IN STD_LOGIC;
    StrmMPix_V_val_1_V_read : OUT STD_LOGIC;
    StrmMPix_V_val_2_V_dout : IN STD_LOGIC_VECTOR (7 downto 0);
    StrmMPix_V_val_2_V_empty_n : IN STD_LOGIC;
    StrmMPix_V_val_2_V_read : OUT STD_LOGIC;
    bytes_plane0_V_V_din : OUT STD_LOGIC_VECTOR (63 downto 0);
    bytes_plane0_V_V_full_n : IN STD_LOGIC;
    bytes_plane0_V_V_write : OUT STD_LOGIC;
    HwReg_height_cast8_loc_dout : IN STD_LOGIC_VECTOR (8 downto 0);
    HwReg_height_cast8_loc_empty_n : IN STD_LOGIC;
    HwReg_height_cast8_loc_read : OUT STD_LOGIC;
    HwReg_width_cast9_loc_dout : IN STD_LOGIC_VECTOR (9 downto 0);
    HwReg_width_cast9_loc_empty_n : IN STD_LOGIC;
    HwReg_width_cast9_loc_read : OUT STD_LOGIC;
    tmp_3_loc_dout : IN STD_LOGIC_VECTOR (11 downto 0);
    tmp_3_loc_empty_n : IN STD_LOGIC;
    tmp_3_loc_read : OUT STD_LOGIC;
    HwReg_video_format : IN STD_LOGIC_VECTOR (15 downto 0);
    HwReg_height_cast8_loc_out_din : OUT STD_LOGIC_VECTOR (8 downto 0);
    HwReg_height_cast8_loc_out_full_n : IN STD_LOGIC;
    HwReg_height_cast8_loc_out_write : OUT STD_LOGIC;
    tmp_3_loc_out_din : OUT STD_LOGIC_VECTOR (11 downto 0);
    tmp_3_loc_out_full_n : IN STD_LOGIC;
    tmp_3_loc_out_write : OUT STD_LOGIC );
end;


architecture behav of design_1_v_frmbuf_wr_0_0_MultiPixStream2Bytes is 
    constant ap_const_logic_1 : STD_LOGIC := '1';
    constant ap_const_logic_0 : STD_LOGIC := '0';
    constant ap_ST_fsm_state1 : STD_LOGIC_VECTOR (11 downto 0) := "000000000001";
    constant ap_ST_fsm_state2 : STD_LOGIC_VECTOR (11 downto 0) := "000000000010";
    constant ap_ST_fsm_state3 : STD_LOGIC_VECTOR (11 downto 0) := "000000000100";
    constant ap_ST_fsm_pp0_stage0 : STD_LOGIC_VECTOR (11 downto 0) := "000000001000";
    constant ap_ST_fsm_pp0_stage1 : STD_LOGIC_VECTOR (11 downto 0) := "000000010000";
    constant ap_ST_fsm_pp0_stage2 : STD_LOGIC_VECTOR (11 downto 0) := "000000100000";
    constant ap_ST_fsm_pp0_stage3 : STD_LOGIC_VECTOR (11 downto 0) := "000001000000";
    constant ap_ST_fsm_pp0_stage4 : STD_LOGIC_VECTOR (11 downto 0) := "000010000000";
    constant ap_ST_fsm_pp0_stage5 : STD_LOGIC_VECTOR (11 downto 0) := "000100000000";
    constant ap_ST_fsm_pp0_stage6 : STD_LOGIC_VECTOR (11 downto 0) := "001000000000";
    constant ap_ST_fsm_pp0_stage7 : STD_LOGIC_VECTOR (11 downto 0) := "010000000000";
    constant ap_ST_fsm_state13 : STD_LOGIC_VECTOR (11 downto 0) := "100000000000";
    constant ap_const_lv32_0 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000000";
    constant ap_const_boolean_1 : BOOLEAN := true;
    constant ap_const_lv32_4 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000100";
    constant ap_const_boolean_0 : BOOLEAN := false;
    constant ap_const_lv1_1 : STD_LOGIC_VECTOR (0 downto 0) := "1";
    constant ap_const_lv32_5 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000101";
    constant ap_const_lv32_6 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000110";
    constant ap_const_lv32_7 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000111";
    constant ap_const_lv32_8 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001000";
    constant ap_const_lv32_9 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001001";
    constant ap_const_lv32_A : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001010";
    constant ap_const_lv32_3 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000011";
    constant ap_const_lv1_0 : STD_LOGIC_VECTOR (0 downto 0) := "0";
    constant ap_const_lv32_1 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000001";
    constant ap_const_lv32_2 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000010";
    constant ap_const_lv16_0 : STD_LOGIC_VECTOR (15 downto 0) := "0000000000000000";
    constant ap_const_lv32_B : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001011";
    constant ap_const_lv8_0 : STD_LOGIC_VECTOR (7 downto 0) := "00000000";
    constant ap_const_lv8_F6 : STD_LOGIC_VECTOR (7 downto 0) := "11110110";
    constant ap_const_lv7_0 : STD_LOGIC_VECTOR (6 downto 0) := "0000000";
    constant ap_const_lv8_F1 : STD_LOGIC_VECTOR (7 downto 0) := "11110001";
    constant ap_const_lv8_C : STD_LOGIC_VECTOR (7 downto 0) := "00001100";
    constant ap_const_lv8_EE : STD_LOGIC_VECTOR (7 downto 0) := "11101110";
    constant ap_const_lv8_EA : STD_LOGIC_VECTOR (7 downto 0) := "11101010";
    constant ap_const_lv8_EC : STD_LOGIC_VECTOR (7 downto 0) := "11101100";
    constant ap_const_lv13_7 : STD_LOGIC_VECTOR (12 downto 0) := "0000000000111";
    constant ap_const_lv32_C : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001100";
    constant ap_const_lv10_2 : STD_LOGIC_VECTOR (9 downto 0) := "0000000010";
    constant ap_const_lv22_556 : STD_LOGIC_VECTOR (21 downto 0) := "0000000000010101010110";
    constant ap_const_lv32_14 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000010100";
    constant ap_const_lv3_0 : STD_LOGIC_VECTOR (2 downto 0) := "000";
    constant ap_const_lv4_8 : STD_LOGIC_VECTOR (3 downto 0) := "1000";
    constant ap_const_lv5_0 : STD_LOGIC_VECTOR (4 downto 0) := "00000";
    constant ap_const_lv9_3F : STD_LOGIC_VECTOR (8 downto 0) := "000111111";
    constant ap_const_lv3_3 : STD_LOGIC_VECTOR (2 downto 0) := "011";
    constant ap_const_lv9_1FF : STD_LOGIC_VECTOR (8 downto 0) := "111111111";
    constant ap_const_lv4_0 : STD_LOGIC_VECTOR (3 downto 0) := "0000";
    constant ap_const_lv4_2 : STD_LOGIC_VECTOR (3 downto 0) := "0010";
    constant ap_const_lv2_0 : STD_LOGIC_VECTOR (1 downto 0) := "00";
    constant ap_const_lv4_4 : STD_LOGIC_VECTOR (3 downto 0) := "0100";
    constant ap_const_lv4_5 : STD_LOGIC_VECTOR (3 downto 0) := "0101";
    constant ap_const_lv4_6 : STD_LOGIC_VECTOR (3 downto 0) := "0110";
    constant ap_const_lv3_2 : STD_LOGIC_VECTOR (2 downto 0) := "010";
    constant ap_const_lv16_1 : STD_LOGIC_VECTOR (15 downto 0) := "0000000000000001";
    constant ap_const_lv8_1 : STD_LOGIC_VECTOR (7 downto 0) := "00000001";

    signal ap_done_reg : STD_LOGIC := '0';
    signal ap_CS_fsm : STD_LOGIC_VECTOR (11 downto 0) := "000000000001";
    attribute fsm_encoding : string;
    attribute fsm_encoding of ap_CS_fsm : signal is "none";
    signal ap_CS_fsm_state1 : STD_LOGIC;
    attribute fsm_encoding of ap_CS_fsm_state1 : signal is "none";
    signal StrmMPix_V_val_0_V_blk_n : STD_LOGIC;
    signal ap_CS_fsm_pp0_stage1 : STD_LOGIC;
    attribute fsm_encoding of ap_CS_fsm_pp0_stage1 : signal is "none";
    signal ap_enable_reg_pp0_iter0 : STD_LOGIC := '0';
    signal ap_block_pp0_stage1_flag00000000 : BOOLEAN;
    signal tmp_13_i_i_reg_1248 : STD_LOGIC_VECTOR (0 downto 0);
    signal or_cond_i_i_reg_1268 : STD_LOGIC_VECTOR (0 downto 0);
    signal ap_CS_fsm_pp0_stage2 : STD_LOGIC;
    attribute fsm_encoding of ap_CS_fsm_pp0_stage2 : signal is "none";
    signal ap_block_pp0_stage2_flag00000000 : BOOLEAN;
    signal or_cond_1_i_i_reg_1314 : STD_LOGIC_VECTOR (0 downto 0);
    signal ap_CS_fsm_pp0_stage3 : STD_LOGIC;
    attribute fsm_encoding of ap_CS_fsm_pp0_stage3 : signal is "none";
    signal ap_block_pp0_stage3_flag00000000 : BOOLEAN;
    signal or_cond_2_i_i_reg_1333 : STD_LOGIC_VECTOR (0 downto 0);
    signal ap_CS_fsm_pp0_stage4 : STD_LOGIC;
    attribute fsm_encoding of ap_CS_fsm_pp0_stage4 : signal is "none";
    signal ap_block_pp0_stage4_flag00000000 : BOOLEAN;
    signal or_cond_3_i_i_reg_1352 : STD_LOGIC_VECTOR (0 downto 0);
    signal ap_CS_fsm_pp0_stage5 : STD_LOGIC;
    attribute fsm_encoding of ap_CS_fsm_pp0_stage5 : signal is "none";
    signal ap_block_pp0_stage5_flag00000000 : BOOLEAN;
    signal or_cond_4_i_i_reg_1371 : STD_LOGIC_VECTOR (0 downto 0);
    signal ap_CS_fsm_pp0_stage6 : STD_LOGIC;
    attribute fsm_encoding of ap_CS_fsm_pp0_stage6 : signal is "none";
    signal ap_block_pp0_stage6_flag00000000 : BOOLEAN;
    signal or_cond_5_i_i_reg_1390 : STD_LOGIC_VECTOR (0 downto 0);
    signal ap_CS_fsm_pp0_stage7 : STD_LOGIC;
    attribute fsm_encoding of ap_CS_fsm_pp0_stage7 : signal is "none";
    signal ap_block_pp0_stage7_flag00000000 : BOOLEAN;
    signal or_cond_6_i_i_reg_1394 : STD_LOGIC_VECTOR (0 downto 0);
    signal ap_CS_fsm_pp0_stage0 : STD_LOGIC;
    attribute fsm_encoding of ap_CS_fsm_pp0_stage0 : signal is "none";
    signal ap_enable_reg_pp0_iter1 : STD_LOGIC := '0';
    signal ap_block_pp0_stage0_flag00000000 : BOOLEAN;
    signal or_cond_7_i_i_reg_1398 : STD_LOGIC_VECTOR (0 downto 0);
    signal StrmMPix_V_val_1_V_blk_n : STD_LOGIC;
    signal StrmMPix_V_val_2_V_blk_n : STD_LOGIC;
    signal bytes_plane0_V_V_blk_n : STD_LOGIC;
    signal or_cond1_i_i_reg_1272 : STD_LOGIC_VECTOR (0 downto 0);
    signal or_cond1_1_i_i_reg_1276 : STD_LOGIC_VECTOR (0 downto 0);
    signal or_cond1_2_i_i_reg_1280 : STD_LOGIC_VECTOR (0 downto 0);
    signal HwReg_height_cast8_loc_blk_n : STD_LOGIC;
    signal HwReg_width_cast9_loc_blk_n : STD_LOGIC;
    signal tmp_3_loc_blk_n : STD_LOGIC;
    signal HwReg_height_cast8_loc_out_blk_n : STD_LOGIC;
    signal tmp_3_loc_out_blk_n : STD_LOGIC;
    signal x_i_i_reg_254 : STD_LOGIC_VECTOR (7 downto 0);
    signal pix_val_V_2_2_i_i_reg_265 : STD_LOGIC_VECTOR (7 downto 0);
    signal pix_val_V_1_2_i_i_reg_275 : STD_LOGIC_VECTOR (7 downto 0);
    signal pix_val_V_0_2_i_i_reg_285 : STD_LOGIC_VECTOR (7 downto 0);
    signal pix_val_V_2_3_i_i_reg_295 : STD_LOGIC_VECTOR (7 downto 0);
    signal pix_val_V_1_3_i_i_reg_306 : STD_LOGIC_VECTOR (7 downto 0);
    signal pix_val_V_0_3_i_i_reg_317 : STD_LOGIC_VECTOR (7 downto 0);
    signal pix_val_V_2_4_i_i_reg_328 : STD_LOGIC_VECTOR (7 downto 0);
    signal pix_val_V_2_5_i_i_reg_361 : STD_LOGIC_VECTOR (7 downto 0);
    signal pix_val_V_1_5_i_i_reg_372 : STD_LOGIC_VECTOR (7 downto 0);
    signal pix_val_V_0_5_i_i_reg_383 : STD_LOGIC_VECTOR (7 downto 0);
    signal pix_val_V_2_6_i_i_reg_394 : STD_LOGIC_VECTOR (7 downto 0);
    signal pix_val_V_1_6_i_i_reg_405 : STD_LOGIC_VECTOR (7 downto 0);
    signal pix_val_V_0_6_i_i_reg_416 : STD_LOGIC_VECTOR (7 downto 0);
    signal pix_val_V_2_7_i_i_reg_427 : STD_LOGIC_VECTOR (7 downto 0);
    signal pix_val_V_1_7_i_i_reg_438 : STD_LOGIC_VECTOR (7 downto 0);
    signal HwReg_height_cast8_l_reg_1103 : STD_LOGIC_VECTOR (8 downto 0);
    signal ap_block_state1 : BOOLEAN;
    signal icmp_fu_555_p2 : STD_LOGIC_VECTOR (0 downto 0);
    signal icmp1_fu_577_p2 : STD_LOGIC_VECTOR (0 downto 0);
    signal tmp_i_i_fu_583_p2 : STD_LOGIC_VECTOR (0 downto 0);
    signal icmp2_fu_605_p2 : STD_LOGIC_VECTOR (0 downto 0);
    signal icmp3_fu_627_p2 : STD_LOGIC_VECTOR (0 downto 0);
    signal icmp4_fu_649_p2 : STD_LOGIC_VECTOR (0 downto 0);
    signal tmp_6_i_i_fu_675_p2 : STD_LOGIC_VECTOR (9 downto 0);
    signal tmp_6_i_i_reg_1156 : STD_LOGIC_VECTOR (9 downto 0);
    signal remPix_fu_681_p1 : STD_LOGIC_VECTOR (2 downto 0);
    signal remPix_reg_1161 : STD_LOGIC_VECTOR (2 downto 0);
    signal loopWidth_cast_i_i_c_fu_699_p4 : STD_LOGIC_VECTOR (8 downto 0);
    signal loopWidth_cast_i_i_c_reg_1169 : STD_LOGIC_VECTOR (8 downto 0);
    signal ap_CS_fsm_state2 : STD_LOGIC;
    attribute fsm_encoding of ap_CS_fsm_state2 : signal is "none";
    signal tmp_7_i_i_fu_712_p2 : STD_LOGIC_VECTOR (0 downto 0);
    signal tmp_7_i_i_reg_1174 : STD_LOGIC_VECTOR (0 downto 0);
    signal tmp_11_cast_i_i_fu_777_p1 : STD_LOGIC_VECTOR (16 downto 0);
    signal tmp_11_cast_i_i_reg_1179 : STD_LOGIC_VECTOR (16 downto 0);
    signal tmp_12_i_i_fu_780_p2 : STD_LOGIC_VECTOR (8 downto 0);
    signal tmp_12_i_i_reg_1184 : STD_LOGIC_VECTOR (8 downto 0);
    signal tmp_24_i_i_fu_786_p2 : STD_LOGIC_VECTOR (0 downto 0);
    signal tmp_24_i_i_reg_1189 : STD_LOGIC_VECTOR (0 downto 0);
    signal icmp5_fu_802_p2 : STD_LOGIC_VECTOR (0 downto 0);
    signal icmp5_reg_1194 : STD_LOGIC_VECTOR (0 downto 0);
    signal tmp_24_2_i_i_fu_808_p2 : STD_LOGIC_VECTOR (0 downto 0);
    signal tmp_24_2_i_i_reg_1199 : STD_LOGIC_VECTOR (0 downto 0);
    signal icmp6_fu_824_p2 : STD_LOGIC_VECTOR (0 downto 0);
    signal icmp6_reg_1204 : STD_LOGIC_VECTOR (0 downto 0);
    signal tmp_24_4_i_i_fu_830_p2 : STD_LOGIC_VECTOR (0 downto 0);
    signal tmp_24_4_i_i_reg_1209 : STD_LOGIC_VECTOR (0 downto 0);
    signal tmp_24_5_i_i_fu_836_p2 : STD_LOGIC_VECTOR (0 downto 0);
    signal tmp_24_5_i_i_reg_1214 : STD_LOGIC_VECTOR (0 downto 0);
    signal tmp_24_6_i_i_fu_842_p2 : STD_LOGIC_VECTOR (0 downto 0);
    signal tmp_24_6_i_i_reg_1219 : STD_LOGIC_VECTOR (0 downto 0);
    signal tmp_25_i_i_fu_848_p2 : STD_LOGIC_VECTOR (0 downto 0);
    signal tmp_25_i_i_reg_1224 : STD_LOGIC_VECTOR (0 downto 0);
    signal icmp7_fu_864_p2 : STD_LOGIC_VECTOR (0 downto 0);
    signal icmp7_reg_1229 : STD_LOGIC_VECTOR (0 downto 0);
    signal tmp_25_2_i_i_fu_870_p2 : STD_LOGIC_VECTOR (0 downto 0);
    signal tmp_25_2_i_i_reg_1234 : STD_LOGIC_VECTOR (0 downto 0);
    signal exitcond1_i_i_fu_880_p2 : STD_LOGIC_VECTOR (0 downto 0);
    signal ap_CS_fsm_state3 : STD_LOGIC;
    attribute fsm_encoding of ap_CS_fsm_state3 : signal is "none";
    signal y_fu_885_p2 : STD_LOGIC_VECTOR (15 downto 0);
    signal y_reg_1243 : STD_LOGIC_VECTOR (15 downto 0);
    signal tmp_13_i_i_fu_895_p2 : STD_LOGIC_VECTOR (0 downto 0);
    signal ap_block_state4_pp0_stage0_iter0 : BOOLEAN;
    signal StrmMPix_V_val_0_V0_status : STD_LOGIC;
    signal ap_predicate_op205_read_state12 : BOOLEAN;
    signal ap_block_state12_pp0_stage0_iter1 : BOOLEAN;
    signal ap_block_pp0_stage0_flag00011001 : BOOLEAN;
    signal x_fu_900_p2 : STD_LOGIC_VECTOR (7 downto 0);
    signal x_reg_1252 : STD_LOGIC_VECTOR (7 downto 0);
    signal tmp_14_i_i_fu_906_p2 : STD_LOGIC_VECTOR (0 downto 0);
    signal tmp_14_i_i_reg_1257 : STD_LOGIC_VECTOR (0 downto 0);
    signal or_cond_i_i_fu_911_p2 : STD_LOGIC_VECTOR (0 downto 0);
    signal or_cond1_i_i_fu_916_p2 : STD_LOGIC_VECTOR (0 downto 0);
    signal or_cond1_1_i_i_fu_921_p2 : STD_LOGIC_VECTOR (0 downto 0);
    signal or_cond1_2_i_i_fu_926_p2 : STD_LOGIC_VECTOR (0 downto 0);
    signal ap_predicate_op129_read_state5 : BOOLEAN;
    signal ap_block_state5_pp0_stage1_iter0 : BOOLEAN;
    signal ap_block_pp0_stage1_flag00011001 : BOOLEAN;
    signal or_cond_1_i_i_fu_940_p2 : STD_LOGIC_VECTOR (0 downto 0);
    signal ap_predicate_op139_read_state6 : BOOLEAN;
    signal ap_block_state6_pp0_stage2_iter0 : BOOLEAN;
    signal ap_block_pp0_stage2_flag00011001 : BOOLEAN;
    signal or_cond_2_i_i_fu_944_p2 : STD_LOGIC_VECTOR (0 downto 0);
    signal ap_predicate_op149_read_state7 : BOOLEAN;
    signal ap_block_state7_pp0_stage3_iter0 : BOOLEAN;
    signal ap_block_pp0_stage3_flag00011001 : BOOLEAN;
    signal or_cond_3_i_i_fu_948_p2 : STD_LOGIC_VECTOR (0 downto 0);
    signal ap_predicate_op159_read_state8 : BOOLEAN;
    signal ap_predicate_op166_write_state8 : BOOLEAN;
    signal ap_block_state8_pp0_stage4_iter0 : BOOLEAN;
    signal ap_block_pp0_stage4_flag00011001 : BOOLEAN;
    signal or_cond_4_i_i_fu_952_p2 : STD_LOGIC_VECTOR (0 downto 0);
    signal ap_predicate_op172_read_state9 : BOOLEAN;
    signal ap_block_state9_pp0_stage5_iter0 : BOOLEAN;
    signal ap_block_pp0_stage5_flag00011001 : BOOLEAN;
    signal or_cond_5_i_i_fu_977_p2 : STD_LOGIC_VECTOR (0 downto 0);
    signal or_cond_6_i_i_fu_981_p2 : STD_LOGIC_VECTOR (0 downto 0);
    signal or_cond_7_i_i_fu_985_p2 : STD_LOGIC_VECTOR (0 downto 0);
    signal ap_predicate_op184_read_state10 : BOOLEAN;
    signal ap_block_state10_pp0_stage6_iter0 : BOOLEAN;
    signal ap_block_pp0_stage6_flag00011001 : BOOLEAN;
    signal ap_predicate_op193_read_state11 : BOOLEAN;
    signal ap_predicate_op199_write_state11 : BOOLEAN;
    signal ap_block_state11_pp0_stage7_iter0 : BOOLEAN;
    signal ap_block_pp0_stage7_flag00011001 : BOOLEAN;
    signal ap_block_pp0_stage1_flag00011011 : BOOLEAN;
    signal ap_condition_pp0_exit_iter0_state5 : STD_LOGIC;
    signal ap_block_pp0_stage7_flag00011011 : BOOLEAN;
    signal y_i_i_reg_243 : STD_LOGIC_VECTOR (15 downto 0);
    signal ap_CS_fsm_state13 : STD_LOGIC;
    attribute fsm_encoding of ap_CS_fsm_state13 : signal is "none";
    signal x_i_i_phi_fu_258_p4 : STD_LOGIC_VECTOR (7 downto 0);
    signal ap_phi_precharge_reg_pp0_iter0_pix_val_V_2_2_i_i_reg_265 : STD_LOGIC_VECTOR (7 downto 0);
    signal ap_phi_precharge_reg_pp0_iter0_pix_val_V_1_2_i_i_reg_275 : STD_LOGIC_VECTOR (7 downto 0);
    signal ap_phi_precharge_reg_pp0_iter0_pix_val_V_0_2_i_i_reg_285 : STD_LOGIC_VECTOR (7 downto 0);
    signal ap_phi_precharge_reg_pp0_iter0_pix_val_V_2_3_i_i_reg_295 : STD_LOGIC_VECTOR (7 downto 0);
    signal ap_phi_precharge_reg_pp0_iter0_pix_val_V_1_3_i_i_reg_306 : STD_LOGIC_VECTOR (7 downto 0);
    signal ap_phi_precharge_reg_pp0_iter0_pix_val_V_0_3_i_i_reg_317 : STD_LOGIC_VECTOR (7 downto 0);
    signal ap_phi_precharge_reg_pp0_iter0_pix_val_V_2_4_i_i_reg_328 : STD_LOGIC_VECTOR (7 downto 0);
    signal ap_phi_precharge_reg_pp0_iter0_pix_val_V_1_4_i_i_reg_339 : STD_LOGIC_VECTOR (7 downto 0);
    signal ap_phi_precharge_reg_pp0_iter0_pix_val_V_0_4_i_i_reg_350 : STD_LOGIC_VECTOR (7 downto 0);
    signal ap_phi_precharge_reg_pp0_iter0_pix_val_V_2_5_i_i_reg_361 : STD_LOGIC_VECTOR (7 downto 0);
    signal ap_phi_precharge_reg_pp0_iter0_pix_val_V_1_5_i_i_reg_372 : STD_LOGIC_VECTOR (7 downto 0);
    signal ap_phi_precharge_reg_pp0_iter0_pix_val_V_0_5_i_i_reg_383 : STD_LOGIC_VECTOR (7 downto 0);
    signal ap_phi_precharge_reg_pp0_iter0_pix_val_V_2_6_i_i_reg_394 : STD_LOGIC_VECTOR (7 downto 0);
    signal ap_phi_precharge_reg_pp0_iter0_pix_val_V_1_6_i_i_reg_405 : STD_LOGIC_VECTOR (7 downto 0);
    signal ap_phi_precharge_reg_pp0_iter0_pix_val_V_0_6_i_i_reg_416 : STD_LOGIC_VECTOR (7 downto 0);
    signal ap_phi_precharge_reg_pp0_iter0_pix_val_V_2_7_i_i_reg_427 : STD_LOGIC_VECTOR (7 downto 0);
    signal ap_phi_precharge_reg_pp0_iter0_pix_val_V_1_7_i_i_reg_438 : STD_LOGIC_VECTOR (7 downto 0);
    signal ap_phi_precharge_reg_pp0_iter0_pix_val_V_0_7_i_i_reg_449 : STD_LOGIC_VECTOR (7 downto 0);
    signal ap_phi_precharge_reg_pp0_iter0_pix_val_V_2_8_i_i_reg_460 : STD_LOGIC_VECTOR (7 downto 0);
    signal ap_phi_precharge_reg_pp0_iter1_pix_val_V_2_8_i_i_reg_460 : STD_LOGIC_VECTOR (7 downto 0);
    signal ap_phi_precharge_reg_pp0_iter0_pix_val_V_1_8_i_i_reg_470 : STD_LOGIC_VECTOR (7 downto 0);
    signal ap_phi_precharge_reg_pp0_iter1_pix_val_V_1_8_i_i_reg_470 : STD_LOGIC_VECTOR (7 downto 0);
    signal ap_phi_precharge_reg_pp0_iter0_pix_val_V_0_8_i_i_reg_480 : STD_LOGIC_VECTOR (7 downto 0);
    signal ap_phi_precharge_reg_pp0_iter1_pix_val_V_0_8_i_i_reg_480 : STD_LOGIC_VECTOR (7 downto 0);
    signal ap_phi_precharge_reg_pp0_iter0_pix_val_V_2_9_i_i_reg_490 : STD_LOGIC_VECTOR (7 downto 0);
    signal ap_phi_precharge_reg_pp0_iter1_pix_val_V_2_9_i_i_reg_490 : STD_LOGIC_VECTOR (7 downto 0);
    signal pix_val_V_2_9_i_i_phi_fu_493_p4 : STD_LOGIC_VECTOR (7 downto 0);
    signal ap_phi_precharge_reg_pp0_iter0_pix_val_V_1_9_i_i_reg_500 : STD_LOGIC_VECTOR (7 downto 0);
    signal ap_phi_precharge_reg_pp0_iter1_pix_val_V_1_9_i_i_reg_500 : STD_LOGIC_VECTOR (7 downto 0);
    signal pix_val_V_1_9_i_i_phi_fu_503_p4 : STD_LOGIC_VECTOR (7 downto 0);
    signal ap_phi_precharge_reg_pp0_iter0_pix_val_V_0_9_i_i_reg_510 : STD_LOGIC_VECTOR (7 downto 0);
    signal ap_phi_precharge_reg_pp0_iter1_pix_val_V_0_9_i_i_reg_510 : STD_LOGIC_VECTOR (7 downto 0);
    signal pix_val_V_0_9_i_i_phi_fu_513_p4 : STD_LOGIC_VECTOR (7 downto 0);
    signal StrmMPix_V_val_0_V0_update : STD_LOGIC;
    signal tmp_V_fu_956_p9 : STD_LOGIC_VECTOR (63 downto 0);
    signal ap_block_pp0_stage4_flag00001001 : BOOLEAN;
    signal tmp_V_1_fu_989_p9 : STD_LOGIC_VECTOR (63 downto 0);
    signal ap_block_pp0_stage7_flag00001001 : BOOLEAN;
    signal tmp_V_2_fu_1062_p9 : STD_LOGIC_VECTOR (63 downto 0);
    signal ap_block_pp0_stage0_flag00001001 : BOOLEAN;
    signal tmp_val_0_V_fu_174 : STD_LOGIC_VECTOR (7 downto 0);
    signal tmp_val_1_V_fu_178 : STD_LOGIC_VECTOR (7 downto 0);
    signal tmp_val_2_V_fu_182 : STD_LOGIC_VECTOR (7 downto 0);
    signal tmp_fu_535_p1 : STD_LOGIC_VECTOR (7 downto 0);
    signal VideoFormat_off_i_i_fu_539_p2 : STD_LOGIC_VECTOR (7 downto 0);
    signal tmp_2_fu_545_p4 : STD_LOGIC_VECTOR (6 downto 0);
    signal VideoFormat_off1_i_i_fu_561_p2 : STD_LOGIC_VECTOR (7 downto 0);
    signal tmp_3_fu_567_p4 : STD_LOGIC_VECTOR (6 downto 0);
    signal VideoFormat_off2_i_i_fu_589_p2 : STD_LOGIC_VECTOR (7 downto 0);
    signal tmp_4_fu_595_p4 : STD_LOGIC_VECTOR (6 downto 0);
    signal VideoFormat_off3_i_i_fu_611_p2 : STD_LOGIC_VECTOR (7 downto 0);
    signal tmp_5_fu_617_p4 : STD_LOGIC_VECTOR (6 downto 0);
    signal VideoFormat_off4_i_i_fu_633_p2 : STD_LOGIC_VECTOR (7 downto 0);
    signal tmp_6_fu_639_p4 : STD_LOGIC_VECTOR (6 downto 0);
    signal tmp_cast_i_i_cast_fu_655_p1 : STD_LOGIC_VECTOR (12 downto 0);
    signal tmp_5_i_i_fu_659_p2 : STD_LOGIC_VECTOR (12 downto 0);
    signal loopWidth1_cast_i_i_s_fu_665_p4 : STD_LOGIC_VECTOR (9 downto 0);
    signal mul_fu_693_p1 : STD_LOGIC_VECTOR (9 downto 0);
    signal mul_fu_693_p2 : STD_LOGIC_VECTOR (21 downto 0);
    signal remPix_cast_i_i_fu_709_p1 : STD_LOGIC_VECTOR (3 downto 0);
    signal p_shl_i_i_fu_725_p3 : STD_LOGIC_VECTOR (7 downto 0);
    signal p_shl1_i_i_fu_736_p3 : STD_LOGIC_VECTOR (5 downto 0);
    signal p_shl_cast_i_i_fu_732_p1 : STD_LOGIC_VECTOR (8 downto 0);
    signal p_shl1_cast_i_i_fu_743_p1 : STD_LOGIC_VECTOR (8 downto 0);
    signal tmp_8_i_i_fu_747_p2 : STD_LOGIC_VECTOR (8 downto 0);
    signal tmp_9_i_i_fu_753_p2 : STD_LOGIC_VECTOR (8 downto 0);
    signal tmp_10_cast_i_i_fu_759_p4 : STD_LOGIC_VECTOR (2 downto 0);
    signal remPix_2_fu_717_p3 : STD_LOGIC_VECTOR (3 downto 0);
    signal tmp_8_fu_792_p4 : STD_LOGIC_VECTOR (2 downto 0);
    signal tmp_9_fu_814_p4 : STD_LOGIC_VECTOR (1 downto 0);
    signal remainTrx_fu_769_p3 : STD_LOGIC_VECTOR (2 downto 0);
    signal tmp_10_fu_854_p4 : STD_LOGIC_VECTOR (1 downto 0);
    signal y_cast_i_i_fu_876_p1 : STD_LOGIC_VECTOR (16 downto 0);
    signal x_cast_i_i_cast_fu_891_p1 : STD_LOGIC_VECTOR (8 downto 0);
    signal ap_NS_fsm : STD_LOGIC_VECTOR (11 downto 0);
    signal ap_block_pp0_stage0_flag00011011 : BOOLEAN;
    signal ap_block_pp0_stage2_flag00011011 : BOOLEAN;
    signal ap_block_pp0_stage3_flag00011011 : BOOLEAN;
    signal ap_block_pp0_stage4_flag00011011 : BOOLEAN;
    signal ap_block_pp0_stage5_flag00011011 : BOOLEAN;
    signal ap_block_pp0_stage6_flag00011011 : BOOLEAN;
    signal ap_idle_pp0 : STD_LOGIC;
    signal ap_enable_pp0 : STD_LOGIC;
    signal mul_fu_693_p10 : STD_LOGIC_VECTOR (21 downto 0);
    signal ap_condition_1138 : BOOLEAN;
    signal ap_condition_1143 : BOOLEAN;
    signal ap_condition_1147 : BOOLEAN;
    signal ap_condition_1151 : BOOLEAN;
    signal ap_condition_1155 : BOOLEAN;
    signal ap_condition_1159 : BOOLEAN;
    signal ap_condition_515 : BOOLEAN;
    signal ap_condition_549 : BOOLEAN;


begin




    ap_CS_fsm_assign_proc : process(ap_clk)
    begin
        if (ap_clk'event and ap_clk =  '1') then
            if (ap_rst = '1') then
                ap_CS_fsm <= ap_ST_fsm_state1;
            else
                ap_CS_fsm <= ap_NS_fsm;
            end if;
        end if;
    end process;


    ap_done_reg_assign_proc : process(ap_clk)
    begin
        if (ap_clk'event and ap_clk =  '1') then
            if (ap_rst = '1') then
                ap_done_reg <= ap_const_logic_0;
            else
                if ((ap_const_logic_1 = ap_continue)) then 
                    ap_done_reg <= ap_const_logic_0;
                elsif (((ap_const_logic_1 = ap_CS_fsm_state3) and ((ap_const_lv1_1 = icmp_fu_555_p2) or (ap_const_lv1_1 = icmp1_fu_577_p2) or (ap_const_lv1_1 = tmp_i_i_fu_583_p2) or (ap_const_lv1_1 = icmp2_fu_605_p2) or (ap_const_lv1_1 = icmp3_fu_627_p2) or (ap_const_lv1_0 = icmp4_fu_649_p2) or (ap_const_lv1_1 = exitcond1_i_i_fu_880_p2)))) then 
                    ap_done_reg <= ap_const_logic_1;
                end if; 
            end if;
        end if;
    end process;


    ap_enable_reg_pp0_iter0_assign_proc : process(ap_clk)
    begin
        if (ap_clk'event and ap_clk =  '1') then
            if (ap_rst = '1') then
                ap_enable_reg_pp0_iter0 <= ap_const_logic_0;
            else
                if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_block_pp0_stage1_flag00011011 = ap_const_boolean_0) and (ap_const_logic_1 = ap_condition_pp0_exit_iter0_state5))) then 
                    ap_enable_reg_pp0_iter0 <= ap_const_logic_0;
                elsif (((icmp_fu_555_p2 = ap_const_lv1_0) and (icmp1_fu_577_p2 = ap_const_lv1_0) and (ap_const_lv1_0 = tmp_i_i_fu_583_p2) and (ap_const_lv1_0 = icmp2_fu_605_p2) and (ap_const_lv1_0 = icmp3_fu_627_p2) and (ap_const_lv1_1 = icmp4_fu_649_p2) and (ap_const_logic_1 = ap_CS_fsm_state3) and (ap_const_lv1_0 = exitcond1_i_i_fu_880_p2))) then 
                    ap_enable_reg_pp0_iter0 <= ap_const_logic_1;
                end if; 
            end if;
        end if;
    end process;


    ap_enable_reg_pp0_iter1_assign_proc : process(ap_clk)
    begin
        if (ap_clk'event and ap_clk =  '1') then
            if (ap_rst = '1') then
                ap_enable_reg_pp0_iter1 <= ap_const_logic_0;
            else
                if (((ap_const_logic_1 = ap_condition_pp0_exit_iter0_state5) and (((ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_block_pp0_stage1_flag00011011 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_block_pp0_stage7_flag00011011 = ap_const_boolean_0))))) then 
                    ap_enable_reg_pp0_iter1 <= (ap_condition_pp0_exit_iter0_state5 xor ap_const_logic_1);
                elsif ((((ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_block_pp0_stage1_flag00011011 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_block_pp0_stage7_flag00011011 = ap_const_boolean_0)))) then 
                    ap_enable_reg_pp0_iter1 <= ap_enable_reg_pp0_iter0;
                elsif (((icmp_fu_555_p2 = ap_const_lv1_0) and (icmp1_fu_577_p2 = ap_const_lv1_0) and (ap_const_lv1_0 = tmp_i_i_fu_583_p2) and (ap_const_lv1_0 = icmp2_fu_605_p2) and (ap_const_lv1_0 = icmp3_fu_627_p2) and (ap_const_lv1_1 = icmp4_fu_649_p2) and (ap_const_logic_1 = ap_CS_fsm_state3) and (ap_const_lv1_0 = exitcond1_i_i_fu_880_p2))) then 
                    ap_enable_reg_pp0_iter1 <= ap_const_logic_0;
                end if; 
            end if;
        end if;
    end process;


    ap_phi_precharge_reg_pp0_iter0_pix_val_V_0_2_i_i_reg_285_assign_proc : process (ap_clk)
    begin
        if (ap_clk'event and ap_clk = '1') then
            if ((ap_condition_1138 = ap_const_boolean_1)) then
                if ((or_cond_i_i_reg_1268 = ap_const_lv1_0)) then 
                    ap_phi_precharge_reg_pp0_iter0_pix_val_V_0_2_i_i_reg_285 <= tmp_val_0_V_fu_174;
                elsif ((ap_const_lv1_1 = or_cond_i_i_reg_1268)) then 
                    ap_phi_precharge_reg_pp0_iter0_pix_val_V_0_2_i_i_reg_285 <= StrmMPix_V_val_0_V_dout;
                end if;
            end if; 
        end if;
    end process;

    ap_phi_precharge_reg_pp0_iter0_pix_val_V_0_3_i_i_reg_317_assign_proc : process (ap_clk)
    begin
        if (ap_clk'event and ap_clk = '1') then
            if ((ap_condition_1143 = ap_const_boolean_1)) then
                if ((or_cond_1_i_i_reg_1314 = ap_const_lv1_0)) then 
                    ap_phi_precharge_reg_pp0_iter0_pix_val_V_0_3_i_i_reg_317 <= ap_phi_precharge_reg_pp0_iter0_pix_val_V_0_2_i_i_reg_285;
                elsif ((ap_const_lv1_1 = or_cond_1_i_i_reg_1314)) then 
                    ap_phi_precharge_reg_pp0_iter0_pix_val_V_0_3_i_i_reg_317 <= StrmMPix_V_val_0_V_dout;
                end if;
            end if; 
        end if;
    end process;

    ap_phi_precharge_reg_pp0_iter0_pix_val_V_0_4_i_i_reg_350_assign_proc : process (ap_clk)
    begin
        if (ap_clk'event and ap_clk = '1') then
            if ((ap_condition_1147 = ap_const_boolean_1)) then
                if ((or_cond_2_i_i_reg_1333 = ap_const_lv1_0)) then 
                    ap_phi_precharge_reg_pp0_iter0_pix_val_V_0_4_i_i_reg_350 <= ap_phi_precharge_reg_pp0_iter0_pix_val_V_0_3_i_i_reg_317;
                elsif ((ap_const_lv1_1 = or_cond_2_i_i_reg_1333)) then 
                    ap_phi_precharge_reg_pp0_iter0_pix_val_V_0_4_i_i_reg_350 <= StrmMPix_V_val_0_V_dout;
                end if;
            end if; 
        end if;
    end process;

    ap_phi_precharge_reg_pp0_iter0_pix_val_V_0_5_i_i_reg_383_assign_proc : process (ap_clk)
    begin
        if (ap_clk'event and ap_clk = '1') then
            if ((ap_condition_1151 = ap_const_boolean_1)) then
                if ((or_cond_3_i_i_reg_1352 = ap_const_lv1_0)) then 
                    ap_phi_precharge_reg_pp0_iter0_pix_val_V_0_5_i_i_reg_383 <= ap_phi_precharge_reg_pp0_iter0_pix_val_V_0_4_i_i_reg_350;
                elsif ((ap_const_lv1_1 = or_cond_3_i_i_reg_1352)) then 
                    ap_phi_precharge_reg_pp0_iter0_pix_val_V_0_5_i_i_reg_383 <= StrmMPix_V_val_0_V_dout;
                end if;
            end if; 
        end if;
    end process;

    ap_phi_precharge_reg_pp0_iter0_pix_val_V_0_6_i_i_reg_416_assign_proc : process (ap_clk)
    begin
        if (ap_clk'event and ap_clk = '1') then
            if ((ap_condition_1155 = ap_const_boolean_1)) then
                if ((or_cond_4_i_i_reg_1371 = ap_const_lv1_0)) then 
                    ap_phi_precharge_reg_pp0_iter0_pix_val_V_0_6_i_i_reg_416 <= ap_phi_precharge_reg_pp0_iter0_pix_val_V_0_5_i_i_reg_383;
                elsif ((ap_const_lv1_1 = or_cond_4_i_i_reg_1371)) then 
                    ap_phi_precharge_reg_pp0_iter0_pix_val_V_0_6_i_i_reg_416 <= StrmMPix_V_val_0_V_dout;
                end if;
            end if; 
        end if;
    end process;

    ap_phi_precharge_reg_pp0_iter0_pix_val_V_0_7_i_i_reg_449_assign_proc : process (ap_clk)
    begin
        if (ap_clk'event and ap_clk = '1') then
            if ((ap_condition_1159 = ap_const_boolean_1)) then
                if ((or_cond_5_i_i_reg_1390 = ap_const_lv1_0)) then 
                    ap_phi_precharge_reg_pp0_iter0_pix_val_V_0_7_i_i_reg_449 <= ap_phi_precharge_reg_pp0_iter0_pix_val_V_0_6_i_i_reg_416;
                elsif ((ap_const_lv1_1 = or_cond_5_i_i_reg_1390)) then 
                    ap_phi_precharge_reg_pp0_iter0_pix_val_V_0_7_i_i_reg_449 <= StrmMPix_V_val_0_V_dout;
                end if;
            end if; 
        end if;
    end process;

    ap_phi_precharge_reg_pp0_iter0_pix_val_V_1_2_i_i_reg_275_assign_proc : process (ap_clk)
    begin
        if (ap_clk'event and ap_clk = '1') then
            if ((ap_condition_1138 = ap_const_boolean_1)) then
                if ((or_cond_i_i_reg_1268 = ap_const_lv1_0)) then 
                    ap_phi_precharge_reg_pp0_iter0_pix_val_V_1_2_i_i_reg_275 <= tmp_val_1_V_fu_178;
                elsif ((ap_const_lv1_1 = or_cond_i_i_reg_1268)) then 
                    ap_phi_precharge_reg_pp0_iter0_pix_val_V_1_2_i_i_reg_275 <= StrmMPix_V_val_1_V_dout;
                end if;
            end if; 
        end if;
    end process;

    ap_phi_precharge_reg_pp0_iter0_pix_val_V_1_3_i_i_reg_306_assign_proc : process (ap_clk)
    begin
        if (ap_clk'event and ap_clk = '1') then
            if ((ap_condition_1143 = ap_const_boolean_1)) then
                if ((or_cond_1_i_i_reg_1314 = ap_const_lv1_0)) then 
                    ap_phi_precharge_reg_pp0_iter0_pix_val_V_1_3_i_i_reg_306 <= ap_phi_precharge_reg_pp0_iter0_pix_val_V_1_2_i_i_reg_275;
                elsif ((ap_const_lv1_1 = or_cond_1_i_i_reg_1314)) then 
                    ap_phi_precharge_reg_pp0_iter0_pix_val_V_1_3_i_i_reg_306 <= StrmMPix_V_val_1_V_dout;
                end if;
            end if; 
        end if;
    end process;

    ap_phi_precharge_reg_pp0_iter0_pix_val_V_1_4_i_i_reg_339_assign_proc : process (ap_clk)
    begin
        if (ap_clk'event and ap_clk = '1') then
            if ((ap_condition_1147 = ap_const_boolean_1)) then
                if ((or_cond_2_i_i_reg_1333 = ap_const_lv1_0)) then 
                    ap_phi_precharge_reg_pp0_iter0_pix_val_V_1_4_i_i_reg_339 <= ap_phi_precharge_reg_pp0_iter0_pix_val_V_1_3_i_i_reg_306;
                elsif ((ap_const_lv1_1 = or_cond_2_i_i_reg_1333)) then 
                    ap_phi_precharge_reg_pp0_iter0_pix_val_V_1_4_i_i_reg_339 <= StrmMPix_V_val_1_V_dout;
                end if;
            end if; 
        end if;
    end process;

    ap_phi_precharge_reg_pp0_iter0_pix_val_V_1_5_i_i_reg_372_assign_proc : process (ap_clk)
    begin
        if (ap_clk'event and ap_clk = '1') then
            if ((ap_condition_1151 = ap_const_boolean_1)) then
                if ((or_cond_3_i_i_reg_1352 = ap_const_lv1_0)) then 
                    ap_phi_precharge_reg_pp0_iter0_pix_val_V_1_5_i_i_reg_372 <= ap_phi_precharge_reg_pp0_iter0_pix_val_V_1_4_i_i_reg_339;
                elsif ((ap_const_lv1_1 = or_cond_3_i_i_reg_1352)) then 
                    ap_phi_precharge_reg_pp0_iter0_pix_val_V_1_5_i_i_reg_372 <= StrmMPix_V_val_1_V_dout;
                end if;
            end if; 
        end if;
    end process;

    ap_phi_precharge_reg_pp0_iter0_pix_val_V_1_6_i_i_reg_405_assign_proc : process (ap_clk)
    begin
        if (ap_clk'event and ap_clk = '1') then
            if ((ap_condition_1155 = ap_const_boolean_1)) then
                if ((or_cond_4_i_i_reg_1371 = ap_const_lv1_0)) then 
                    ap_phi_precharge_reg_pp0_iter0_pix_val_V_1_6_i_i_reg_405 <= ap_phi_precharge_reg_pp0_iter0_pix_val_V_1_5_i_i_reg_372;
                elsif ((ap_const_lv1_1 = or_cond_4_i_i_reg_1371)) then 
                    ap_phi_precharge_reg_pp0_iter0_pix_val_V_1_6_i_i_reg_405 <= StrmMPix_V_val_1_V_dout;
                end if;
            end if; 
        end if;
    end process;

    ap_phi_precharge_reg_pp0_iter0_pix_val_V_1_7_i_i_reg_438_assign_proc : process (ap_clk)
    begin
        if (ap_clk'event and ap_clk = '1') then
            if ((ap_condition_1159 = ap_const_boolean_1)) then
                if ((or_cond_5_i_i_reg_1390 = ap_const_lv1_0)) then 
                    ap_phi_precharge_reg_pp0_iter0_pix_val_V_1_7_i_i_reg_438 <= ap_phi_precharge_reg_pp0_iter0_pix_val_V_1_6_i_i_reg_405;
                elsif ((ap_const_lv1_1 = or_cond_5_i_i_reg_1390)) then 
                    ap_phi_precharge_reg_pp0_iter0_pix_val_V_1_7_i_i_reg_438 <= StrmMPix_V_val_1_V_dout;
                end if;
            end if; 
        end if;
    end process;

    ap_phi_precharge_reg_pp0_iter0_pix_val_V_2_2_i_i_reg_265_assign_proc : process (ap_clk)
    begin
        if (ap_clk'event and ap_clk = '1') then
            if ((ap_condition_1138 = ap_const_boolean_1)) then
                if ((or_cond_i_i_reg_1268 = ap_const_lv1_0)) then 
                    ap_phi_precharge_reg_pp0_iter0_pix_val_V_2_2_i_i_reg_265 <= tmp_val_2_V_fu_182;
                elsif ((ap_const_lv1_1 = or_cond_i_i_reg_1268)) then 
                    ap_phi_precharge_reg_pp0_iter0_pix_val_V_2_2_i_i_reg_265 <= StrmMPix_V_val_2_V_dout;
                end if;
            end if; 
        end if;
    end process;

    ap_phi_precharge_reg_pp0_iter0_pix_val_V_2_3_i_i_reg_295_assign_proc : process (ap_clk)
    begin
        if (ap_clk'event and ap_clk = '1') then
            if ((ap_condition_1143 = ap_const_boolean_1)) then
                if ((or_cond_1_i_i_reg_1314 = ap_const_lv1_0)) then 
                    ap_phi_precharge_reg_pp0_iter0_pix_val_V_2_3_i_i_reg_295 <= ap_phi_precharge_reg_pp0_iter0_pix_val_V_2_2_i_i_reg_265;
                elsif ((ap_const_lv1_1 = or_cond_1_i_i_reg_1314)) then 
                    ap_phi_precharge_reg_pp0_iter0_pix_val_V_2_3_i_i_reg_295 <= StrmMPix_V_val_2_V_dout;
                end if;
            end if; 
        end if;
    end process;

    ap_phi_precharge_reg_pp0_iter0_pix_val_V_2_4_i_i_reg_328_assign_proc : process (ap_clk)
    begin
        if (ap_clk'event and ap_clk = '1') then
            if ((ap_condition_1147 = ap_const_boolean_1)) then
                if ((or_cond_2_i_i_reg_1333 = ap_const_lv1_0)) then 
                    ap_phi_precharge_reg_pp0_iter0_pix_val_V_2_4_i_i_reg_328 <= ap_phi_precharge_reg_pp0_iter0_pix_val_V_2_3_i_i_reg_295;
                elsif ((ap_const_lv1_1 = or_cond_2_i_i_reg_1333)) then 
                    ap_phi_precharge_reg_pp0_iter0_pix_val_V_2_4_i_i_reg_328 <= StrmMPix_V_val_2_V_dout;
                end if;
            end if; 
        end if;
    end process;

    ap_phi_precharge_reg_pp0_iter0_pix_val_V_2_5_i_i_reg_361_assign_proc : process (ap_clk)
    begin
        if (ap_clk'event and ap_clk = '1') then
            if ((ap_condition_1151 = ap_const_boolean_1)) then
                if ((or_cond_3_i_i_reg_1352 = ap_const_lv1_0)) then 
                    ap_phi_precharge_reg_pp0_iter0_pix_val_V_2_5_i_i_reg_361 <= ap_phi_precharge_reg_pp0_iter0_pix_val_V_2_4_i_i_reg_328;
                elsif ((ap_const_lv1_1 = or_cond_3_i_i_reg_1352)) then 
                    ap_phi_precharge_reg_pp0_iter0_pix_val_V_2_5_i_i_reg_361 <= StrmMPix_V_val_2_V_dout;
                end if;
            end if; 
        end if;
    end process;

    ap_phi_precharge_reg_pp0_iter0_pix_val_V_2_6_i_i_reg_394_assign_proc : process (ap_clk)
    begin
        if (ap_clk'event and ap_clk = '1') then
            if ((ap_condition_1155 = ap_const_boolean_1)) then
                if ((or_cond_4_i_i_reg_1371 = ap_const_lv1_0)) then 
                    ap_phi_precharge_reg_pp0_iter0_pix_val_V_2_6_i_i_reg_394 <= ap_phi_precharge_reg_pp0_iter0_pix_val_V_2_5_i_i_reg_361;
                elsif ((ap_const_lv1_1 = or_cond_4_i_i_reg_1371)) then 
                    ap_phi_precharge_reg_pp0_iter0_pix_val_V_2_6_i_i_reg_394 <= StrmMPix_V_val_2_V_dout;
                end if;
            end if; 
        end if;
    end process;

    ap_phi_precharge_reg_pp0_iter0_pix_val_V_2_7_i_i_reg_427_assign_proc : process (ap_clk)
    begin
        if (ap_clk'event and ap_clk = '1') then
            if ((ap_condition_1159 = ap_const_boolean_1)) then
                if ((or_cond_5_i_i_reg_1390 = ap_const_lv1_0)) then 
                    ap_phi_precharge_reg_pp0_iter0_pix_val_V_2_7_i_i_reg_427 <= ap_phi_precharge_reg_pp0_iter0_pix_val_V_2_6_i_i_reg_394;
                elsif ((ap_const_lv1_1 = or_cond_5_i_i_reg_1390)) then 
                    ap_phi_precharge_reg_pp0_iter0_pix_val_V_2_7_i_i_reg_427 <= StrmMPix_V_val_2_V_dout;
                end if;
            end if; 
        end if;
    end process;

    ap_phi_precharge_reg_pp0_iter1_pix_val_V_0_8_i_i_reg_480_assign_proc : process (ap_clk)
    begin
        if (ap_clk'event and ap_clk = '1') then
            if ((ap_condition_515 = ap_const_boolean_1)) then
                if (((tmp_13_i_i_reg_1248 = ap_const_lv1_1) and (or_cond_6_i_i_reg_1394 = ap_const_lv1_0))) then 
                    ap_phi_precharge_reg_pp0_iter1_pix_val_V_0_8_i_i_reg_480 <= ap_phi_precharge_reg_pp0_iter0_pix_val_V_0_7_i_i_reg_449;
                elsif (((tmp_13_i_i_reg_1248 = ap_const_lv1_1) and (ap_const_lv1_1 = or_cond_6_i_i_reg_1394))) then 
                    ap_phi_precharge_reg_pp0_iter1_pix_val_V_0_8_i_i_reg_480 <= StrmMPix_V_val_0_V_dout;
                elsif ((ap_const_boolean_1 = ap_const_boolean_1)) then 
                    ap_phi_precharge_reg_pp0_iter1_pix_val_V_0_8_i_i_reg_480 <= ap_phi_precharge_reg_pp0_iter0_pix_val_V_0_8_i_i_reg_480;
                end if;
            end if; 
        end if;
    end process;

    ap_phi_precharge_reg_pp0_iter1_pix_val_V_1_8_i_i_reg_470_assign_proc : process (ap_clk)
    begin
        if (ap_clk'event and ap_clk = '1') then
            if ((ap_condition_515 = ap_const_boolean_1)) then
                if (((tmp_13_i_i_reg_1248 = ap_const_lv1_1) and (or_cond_6_i_i_reg_1394 = ap_const_lv1_0))) then 
                    ap_phi_precharge_reg_pp0_iter1_pix_val_V_1_8_i_i_reg_470 <= ap_phi_precharge_reg_pp0_iter0_pix_val_V_1_7_i_i_reg_438;
                elsif (((tmp_13_i_i_reg_1248 = ap_const_lv1_1) and (ap_const_lv1_1 = or_cond_6_i_i_reg_1394))) then 
                    ap_phi_precharge_reg_pp0_iter1_pix_val_V_1_8_i_i_reg_470 <= StrmMPix_V_val_1_V_dout;
                elsif ((ap_const_boolean_1 = ap_const_boolean_1)) then 
                    ap_phi_precharge_reg_pp0_iter1_pix_val_V_1_8_i_i_reg_470 <= ap_phi_precharge_reg_pp0_iter0_pix_val_V_1_8_i_i_reg_470;
                end if;
            end if; 
        end if;
    end process;

    ap_phi_precharge_reg_pp0_iter1_pix_val_V_2_8_i_i_reg_460_assign_proc : process (ap_clk)
    begin
        if (ap_clk'event and ap_clk = '1') then
            if ((ap_condition_515 = ap_const_boolean_1)) then
                if (((tmp_13_i_i_reg_1248 = ap_const_lv1_1) and (or_cond_6_i_i_reg_1394 = ap_const_lv1_0))) then 
                    ap_phi_precharge_reg_pp0_iter1_pix_val_V_2_8_i_i_reg_460 <= ap_phi_precharge_reg_pp0_iter0_pix_val_V_2_7_i_i_reg_427;
                elsif (((tmp_13_i_i_reg_1248 = ap_const_lv1_1) and (ap_const_lv1_1 = or_cond_6_i_i_reg_1394))) then 
                    ap_phi_precharge_reg_pp0_iter1_pix_val_V_2_8_i_i_reg_460 <= StrmMPix_V_val_2_V_dout;
                elsif ((ap_const_boolean_1 = ap_const_boolean_1)) then 
                    ap_phi_precharge_reg_pp0_iter1_pix_val_V_2_8_i_i_reg_460 <= ap_phi_precharge_reg_pp0_iter0_pix_val_V_2_8_i_i_reg_460;
                end if;
            end if; 
        end if;
    end process;

    x_i_i_reg_254_assign_proc : process (ap_clk)
    begin
        if (ap_clk'event and ap_clk = '1') then
            if (((tmp_13_i_i_reg_1248 = ap_const_lv1_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage0_flag00011001 = ap_const_boolean_0))) then 
                x_i_i_reg_254 <= x_reg_1252;
            elsif (((icmp_fu_555_p2 = ap_const_lv1_0) and (icmp1_fu_577_p2 = ap_const_lv1_0) and (ap_const_lv1_0 = tmp_i_i_fu_583_p2) and (ap_const_lv1_0 = icmp2_fu_605_p2) and (ap_const_lv1_0 = icmp3_fu_627_p2) and (ap_const_lv1_1 = icmp4_fu_649_p2) and (ap_const_logic_1 = ap_CS_fsm_state3) and (ap_const_lv1_0 = exitcond1_i_i_fu_880_p2))) then 
                x_i_i_reg_254 <= ap_const_lv8_0;
            end if; 
        end if;
    end process;

    y_i_i_reg_243_assign_proc : process (ap_clk)
    begin
        if (ap_clk'event and ap_clk = '1') then
            if ((ap_const_logic_1 = ap_CS_fsm_state13)) then 
                y_i_i_reg_243 <= y_reg_1243;
            elsif ((ap_const_logic_1 = ap_CS_fsm_state2)) then 
                y_i_i_reg_243 <= ap_const_lv16_0;
            end if; 
        end if;
    end process;
    process (ap_clk)
    begin
        if (ap_clk'event and ap_clk = '1') then
            if (((ap_const_logic_1 = ap_CS_fsm_state1) and not(((ap_const_logic_0 = ap_start) or (ap_done_reg = ap_const_logic_1) or (ap_const_logic_0 = HwReg_height_cast8_loc_empty_n) or (ap_const_logic_0 = tmp_3_loc_empty_n) or (ap_const_logic_0 = HwReg_height_cast8_loc_out_full_n) or (ap_const_logic_0 = tmp_3_loc_out_full_n) or (ap_const_logic_0 = HwReg_width_cast9_loc_empty_n))))) then
                HwReg_height_cast8_l_reg_1103 <= HwReg_height_cast8_loc_dout;
            end if;
        end if;
    end process;
    process (ap_clk)
    begin
        if (ap_clk'event and ap_clk = '1') then
            if (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_block_pp0_stage7_flag00011001 = ap_const_boolean_0))) then
                ap_phi_precharge_reg_pp0_iter1_pix_val_V_0_9_i_i_reg_510 <= ap_phi_precharge_reg_pp0_iter0_pix_val_V_0_9_i_i_reg_510;
                ap_phi_precharge_reg_pp0_iter1_pix_val_V_1_9_i_i_reg_500 <= ap_phi_precharge_reg_pp0_iter0_pix_val_V_1_9_i_i_reg_500;
                ap_phi_precharge_reg_pp0_iter1_pix_val_V_2_9_i_i_reg_490 <= ap_phi_precharge_reg_pp0_iter0_pix_val_V_2_9_i_i_reg_490;
                pix_val_V_1_7_i_i_reg_438 <= ap_phi_precharge_reg_pp0_iter0_pix_val_V_1_7_i_i_reg_438;
                pix_val_V_2_7_i_i_reg_427 <= ap_phi_precharge_reg_pp0_iter0_pix_val_V_2_7_i_i_reg_427;
            end if;
        end if;
    end process;
    process (ap_clk)
    begin
        if (ap_clk'event and ap_clk = '1') then
            if ((ap_const_logic_1 = ap_CS_fsm_state2)) then
                icmp5_reg_1194 <= icmp5_fu_802_p2;
                icmp6_reg_1204 <= icmp6_fu_824_p2;
                icmp7_reg_1229 <= icmp7_fu_864_p2;
                loopWidth_cast_i_i_c_reg_1169 <= mul_fu_693_p2(20 downto 12);
                    tmp_11_cast_i_i_reg_1179(8 downto 0) <= tmp_11_cast_i_i_fu_777_p1(8 downto 0);
                tmp_12_i_i_reg_1184 <= tmp_12_i_i_fu_780_p2;
                tmp_24_2_i_i_reg_1199 <= tmp_24_2_i_i_fu_808_p2;
                tmp_24_4_i_i_reg_1209 <= tmp_24_4_i_i_fu_830_p2;
                tmp_24_5_i_i_reg_1214 <= tmp_24_5_i_i_fu_836_p2;
                tmp_24_6_i_i_reg_1219 <= tmp_24_6_i_i_fu_842_p2;
                tmp_24_i_i_reg_1189 <= tmp_24_i_i_fu_786_p2;
                tmp_25_2_i_i_reg_1234 <= tmp_25_2_i_i_fu_870_p2;
                tmp_25_i_i_reg_1224 <= tmp_25_i_i_fu_848_p2;
                tmp_7_i_i_reg_1174 <= tmp_7_i_i_fu_712_p2;
            end if;
        end if;
    end process;
    process (ap_clk)
    begin
        if (ap_clk'event and ap_clk = '1') then
            if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_block_pp0_stage0_flag00011001 = ap_const_boolean_0) and (ap_const_lv1_1 = tmp_13_i_i_fu_895_p2))) then
                or_cond1_1_i_i_reg_1276 <= or_cond1_1_i_i_fu_921_p2;
                or_cond1_2_i_i_reg_1280 <= or_cond1_2_i_i_fu_926_p2;
                or_cond1_i_i_reg_1272 <= or_cond1_i_i_fu_916_p2;
                or_cond_i_i_reg_1268 <= or_cond_i_i_fu_911_p2;
                tmp_14_i_i_reg_1257 <= tmp_14_i_i_fu_906_p2;
            end if;
        end if;
    end process;
    process (ap_clk)
    begin
        if (ap_clk'event and ap_clk = '1') then
            if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (tmp_13_i_i_reg_1248 = ap_const_lv1_1) and (ap_block_pp0_stage1_flag00011001 = ap_const_boolean_0))) then
                or_cond_1_i_i_reg_1314 <= or_cond_1_i_i_fu_940_p2;
            end if;
        end if;
    end process;
    process (ap_clk)
    begin
        if (ap_clk'event and ap_clk = '1') then
            if (((tmp_13_i_i_reg_1248 = ap_const_lv1_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_block_pp0_stage2_flag00011001 = ap_const_boolean_0))) then
                or_cond_2_i_i_reg_1333 <= or_cond_2_i_i_fu_944_p2;
            end if;
        end if;
    end process;
    process (ap_clk)
    begin
        if (ap_clk'event and ap_clk = '1') then
            if (((tmp_13_i_i_reg_1248 = ap_const_lv1_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3) and (ap_block_pp0_stage3_flag00011001 = ap_const_boolean_0))) then
                or_cond_3_i_i_reg_1352 <= or_cond_3_i_i_fu_948_p2;
            end if;
        end if;
    end process;
    process (ap_clk)
    begin
        if (ap_clk'event and ap_clk = '1') then
            if (((tmp_13_i_i_reg_1248 = ap_const_lv1_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4) and (ap_block_pp0_stage4_flag00011001 = ap_const_boolean_0))) then
                or_cond_4_i_i_reg_1371 <= or_cond_4_i_i_fu_952_p2;
            end if;
        end if;
    end process;
    process (ap_clk)
    begin
        if (ap_clk'event and ap_clk = '1') then
            if (((tmp_13_i_i_reg_1248 = ap_const_lv1_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_block_pp0_stage5_flag00011001 = ap_const_boolean_0))) then
                or_cond_5_i_i_reg_1390 <= or_cond_5_i_i_fu_977_p2;
                or_cond_6_i_i_reg_1394 <= or_cond_6_i_i_fu_981_p2;
                or_cond_7_i_i_reg_1398 <= or_cond_7_i_i_fu_985_p2;
            end if;
        end if;
    end process;
    process (ap_clk)
    begin
        if (ap_clk'event and ap_clk = '1') then
            if (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_block_pp0_stage2_flag00011001 = ap_const_boolean_0))) then
                pix_val_V_0_2_i_i_reg_285 <= ap_phi_precharge_reg_pp0_iter0_pix_val_V_0_2_i_i_reg_285;
                pix_val_V_1_2_i_i_reg_275 <= ap_phi_precharge_reg_pp0_iter0_pix_val_V_1_2_i_i_reg_275;
                pix_val_V_2_2_i_i_reg_265 <= ap_phi_precharge_reg_pp0_iter0_pix_val_V_2_2_i_i_reg_265;
            end if;
        end if;
    end process;
    process (ap_clk)
    begin
        if (ap_clk'event and ap_clk = '1') then
            if (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3) and (ap_block_pp0_stage3_flag00011001 = ap_const_boolean_0))) then
                pix_val_V_0_3_i_i_reg_317 <= ap_phi_precharge_reg_pp0_iter0_pix_val_V_0_3_i_i_reg_317;
                pix_val_V_1_3_i_i_reg_306 <= ap_phi_precharge_reg_pp0_iter0_pix_val_V_1_3_i_i_reg_306;
                pix_val_V_2_3_i_i_reg_295 <= ap_phi_precharge_reg_pp0_iter0_pix_val_V_2_3_i_i_reg_295;
            end if;
        end if;
    end process;
    process (ap_clk)
    begin
        if (ap_clk'event and ap_clk = '1') then
            if (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_block_pp0_stage5_flag00011001 = ap_const_boolean_0))) then
                pix_val_V_0_5_i_i_reg_383 <= ap_phi_precharge_reg_pp0_iter0_pix_val_V_0_5_i_i_reg_383;
                pix_val_V_1_5_i_i_reg_372 <= ap_phi_precharge_reg_pp0_iter0_pix_val_V_1_5_i_i_reg_372;
                pix_val_V_2_5_i_i_reg_361 <= ap_phi_precharge_reg_pp0_iter0_pix_val_V_2_5_i_i_reg_361;
            end if;
        end if;
    end process;
    process (ap_clk)
    begin
        if (ap_clk'event and ap_clk = '1') then
            if (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_block_pp0_stage6_flag00011001 = ap_const_boolean_0))) then
                pix_val_V_0_6_i_i_reg_416 <= ap_phi_precharge_reg_pp0_iter0_pix_val_V_0_6_i_i_reg_416;
                pix_val_V_1_6_i_i_reg_405 <= ap_phi_precharge_reg_pp0_iter0_pix_val_V_1_6_i_i_reg_405;
                pix_val_V_2_6_i_i_reg_394 <= ap_phi_precharge_reg_pp0_iter0_pix_val_V_2_6_i_i_reg_394;
            end if;
        end if;
    end process;
    process (ap_clk)
    begin
        if (ap_clk'event and ap_clk = '1') then
            if (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4) and (ap_block_pp0_stage4_flag00011001 = ap_const_boolean_0))) then
                pix_val_V_2_4_i_i_reg_328 <= ap_phi_precharge_reg_pp0_iter0_pix_val_V_2_4_i_i_reg_328;
            end if;
        end if;
    end process;
    process (ap_clk)
    begin
        if (ap_clk'event and ap_clk = '1') then
            if (((ap_const_logic_1 = ap_CS_fsm_state1) and not(((ap_const_logic_0 = ap_start) or (ap_done_reg = ap_const_logic_1) or (ap_const_logic_0 = HwReg_height_cast8_loc_empty_n) or (ap_const_logic_0 = tmp_3_loc_empty_n) or (ap_const_logic_0 = HwReg_height_cast8_loc_out_full_n) or (ap_const_logic_0 = tmp_3_loc_out_full_n) or (ap_const_logic_0 = HwReg_width_cast9_loc_empty_n))) and (icmp_fu_555_p2 = ap_const_lv1_0) and (icmp1_fu_577_p2 = ap_const_lv1_0) and (ap_const_lv1_0 = tmp_i_i_fu_583_p2) and (ap_const_lv1_0 = icmp2_fu_605_p2) and (ap_const_lv1_0 = icmp3_fu_627_p2) and (ap_const_lv1_1 = icmp4_fu_649_p2))) then
                remPix_reg_1161 <= remPix_fu_681_p1;
                tmp_6_i_i_reg_1156 <= tmp_6_i_i_fu_675_p2;
            end if;
        end if;
    end process;
    process (ap_clk)
    begin
        if (ap_clk'event and ap_clk = '1') then
            if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_block_pp0_stage0_flag00011001 = ap_const_boolean_0))) then
                tmp_13_i_i_reg_1248 <= tmp_13_i_i_fu_895_p2;
            end if;
        end if;
    end process;
    process (ap_clk)
    begin
        if (ap_clk'event and ap_clk = '1') then
            if (((tmp_13_i_i_reg_1248 = ap_const_lv1_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage0_flag00011001 = ap_const_boolean_0))) then
                tmp_val_0_V_fu_174 <= pix_val_V_0_9_i_i_phi_fu_513_p4;
                tmp_val_1_V_fu_178 <= pix_val_V_1_9_i_i_phi_fu_503_p4;
                tmp_val_2_V_fu_182 <= pix_val_V_2_9_i_i_phi_fu_493_p4;
            end if;
        end if;
    end process;
    process (ap_clk)
    begin
        if (ap_clk'event and ap_clk = '1') then
            if (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_block_pp0_stage0_flag00011001 = ap_const_boolean_0))) then
                x_reg_1252 <= x_fu_900_p2;
            end if;
        end if;
    end process;
    process (ap_clk)
    begin
        if (ap_clk'event and ap_clk = '1') then
            if (((icmp_fu_555_p2 = ap_const_lv1_0) and (icmp1_fu_577_p2 = ap_const_lv1_0) and (ap_const_lv1_0 = tmp_i_i_fu_583_p2) and (ap_const_lv1_0 = icmp2_fu_605_p2) and (ap_const_lv1_0 = icmp3_fu_627_p2) and (ap_const_lv1_1 = icmp4_fu_649_p2) and (ap_const_logic_1 = ap_CS_fsm_state3))) then
                y_reg_1243 <= y_fu_885_p2;
            end if;
        end if;
    end process;
    tmp_11_cast_i_i_reg_1179(16 downto 9) <= "00000000";

    ap_NS_fsm_assign_proc : process (ap_start, ap_done_reg, ap_CS_fsm, ap_CS_fsm_state1, HwReg_height_cast8_loc_empty_n, HwReg_width_cast9_loc_empty_n, tmp_3_loc_empty_n, HwReg_height_cast8_loc_out_full_n, tmp_3_loc_out_full_n, ap_enable_reg_pp0_iter0, tmp_13_i_i_reg_1248, icmp_fu_555_p2, icmp1_fu_577_p2, tmp_i_i_fu_583_p2, icmp2_fu_605_p2, icmp3_fu_627_p2, icmp4_fu_649_p2, exitcond1_i_i_fu_880_p2, ap_CS_fsm_state3, ap_block_pp0_stage1_flag00011011, ap_block_pp0_stage7_flag00011011, ap_block_pp0_stage0_flag00011011, ap_block_pp0_stage2_flag00011011, ap_block_pp0_stage3_flag00011011, ap_block_pp0_stage4_flag00011011, ap_block_pp0_stage5_flag00011011, ap_block_pp0_stage6_flag00011011)
    begin
        case ap_CS_fsm is
            when ap_ST_fsm_state1 => 
                if (((ap_const_logic_1 = ap_CS_fsm_state1) and not(((ap_const_logic_0 = ap_start) or (ap_done_reg = ap_const_logic_1) or (ap_const_logic_0 = HwReg_height_cast8_loc_empty_n) or (ap_const_logic_0 = tmp_3_loc_empty_n) or (ap_const_logic_0 = HwReg_height_cast8_loc_out_full_n) or (ap_const_logic_0 = tmp_3_loc_out_full_n) or (ap_const_logic_0 = HwReg_width_cast9_loc_empty_n))) and (icmp_fu_555_p2 = ap_const_lv1_0) and (icmp1_fu_577_p2 = ap_const_lv1_0) and (ap_const_lv1_0 = tmp_i_i_fu_583_p2) and (ap_const_lv1_0 = icmp2_fu_605_p2) and (ap_const_lv1_0 = icmp3_fu_627_p2) and (ap_const_lv1_1 = icmp4_fu_649_p2))) then
                    ap_NS_fsm <= ap_ST_fsm_state2;
                elsif (((ap_const_logic_1 = ap_CS_fsm_state1) and not(((ap_const_logic_0 = ap_start) or (ap_done_reg = ap_const_logic_1) or (ap_const_logic_0 = HwReg_height_cast8_loc_empty_n) or (ap_const_logic_0 = tmp_3_loc_empty_n) or (ap_const_logic_0 = HwReg_height_cast8_loc_out_full_n) or (ap_const_logic_0 = tmp_3_loc_out_full_n) or (ap_const_logic_0 = HwReg_width_cast9_loc_empty_n))) and ((ap_const_lv1_1 = icmp_fu_555_p2) or (ap_const_lv1_1 = icmp1_fu_577_p2) or (ap_const_lv1_1 = tmp_i_i_fu_583_p2) or (ap_const_lv1_1 = icmp2_fu_605_p2) or (ap_const_lv1_1 = icmp3_fu_627_p2) or (ap_const_lv1_0 = icmp4_fu_649_p2)))) then
                    ap_NS_fsm <= ap_ST_fsm_state3;
                else
                    ap_NS_fsm <= ap_ST_fsm_state1;
                end if;
            when ap_ST_fsm_state2 => 
                ap_NS_fsm <= ap_ST_fsm_state3;
            when ap_ST_fsm_state3 => 
                if (((ap_const_logic_1 = ap_CS_fsm_state3) and ((ap_const_lv1_1 = icmp_fu_555_p2) or (ap_const_lv1_1 = icmp1_fu_577_p2) or (ap_const_lv1_1 = tmp_i_i_fu_583_p2) or (ap_const_lv1_1 = icmp2_fu_605_p2) or (ap_const_lv1_1 = icmp3_fu_627_p2) or (ap_const_lv1_0 = icmp4_fu_649_p2) or (ap_const_lv1_1 = exitcond1_i_i_fu_880_p2)))) then
                    ap_NS_fsm <= ap_ST_fsm_state1;
                else
                    ap_NS_fsm <= ap_ST_fsm_pp0_stage0;
                end if;
            when ap_ST_fsm_pp0_stage0 => 
                if ((ap_block_pp0_stage0_flag00011011 = ap_const_boolean_0)) then
                    ap_NS_fsm <= ap_ST_fsm_pp0_stage1;
                else
                    ap_NS_fsm <= ap_ST_fsm_pp0_stage0;
                end if;
            when ap_ST_fsm_pp0_stage1 => 
                if (((ap_block_pp0_stage1_flag00011011 = ap_const_boolean_0) and not(((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_block_pp0_stage1_flag00011011 = ap_const_boolean_0) and (tmp_13_i_i_reg_1248 = ap_const_lv1_0))))) then
                    ap_NS_fsm <= ap_ST_fsm_pp0_stage2;
                elsif (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_block_pp0_stage1_flag00011011 = ap_const_boolean_0) and (tmp_13_i_i_reg_1248 = ap_const_lv1_0))) then
                    ap_NS_fsm <= ap_ST_fsm_state13;
                else
                    ap_NS_fsm <= ap_ST_fsm_pp0_stage1;
                end if;
            when ap_ST_fsm_pp0_stage2 => 
                if ((ap_block_pp0_stage2_flag00011011 = ap_const_boolean_0)) then
                    ap_NS_fsm <= ap_ST_fsm_pp0_stage3;
                else
                    ap_NS_fsm <= ap_ST_fsm_pp0_stage2;
                end if;
            when ap_ST_fsm_pp0_stage3 => 
                if ((ap_block_pp0_stage3_flag00011011 = ap_const_boolean_0)) then
                    ap_NS_fsm <= ap_ST_fsm_pp0_stage4;
                else
                    ap_NS_fsm <= ap_ST_fsm_pp0_stage3;
                end if;
            when ap_ST_fsm_pp0_stage4 => 
                if ((ap_block_pp0_stage4_flag00011011 = ap_const_boolean_0)) then
                    ap_NS_fsm <= ap_ST_fsm_pp0_stage5;
                else
                    ap_NS_fsm <= ap_ST_fsm_pp0_stage4;
                end if;
            when ap_ST_fsm_pp0_stage5 => 
                if ((ap_block_pp0_stage5_flag00011011 = ap_const_boolean_0)) then
                    ap_NS_fsm <= ap_ST_fsm_pp0_stage6;
                else
                    ap_NS_fsm <= ap_ST_fsm_pp0_stage5;
                end if;
            when ap_ST_fsm_pp0_stage6 => 
                if ((ap_block_pp0_stage6_flag00011011 = ap_const_boolean_0)) then
                    ap_NS_fsm <= ap_ST_fsm_pp0_stage7;
                else
                    ap_NS_fsm <= ap_ST_fsm_pp0_stage6;
                end if;
            when ap_ST_fsm_pp0_stage7 => 
                if ((ap_block_pp0_stage7_flag00011011 = ap_const_boolean_0)) then
                    ap_NS_fsm <= ap_ST_fsm_pp0_stage0;
                else
                    ap_NS_fsm <= ap_ST_fsm_pp0_stage7;
                end if;
            when ap_ST_fsm_state13 => 
                ap_NS_fsm <= ap_ST_fsm_state3;
            when others =>  
                ap_NS_fsm <= "XXXXXXXXXXXX";
        end case;
    end process;

    HwReg_height_cast8_loc_blk_n_assign_proc : process(ap_start, ap_done_reg, ap_CS_fsm_state1, HwReg_height_cast8_loc_empty_n)
    begin
        if (((ap_const_logic_1 = ap_CS_fsm_state1) and not(((ap_const_logic_0 = ap_start) or (ap_done_reg = ap_const_logic_1))))) then 
            HwReg_height_cast8_loc_blk_n <= HwReg_height_cast8_loc_empty_n;
        else 
            HwReg_height_cast8_loc_blk_n <= ap_const_logic_1;
        end if; 
    end process;


    HwReg_height_cast8_loc_out_blk_n_assign_proc : process(ap_start, ap_done_reg, ap_CS_fsm_state1, HwReg_height_cast8_loc_out_full_n)
    begin
        if (((ap_const_logic_1 = ap_CS_fsm_state1) and not(((ap_const_logic_0 = ap_start) or (ap_done_reg = ap_const_logic_1))))) then 
            HwReg_height_cast8_loc_out_blk_n <= HwReg_height_cast8_loc_out_full_n;
        else 
            HwReg_height_cast8_loc_out_blk_n <= ap_const_logic_1;
        end if; 
    end process;

    HwReg_height_cast8_loc_out_din <= HwReg_height_cast8_loc_dout;

    HwReg_height_cast8_loc_out_write_assign_proc : process(ap_start, ap_done_reg, ap_CS_fsm_state1, HwReg_height_cast8_loc_empty_n, HwReg_width_cast9_loc_empty_n, tmp_3_loc_empty_n, HwReg_height_cast8_loc_out_full_n, tmp_3_loc_out_full_n)
    begin
        if (((ap_const_logic_1 = ap_CS_fsm_state1) and not(((ap_const_logic_0 = ap_start) or (ap_done_reg = ap_const_logic_1) or (ap_const_logic_0 = HwReg_height_cast8_loc_empty_n) or (ap_const_logic_0 = tmp_3_loc_empty_n) or (ap_const_logic_0 = HwReg_height_cast8_loc_out_full_n) or (ap_const_logic_0 = tmp_3_loc_out_full_n) or (ap_const_logic_0 = HwReg_width_cast9_loc_empty_n))))) then 
            HwReg_height_cast8_loc_out_write <= ap_const_logic_1;
        else 
            HwReg_height_cast8_loc_out_write <= ap_const_logic_0;
        end if; 
    end process;


    HwReg_height_cast8_loc_read_assign_proc : process(ap_start, ap_done_reg, ap_CS_fsm_state1, HwReg_height_cast8_loc_empty_n, HwReg_width_cast9_loc_empty_n, tmp_3_loc_empty_n, HwReg_height_cast8_loc_out_full_n, tmp_3_loc_out_full_n)
    begin
        if (((ap_const_logic_1 = ap_CS_fsm_state1) and not(((ap_const_logic_0 = ap_start) or (ap_done_reg = ap_const_logic_1) or (ap_const_logic_0 = HwReg_height_cast8_loc_empty_n) or (ap_const_logic_0 = tmp_3_loc_empty_n) or (ap_const_logic_0 = HwReg_height_cast8_loc_out_full_n) or (ap_const_logic_0 = tmp_3_loc_out_full_n) or (ap_const_logic_0 = HwReg_width_cast9_loc_empty_n))))) then 
            HwReg_height_cast8_loc_read <= ap_const_logic_1;
        else 
            HwReg_height_cast8_loc_read <= ap_const_logic_0;
        end if; 
    end process;


    HwReg_width_cast9_loc_blk_n_assign_proc : process(ap_start, ap_done_reg, ap_CS_fsm_state1, HwReg_width_cast9_loc_empty_n)
    begin
        if (((ap_const_logic_1 = ap_CS_fsm_state1) and not(((ap_const_logic_0 = ap_start) or (ap_done_reg = ap_const_logic_1))))) then 
            HwReg_width_cast9_loc_blk_n <= HwReg_width_cast9_loc_empty_n;
        else 
            HwReg_width_cast9_loc_blk_n <= ap_const_logic_1;
        end if; 
    end process;


    HwReg_width_cast9_loc_read_assign_proc : process(ap_start, ap_done_reg, ap_CS_fsm_state1, HwReg_height_cast8_loc_empty_n, HwReg_width_cast9_loc_empty_n, tmp_3_loc_empty_n, HwReg_height_cast8_loc_out_full_n, tmp_3_loc_out_full_n)
    begin
        if (((ap_const_logic_1 = ap_CS_fsm_state1) and not(((ap_const_logic_0 = ap_start) or (ap_done_reg = ap_const_logic_1) or (ap_const_logic_0 = HwReg_height_cast8_loc_empty_n) or (ap_const_logic_0 = tmp_3_loc_empty_n) or (ap_const_logic_0 = HwReg_height_cast8_loc_out_full_n) or (ap_const_logic_0 = tmp_3_loc_out_full_n) or (ap_const_logic_0 = HwReg_width_cast9_loc_empty_n))))) then 
            HwReg_width_cast9_loc_read <= ap_const_logic_1;
        else 
            HwReg_width_cast9_loc_read <= ap_const_logic_0;
        end if; 
    end process;

    StrmMPix_V_val_0_V0_status <= (StrmMPix_V_val_0_V_empty_n and StrmMPix_V_val_1_V_empty_n and StrmMPix_V_val_2_V_empty_n);

    StrmMPix_V_val_0_V0_update_assign_proc : process(ap_CS_fsm_pp0_stage1, ap_enable_reg_pp0_iter0, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage7, ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter1, ap_predicate_op205_read_state12, ap_block_pp0_stage0_flag00011001, ap_predicate_op129_read_state5, ap_block_pp0_stage1_flag00011001, ap_predicate_op139_read_state6, ap_block_pp0_stage2_flag00011001, ap_predicate_op149_read_state7, ap_block_pp0_stage3_flag00011001, ap_predicate_op159_read_state8, ap_block_pp0_stage4_flag00011001, ap_predicate_op172_read_state9, ap_block_pp0_stage5_flag00011001, ap_predicate_op184_read_state10, ap_block_pp0_stage6_flag00011001, ap_predicate_op193_read_state11, ap_block_pp0_stage7_flag00011001)
    begin
        if ((((ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_boolean_1 = ap_predicate_op129_read_state5) and (ap_block_pp0_stage1_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_const_boolean_1 = ap_predicate_op139_read_state6) and (ap_block_pp0_stage2_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3) and (ap_const_boolean_1 = ap_predicate_op149_read_state7) and (ap_block_pp0_stage3_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4) and (ap_const_boolean_1 = ap_predicate_op159_read_state8) and (ap_block_pp0_stage4_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_const_boolean_1 = ap_predicate_op172_read_state9) and (ap_block_pp0_stage5_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_const_boolean_1 = ap_predicate_op184_read_state10) and (ap_block_pp0_stage6_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_const_boolean_1 = ap_predicate_op193_read_state11) and (ap_block_pp0_stage7_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_boolean_1 = ap_predicate_op205_read_state12) and (ap_block_pp0_stage0_flag00011001 = ap_const_boolean_0)))) then 
            StrmMPix_V_val_0_V0_update <= ap_const_logic_1;
        else 
            StrmMPix_V_val_0_V0_update <= ap_const_logic_0;
        end if; 
    end process;


    StrmMPix_V_val_0_V_blk_n_assign_proc : process(StrmMPix_V_val_0_V_empty_n, ap_CS_fsm_pp0_stage1, ap_enable_reg_pp0_iter0, ap_block_pp0_stage1_flag00000000, tmp_13_i_i_reg_1248, or_cond_i_i_reg_1268, ap_CS_fsm_pp0_stage2, ap_block_pp0_stage2_flag00000000, or_cond_1_i_i_reg_1314, ap_CS_fsm_pp0_stage3, ap_block_pp0_stage3_flag00000000, or_cond_2_i_i_reg_1333, ap_CS_fsm_pp0_stage4, ap_block_pp0_stage4_flag00000000, or_cond_3_i_i_reg_1352, ap_CS_fsm_pp0_stage5, ap_block_pp0_stage5_flag00000000, or_cond_4_i_i_reg_1371, ap_CS_fsm_pp0_stage6, ap_block_pp0_stage6_flag00000000, or_cond_5_i_i_reg_1390, ap_CS_fsm_pp0_stage7, ap_block_pp0_stage7_flag00000000, or_cond_6_i_i_reg_1394, ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter1, ap_block_pp0_stage0_flag00000000, or_cond_7_i_i_reg_1398)
    begin
        if ((((ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_block_pp0_stage1_flag00000000 = ap_const_boolean_0) and (tmp_13_i_i_reg_1248 = ap_const_lv1_1) and (ap_const_lv1_1 = or_cond_i_i_reg_1268)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (tmp_13_i_i_reg_1248 = ap_const_lv1_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_block_pp0_stage2_flag00000000 = ap_const_boolean_0) and (ap_const_lv1_1 = or_cond_1_i_i_reg_1314)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (tmp_13_i_i_reg_1248 = ap_const_lv1_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3) and (ap_block_pp0_stage3_flag00000000 = ap_const_boolean_0) and (ap_const_lv1_1 = or_cond_2_i_i_reg_1333)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (tmp_13_i_i_reg_1248 = ap_const_lv1_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4) and (ap_block_pp0_stage4_flag00000000 = ap_const_boolean_0) and (ap_const_lv1_1 = or_cond_3_i_i_reg_1352)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (tmp_13_i_i_reg_1248 = ap_const_lv1_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_block_pp0_stage5_flag00000000 = ap_const_boolean_0) and (ap_const_lv1_1 = or_cond_4_i_i_reg_1371)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (tmp_13_i_i_reg_1248 = ap_const_lv1_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_block_pp0_stage6_flag00000000 = ap_const_boolean_0) and (ap_const_lv1_1 = or_cond_5_i_i_reg_1390)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (tmp_13_i_i_reg_1248 = ap_const_lv1_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_block_pp0_stage7_flag00000000 = ap_const_boolean_0) and (ap_const_lv1_1 = or_cond_6_i_i_reg_1394)) or ((tmp_13_i_i_reg_1248 = ap_const_lv1_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage0_flag00000000 = ap_const_boolean_0) and (ap_const_lv1_1 = or_cond_7_i_i_reg_1398)))) then 
            StrmMPix_V_val_0_V_blk_n <= StrmMPix_V_val_0_V_empty_n;
        else 
            StrmMPix_V_val_0_V_blk_n <= ap_const_logic_1;
        end if; 
    end process;

    StrmMPix_V_val_0_V_read <= StrmMPix_V_val_0_V0_update;

    StrmMPix_V_val_1_V_blk_n_assign_proc : process(StrmMPix_V_val_1_V_empty_n, ap_CS_fsm_pp0_stage1, ap_enable_reg_pp0_iter0, ap_block_pp0_stage1_flag00000000, tmp_13_i_i_reg_1248, or_cond_i_i_reg_1268, ap_CS_fsm_pp0_stage2, ap_block_pp0_stage2_flag00000000, or_cond_1_i_i_reg_1314, ap_CS_fsm_pp0_stage3, ap_block_pp0_stage3_flag00000000, or_cond_2_i_i_reg_1333, ap_CS_fsm_pp0_stage4, ap_block_pp0_stage4_flag00000000, or_cond_3_i_i_reg_1352, ap_CS_fsm_pp0_stage5, ap_block_pp0_stage5_flag00000000, or_cond_4_i_i_reg_1371, ap_CS_fsm_pp0_stage6, ap_block_pp0_stage6_flag00000000, or_cond_5_i_i_reg_1390, ap_CS_fsm_pp0_stage7, ap_block_pp0_stage7_flag00000000, or_cond_6_i_i_reg_1394, ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter1, ap_block_pp0_stage0_flag00000000, or_cond_7_i_i_reg_1398)
    begin
        if ((((ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_block_pp0_stage1_flag00000000 = ap_const_boolean_0) and (tmp_13_i_i_reg_1248 = ap_const_lv1_1) and (ap_const_lv1_1 = or_cond_i_i_reg_1268)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (tmp_13_i_i_reg_1248 = ap_const_lv1_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_block_pp0_stage2_flag00000000 = ap_const_boolean_0) and (ap_const_lv1_1 = or_cond_1_i_i_reg_1314)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (tmp_13_i_i_reg_1248 = ap_const_lv1_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3) and (ap_block_pp0_stage3_flag00000000 = ap_const_boolean_0) and (ap_const_lv1_1 = or_cond_2_i_i_reg_1333)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (tmp_13_i_i_reg_1248 = ap_const_lv1_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4) and (ap_block_pp0_stage4_flag00000000 = ap_const_boolean_0) and (ap_const_lv1_1 = or_cond_3_i_i_reg_1352)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (tmp_13_i_i_reg_1248 = ap_const_lv1_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_block_pp0_stage5_flag00000000 = ap_const_boolean_0) and (ap_const_lv1_1 = or_cond_4_i_i_reg_1371)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (tmp_13_i_i_reg_1248 = ap_const_lv1_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_block_pp0_stage6_flag00000000 = ap_const_boolean_0) and (ap_const_lv1_1 = or_cond_5_i_i_reg_1390)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (tmp_13_i_i_reg_1248 = ap_const_lv1_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_block_pp0_stage7_flag00000000 = ap_const_boolean_0) and (ap_const_lv1_1 = or_cond_6_i_i_reg_1394)) or ((tmp_13_i_i_reg_1248 = ap_const_lv1_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage0_flag00000000 = ap_const_boolean_0) and (ap_const_lv1_1 = or_cond_7_i_i_reg_1398)))) then 
            StrmMPix_V_val_1_V_blk_n <= StrmMPix_V_val_1_V_empty_n;
        else 
            StrmMPix_V_val_1_V_blk_n <= ap_const_logic_1;
        end if; 
    end process;

    StrmMPix_V_val_1_V_read <= StrmMPix_V_val_0_V0_update;

    StrmMPix_V_val_2_V_blk_n_assign_proc : process(StrmMPix_V_val_2_V_empty_n, ap_CS_fsm_pp0_stage1, ap_enable_reg_pp0_iter0, ap_block_pp0_stage1_flag00000000, tmp_13_i_i_reg_1248, or_cond_i_i_reg_1268, ap_CS_fsm_pp0_stage2, ap_block_pp0_stage2_flag00000000, or_cond_1_i_i_reg_1314, ap_CS_fsm_pp0_stage3, ap_block_pp0_stage3_flag00000000, or_cond_2_i_i_reg_1333, ap_CS_fsm_pp0_stage4, ap_block_pp0_stage4_flag00000000, or_cond_3_i_i_reg_1352, ap_CS_fsm_pp0_stage5, ap_block_pp0_stage5_flag00000000, or_cond_4_i_i_reg_1371, ap_CS_fsm_pp0_stage6, ap_block_pp0_stage6_flag00000000, or_cond_5_i_i_reg_1390, ap_CS_fsm_pp0_stage7, ap_block_pp0_stage7_flag00000000, or_cond_6_i_i_reg_1394, ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter1, ap_block_pp0_stage0_flag00000000, or_cond_7_i_i_reg_1398)
    begin
        if ((((ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_block_pp0_stage1_flag00000000 = ap_const_boolean_0) and (tmp_13_i_i_reg_1248 = ap_const_lv1_1) and (ap_const_lv1_1 = or_cond_i_i_reg_1268)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (tmp_13_i_i_reg_1248 = ap_const_lv1_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_block_pp0_stage2_flag00000000 = ap_const_boolean_0) and (ap_const_lv1_1 = or_cond_1_i_i_reg_1314)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (tmp_13_i_i_reg_1248 = ap_const_lv1_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3) and (ap_block_pp0_stage3_flag00000000 = ap_const_boolean_0) and (ap_const_lv1_1 = or_cond_2_i_i_reg_1333)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (tmp_13_i_i_reg_1248 = ap_const_lv1_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4) and (ap_block_pp0_stage4_flag00000000 = ap_const_boolean_0) and (ap_const_lv1_1 = or_cond_3_i_i_reg_1352)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (tmp_13_i_i_reg_1248 = ap_const_lv1_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_block_pp0_stage5_flag00000000 = ap_const_boolean_0) and (ap_const_lv1_1 = or_cond_4_i_i_reg_1371)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (tmp_13_i_i_reg_1248 = ap_const_lv1_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_block_pp0_stage6_flag00000000 = ap_const_boolean_0) and (ap_const_lv1_1 = or_cond_5_i_i_reg_1390)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (tmp_13_i_i_reg_1248 = ap_const_lv1_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_block_pp0_stage7_flag00000000 = ap_const_boolean_0) and (ap_const_lv1_1 = or_cond_6_i_i_reg_1394)) or ((tmp_13_i_i_reg_1248 = ap_const_lv1_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage0_flag00000000 = ap_const_boolean_0) and (ap_const_lv1_1 = or_cond_7_i_i_reg_1398)))) then 
            StrmMPix_V_val_2_V_blk_n <= StrmMPix_V_val_2_V_empty_n;
        else 
            StrmMPix_V_val_2_V_blk_n <= ap_const_logic_1;
        end if; 
    end process;

    StrmMPix_V_val_2_V_read <= StrmMPix_V_val_0_V0_update;
    VideoFormat_off1_i_i_fu_561_p2 <= std_logic_vector(unsigned(tmp_fu_535_p1) + unsigned(ap_const_lv8_F1));
    VideoFormat_off2_i_i_fu_589_p2 <= std_logic_vector(unsigned(tmp_fu_535_p1) + unsigned(ap_const_lv8_EE));
    VideoFormat_off3_i_i_fu_611_p2 <= std_logic_vector(unsigned(tmp_fu_535_p1) + unsigned(ap_const_lv8_EA));
    VideoFormat_off4_i_i_fu_633_p2 <= std_logic_vector(unsigned(tmp_fu_535_p1) + unsigned(ap_const_lv8_EC));
    VideoFormat_off_i_i_fu_539_p2 <= std_logic_vector(signed(ap_const_lv8_F6) + signed(tmp_fu_535_p1));
    ap_CS_fsm_pp0_stage0 <= ap_CS_fsm(3);
    ap_CS_fsm_pp0_stage1 <= ap_CS_fsm(4);
    ap_CS_fsm_pp0_stage2 <= ap_CS_fsm(5);
    ap_CS_fsm_pp0_stage3 <= ap_CS_fsm(6);
    ap_CS_fsm_pp0_stage4 <= ap_CS_fsm(7);
    ap_CS_fsm_pp0_stage5 <= ap_CS_fsm(8);
    ap_CS_fsm_pp0_stage6 <= ap_CS_fsm(9);
    ap_CS_fsm_pp0_stage7 <= ap_CS_fsm(10);
    ap_CS_fsm_state1 <= ap_CS_fsm(0);
    ap_CS_fsm_state13 <= ap_CS_fsm(11);
    ap_CS_fsm_state2 <= ap_CS_fsm(1);
    ap_CS_fsm_state3 <= ap_CS_fsm(2);
        ap_block_pp0_stage0_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1));

    ap_block_pp0_stage0_flag00001001_assign_proc : process(bytes_plane0_V_V_full_n, ap_enable_reg_pp0_iter1, or_cond1_2_i_i_reg_1280, StrmMPix_V_val_0_V0_status, ap_predicate_op205_read_state12)
    begin
                ap_block_pp0_stage0_flag00001001 <= ((ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (((ap_const_logic_0 = StrmMPix_V_val_0_V0_status) and (ap_const_boolean_1 = ap_predicate_op205_read_state12)) or ((ap_const_lv1_1 = or_cond1_2_i_i_reg_1280) and (ap_const_logic_0 = bytes_plane0_V_V_full_n))));
    end process;


    ap_block_pp0_stage0_flag00011001_assign_proc : process(bytes_plane0_V_V_full_n, ap_enable_reg_pp0_iter1, or_cond1_2_i_i_reg_1280, StrmMPix_V_val_0_V0_status, ap_predicate_op205_read_state12)
    begin
                ap_block_pp0_stage0_flag00011001 <= ((ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (((ap_const_logic_0 = StrmMPix_V_val_0_V0_status) and (ap_const_boolean_1 = ap_predicate_op205_read_state12)) or ((ap_const_lv1_1 = or_cond1_2_i_i_reg_1280) and (ap_const_logic_0 = bytes_plane0_V_V_full_n))));
    end process;


    ap_block_pp0_stage0_flag00011011_assign_proc : process(bytes_plane0_V_V_full_n, ap_enable_reg_pp0_iter1, or_cond1_2_i_i_reg_1280, StrmMPix_V_val_0_V0_status, ap_predicate_op205_read_state12)
    begin
                ap_block_pp0_stage0_flag00011011 <= ((ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (((ap_const_logic_0 = StrmMPix_V_val_0_V0_status) and (ap_const_boolean_1 = ap_predicate_op205_read_state12)) or ((ap_const_lv1_1 = or_cond1_2_i_i_reg_1280) and (ap_const_logic_0 = bytes_plane0_V_V_full_n))));
    end process;

        ap_block_pp0_stage1_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1));

    ap_block_pp0_stage1_flag00011001_assign_proc : process(ap_enable_reg_pp0_iter0, StrmMPix_V_val_0_V0_status, ap_predicate_op129_read_state5)
    begin
                ap_block_pp0_stage1_flag00011001 <= ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_0 = StrmMPix_V_val_0_V0_status) and (ap_const_boolean_1 = ap_predicate_op129_read_state5));
    end process;


    ap_block_pp0_stage1_flag00011011_assign_proc : process(ap_enable_reg_pp0_iter0, StrmMPix_V_val_0_V0_status, ap_predicate_op129_read_state5)
    begin
                ap_block_pp0_stage1_flag00011011 <= ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_0 = StrmMPix_V_val_0_V0_status) and (ap_const_boolean_1 = ap_predicate_op129_read_state5));
    end process;

        ap_block_pp0_stage2_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1));

    ap_block_pp0_stage2_flag00011001_assign_proc : process(ap_enable_reg_pp0_iter0, StrmMPix_V_val_0_V0_status, ap_predicate_op139_read_state6)
    begin
                ap_block_pp0_stage2_flag00011001 <= ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_0 = StrmMPix_V_val_0_V0_status) and (ap_const_boolean_1 = ap_predicate_op139_read_state6));
    end process;


    ap_block_pp0_stage2_flag00011011_assign_proc : process(ap_enable_reg_pp0_iter0, StrmMPix_V_val_0_V0_status, ap_predicate_op139_read_state6)
    begin
                ap_block_pp0_stage2_flag00011011 <= ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_0 = StrmMPix_V_val_0_V0_status) and (ap_const_boolean_1 = ap_predicate_op139_read_state6));
    end process;

        ap_block_pp0_stage3_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1));

    ap_block_pp0_stage3_flag00011001_assign_proc : process(ap_enable_reg_pp0_iter0, StrmMPix_V_val_0_V0_status, ap_predicate_op149_read_state7)
    begin
                ap_block_pp0_stage3_flag00011001 <= ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_0 = StrmMPix_V_val_0_V0_status) and (ap_const_boolean_1 = ap_predicate_op149_read_state7));
    end process;


    ap_block_pp0_stage3_flag00011011_assign_proc : process(ap_enable_reg_pp0_iter0, StrmMPix_V_val_0_V0_status, ap_predicate_op149_read_state7)
    begin
                ap_block_pp0_stage3_flag00011011 <= ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_0 = StrmMPix_V_val_0_V0_status) and (ap_const_boolean_1 = ap_predicate_op149_read_state7));
    end process;

        ap_block_pp0_stage4_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1));

    ap_block_pp0_stage4_flag00001001_assign_proc : process(bytes_plane0_V_V_full_n, ap_enable_reg_pp0_iter0, StrmMPix_V_val_0_V0_status, ap_predicate_op159_read_state8, ap_predicate_op166_write_state8)
    begin
                ap_block_pp0_stage4_flag00001001 <= ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (((ap_const_logic_0 = StrmMPix_V_val_0_V0_status) and (ap_const_boolean_1 = ap_predicate_op159_read_state8)) or ((ap_const_logic_0 = bytes_plane0_V_V_full_n) and (ap_const_boolean_1 = ap_predicate_op166_write_state8))));
    end process;


    ap_block_pp0_stage4_flag00011001_assign_proc : process(bytes_plane0_V_V_full_n, ap_enable_reg_pp0_iter0, StrmMPix_V_val_0_V0_status, ap_predicate_op159_read_state8, ap_predicate_op166_write_state8)
    begin
                ap_block_pp0_stage4_flag00011001 <= ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (((ap_const_logic_0 = StrmMPix_V_val_0_V0_status) and (ap_const_boolean_1 = ap_predicate_op159_read_state8)) or ((ap_const_logic_0 = bytes_plane0_V_V_full_n) and (ap_const_boolean_1 = ap_predicate_op166_write_state8))));
    end process;


    ap_block_pp0_stage4_flag00011011_assign_proc : process(bytes_plane0_V_V_full_n, ap_enable_reg_pp0_iter0, StrmMPix_V_val_0_V0_status, ap_predicate_op159_read_state8, ap_predicate_op166_write_state8)
    begin
                ap_block_pp0_stage4_flag00011011 <= ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (((ap_const_logic_0 = StrmMPix_V_val_0_V0_status) and (ap_const_boolean_1 = ap_predicate_op159_read_state8)) or ((ap_const_logic_0 = bytes_plane0_V_V_full_n) and (ap_const_boolean_1 = ap_predicate_op166_write_state8))));
    end process;

        ap_block_pp0_stage5_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1));

    ap_block_pp0_stage5_flag00011001_assign_proc : process(ap_enable_reg_pp0_iter0, StrmMPix_V_val_0_V0_status, ap_predicate_op172_read_state9)
    begin
                ap_block_pp0_stage5_flag00011001 <= ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_0 = StrmMPix_V_val_0_V0_status) and (ap_const_boolean_1 = ap_predicate_op172_read_state9));
    end process;


    ap_block_pp0_stage5_flag00011011_assign_proc : process(ap_enable_reg_pp0_iter0, StrmMPix_V_val_0_V0_status, ap_predicate_op172_read_state9)
    begin
                ap_block_pp0_stage5_flag00011011 <= ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_0 = StrmMPix_V_val_0_V0_status) and (ap_const_boolean_1 = ap_predicate_op172_read_state9));
    end process;

        ap_block_pp0_stage6_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1));

    ap_block_pp0_stage6_flag00011001_assign_proc : process(ap_enable_reg_pp0_iter0, StrmMPix_V_val_0_V0_status, ap_predicate_op184_read_state10)
    begin
                ap_block_pp0_stage6_flag00011001 <= ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_0 = StrmMPix_V_val_0_V0_status) and (ap_const_boolean_1 = ap_predicate_op184_read_state10));
    end process;


    ap_block_pp0_stage6_flag00011011_assign_proc : process(ap_enable_reg_pp0_iter0, StrmMPix_V_val_0_V0_status, ap_predicate_op184_read_state10)
    begin
                ap_block_pp0_stage6_flag00011011 <= ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_0 = StrmMPix_V_val_0_V0_status) and (ap_const_boolean_1 = ap_predicate_op184_read_state10));
    end process;

        ap_block_pp0_stage7_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1));

    ap_block_pp0_stage7_flag00001001_assign_proc : process(bytes_plane0_V_V_full_n, ap_enable_reg_pp0_iter0, StrmMPix_V_val_0_V0_status, ap_predicate_op193_read_state11, ap_predicate_op199_write_state11)
    begin
                ap_block_pp0_stage7_flag00001001 <= ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (((ap_const_logic_0 = StrmMPix_V_val_0_V0_status) and (ap_const_boolean_1 = ap_predicate_op193_read_state11)) or ((ap_const_logic_0 = bytes_plane0_V_V_full_n) and (ap_const_boolean_1 = ap_predicate_op199_write_state11))));
    end process;


    ap_block_pp0_stage7_flag00011001_assign_proc : process(bytes_plane0_V_V_full_n, ap_enable_reg_pp0_iter0, StrmMPix_V_val_0_V0_status, ap_predicate_op193_read_state11, ap_predicate_op199_write_state11)
    begin
                ap_block_pp0_stage7_flag00011001 <= ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (((ap_const_logic_0 = StrmMPix_V_val_0_V0_status) and (ap_const_boolean_1 = ap_predicate_op193_read_state11)) or ((ap_const_logic_0 = bytes_plane0_V_V_full_n) and (ap_const_boolean_1 = ap_predicate_op199_write_state11))));
    end process;


    ap_block_pp0_stage7_flag00011011_assign_proc : process(bytes_plane0_V_V_full_n, ap_enable_reg_pp0_iter0, StrmMPix_V_val_0_V0_status, ap_predicate_op193_read_state11, ap_predicate_op199_write_state11)
    begin
                ap_block_pp0_stage7_flag00011011 <= ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (((ap_const_logic_0 = StrmMPix_V_val_0_V0_status) and (ap_const_boolean_1 = ap_predicate_op193_read_state11)) or ((ap_const_logic_0 = bytes_plane0_V_V_full_n) and (ap_const_boolean_1 = ap_predicate_op199_write_state11))));
    end process;


    ap_block_state1_assign_proc : process(ap_start, ap_done_reg, HwReg_height_cast8_loc_empty_n, HwReg_width_cast9_loc_empty_n, tmp_3_loc_empty_n, HwReg_height_cast8_loc_out_full_n, tmp_3_loc_out_full_n)
    begin
                ap_block_state1 <= ((ap_const_logic_0 = ap_start) or (ap_done_reg = ap_const_logic_1) or (ap_const_logic_0 = HwReg_height_cast8_loc_empty_n) or (ap_const_logic_0 = tmp_3_loc_empty_n) or (ap_const_logic_0 = HwReg_height_cast8_loc_out_full_n) or (ap_const_logic_0 = tmp_3_loc_out_full_n) or (ap_const_logic_0 = HwReg_width_cast9_loc_empty_n));
    end process;


    ap_block_state10_pp0_stage6_iter0_assign_proc : process(StrmMPix_V_val_0_V0_status, ap_predicate_op184_read_state10)
    begin
                ap_block_state10_pp0_stage6_iter0 <= ((ap_const_logic_0 = StrmMPix_V_val_0_V0_status) and (ap_const_boolean_1 = ap_predicate_op184_read_state10));
    end process;


    ap_block_state11_pp0_stage7_iter0_assign_proc : process(bytes_plane0_V_V_full_n, StrmMPix_V_val_0_V0_status, ap_predicate_op193_read_state11, ap_predicate_op199_write_state11)
    begin
                ap_block_state11_pp0_stage7_iter0 <= (((ap_const_logic_0 = StrmMPix_V_val_0_V0_status) and (ap_const_boolean_1 = ap_predicate_op193_read_state11)) or ((ap_const_logic_0 = bytes_plane0_V_V_full_n) and (ap_const_boolean_1 = ap_predicate_op199_write_state11)));
    end process;


    ap_block_state12_pp0_stage0_iter1_assign_proc : process(bytes_plane0_V_V_full_n, or_cond1_2_i_i_reg_1280, StrmMPix_V_val_0_V0_status, ap_predicate_op205_read_state12)
    begin
                ap_block_state12_pp0_stage0_iter1 <= (((ap_const_logic_0 = StrmMPix_V_val_0_V0_status) and (ap_const_boolean_1 = ap_predicate_op205_read_state12)) or ((ap_const_lv1_1 = or_cond1_2_i_i_reg_1280) and (ap_const_logic_0 = bytes_plane0_V_V_full_n)));
    end process;

        ap_block_state4_pp0_stage0_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1));

    ap_block_state5_pp0_stage1_iter0_assign_proc : process(StrmMPix_V_val_0_V0_status, ap_predicate_op129_read_state5)
    begin
                ap_block_state5_pp0_stage1_iter0 <= ((ap_const_logic_0 = StrmMPix_V_val_0_V0_status) and (ap_const_boolean_1 = ap_predicate_op129_read_state5));
    end process;


    ap_block_state6_pp0_stage2_iter0_assign_proc : process(StrmMPix_V_val_0_V0_status, ap_predicate_op139_read_state6)
    begin
                ap_block_state6_pp0_stage2_iter0 <= ((ap_const_logic_0 = StrmMPix_V_val_0_V0_status) and (ap_const_boolean_1 = ap_predicate_op139_read_state6));
    end process;


    ap_block_state7_pp0_stage3_iter0_assign_proc : process(StrmMPix_V_val_0_V0_status, ap_predicate_op149_read_state7)
    begin
                ap_block_state7_pp0_stage3_iter0 <= ((ap_const_logic_0 = StrmMPix_V_val_0_V0_status) and (ap_const_boolean_1 = ap_predicate_op149_read_state7));
    end process;


    ap_block_state8_pp0_stage4_iter0_assign_proc : process(bytes_plane0_V_V_full_n, StrmMPix_V_val_0_V0_status, ap_predicate_op159_read_state8, ap_predicate_op166_write_state8)
    begin
                ap_block_state8_pp0_stage4_iter0 <= (((ap_const_logic_0 = StrmMPix_V_val_0_V0_status) and (ap_const_boolean_1 = ap_predicate_op159_read_state8)) or ((ap_const_logic_0 = bytes_plane0_V_V_full_n) and (ap_const_boolean_1 = ap_predicate_op166_write_state8)));
    end process;


    ap_block_state9_pp0_stage5_iter0_assign_proc : process(StrmMPix_V_val_0_V0_status, ap_predicate_op172_read_state9)
    begin
                ap_block_state9_pp0_stage5_iter0 <= ((ap_const_logic_0 = StrmMPix_V_val_0_V0_status) and (ap_const_boolean_1 = ap_predicate_op172_read_state9));
    end process;


    ap_condition_1138_assign_proc : process(ap_CS_fsm_pp0_stage1, ap_enable_reg_pp0_iter0, tmp_13_i_i_reg_1248, ap_block_pp0_stage1_flag00011001)
    begin
                ap_condition_1138 <= ((ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (tmp_13_i_i_reg_1248 = ap_const_lv1_1) and (ap_block_pp0_stage1_flag00011001 = ap_const_boolean_0));
    end process;


    ap_condition_1143_assign_proc : process(ap_enable_reg_pp0_iter0, tmp_13_i_i_reg_1248, ap_CS_fsm_pp0_stage2, ap_block_pp0_stage2_flag00011001)
    begin
                ap_condition_1143 <= ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (tmp_13_i_i_reg_1248 = ap_const_lv1_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_block_pp0_stage2_flag00011001 = ap_const_boolean_0));
    end process;


    ap_condition_1147_assign_proc : process(ap_enable_reg_pp0_iter0, tmp_13_i_i_reg_1248, ap_CS_fsm_pp0_stage3, ap_block_pp0_stage3_flag00011001)
    begin
                ap_condition_1147 <= ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (tmp_13_i_i_reg_1248 = ap_const_lv1_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3) and (ap_block_pp0_stage3_flag00011001 = ap_const_boolean_0));
    end process;


    ap_condition_1151_assign_proc : process(ap_enable_reg_pp0_iter0, tmp_13_i_i_reg_1248, ap_CS_fsm_pp0_stage4, ap_block_pp0_stage4_flag00011001)
    begin
                ap_condition_1151 <= ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (tmp_13_i_i_reg_1248 = ap_const_lv1_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4) and (ap_block_pp0_stage4_flag00011001 = ap_const_boolean_0));
    end process;


    ap_condition_1155_assign_proc : process(ap_enable_reg_pp0_iter0, tmp_13_i_i_reg_1248, ap_CS_fsm_pp0_stage5, ap_block_pp0_stage5_flag00011001)
    begin
                ap_condition_1155 <= ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (tmp_13_i_i_reg_1248 = ap_const_lv1_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_block_pp0_stage5_flag00011001 = ap_const_boolean_0));
    end process;


    ap_condition_1159_assign_proc : process(ap_enable_reg_pp0_iter0, tmp_13_i_i_reg_1248, ap_CS_fsm_pp0_stage6, ap_block_pp0_stage6_flag00011001)
    begin
                ap_condition_1159 <= ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (tmp_13_i_i_reg_1248 = ap_const_lv1_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_block_pp0_stage6_flag00011001 = ap_const_boolean_0));
    end process;


    ap_condition_515_assign_proc : process(ap_enable_reg_pp0_iter0, ap_CS_fsm_pp0_stage7, ap_block_pp0_stage7_flag00011001)
    begin
                ap_condition_515 <= ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_block_pp0_stage7_flag00011001 = ap_const_boolean_0));
    end process;


    ap_condition_549_assign_proc : process(tmp_13_i_i_reg_1248, ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter1, ap_block_pp0_stage0_flag00000000)
    begin
                ap_condition_549 <= ((tmp_13_i_i_reg_1248 = ap_const_lv1_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage0_flag00000000 = ap_const_boolean_0));
    end process;


    ap_condition_pp0_exit_iter0_state5_assign_proc : process(tmp_13_i_i_reg_1248)
    begin
        if ((tmp_13_i_i_reg_1248 = ap_const_lv1_0)) then 
            ap_condition_pp0_exit_iter0_state5 <= ap_const_logic_1;
        else 
            ap_condition_pp0_exit_iter0_state5 <= ap_const_logic_0;
        end if; 
    end process;


    ap_done_assign_proc : process(ap_done_reg, icmp_fu_555_p2, icmp1_fu_577_p2, tmp_i_i_fu_583_p2, icmp2_fu_605_p2, icmp3_fu_627_p2, icmp4_fu_649_p2, exitcond1_i_i_fu_880_p2, ap_CS_fsm_state3)
    begin
        if (((ap_const_logic_1 = ap_CS_fsm_state3) and ((ap_const_lv1_1 = icmp_fu_555_p2) or (ap_const_lv1_1 = icmp1_fu_577_p2) or (ap_const_lv1_1 = tmp_i_i_fu_583_p2) or (ap_const_lv1_1 = icmp2_fu_605_p2) or (ap_const_lv1_1 = icmp3_fu_627_p2) or (ap_const_lv1_0 = icmp4_fu_649_p2) or (ap_const_lv1_1 = exitcond1_i_i_fu_880_p2)))) then 
            ap_done <= ap_const_logic_1;
        else 
            ap_done <= ap_done_reg;
        end if; 
    end process;

    ap_enable_pp0 <= (ap_idle_pp0 xor ap_const_logic_1);

    ap_idle_assign_proc : process(ap_start, ap_CS_fsm_state1)
    begin
        if (((ap_const_logic_0 = ap_start) and (ap_const_logic_1 = ap_CS_fsm_state1))) then 
            ap_idle <= ap_const_logic_1;
        else 
            ap_idle <= ap_const_logic_0;
        end if; 
    end process;


    ap_idle_pp0_assign_proc : process(ap_enable_reg_pp0_iter0, ap_enable_reg_pp0_iter1)
    begin
        if (((ap_const_logic_0 = ap_enable_reg_pp0_iter0) and (ap_const_logic_0 = ap_enable_reg_pp0_iter1))) then 
            ap_idle_pp0 <= ap_const_logic_1;
        else 
            ap_idle_pp0 <= ap_const_logic_0;
        end if; 
    end process;

    ap_phi_precharge_reg_pp0_iter0_pix_val_V_0_8_i_i_reg_480 <= "XXXXXXXX";
    ap_phi_precharge_reg_pp0_iter0_pix_val_V_0_9_i_i_reg_510 <= "XXXXXXXX";
    ap_phi_precharge_reg_pp0_iter0_pix_val_V_1_8_i_i_reg_470 <= "XXXXXXXX";
    ap_phi_precharge_reg_pp0_iter0_pix_val_V_1_9_i_i_reg_500 <= "XXXXXXXX";
    ap_phi_precharge_reg_pp0_iter0_pix_val_V_2_8_i_i_reg_460 <= "XXXXXXXX";
    ap_phi_precharge_reg_pp0_iter0_pix_val_V_2_9_i_i_reg_490 <= "XXXXXXXX";

    ap_predicate_op129_read_state5_assign_proc : process(tmp_13_i_i_reg_1248, or_cond_i_i_reg_1268)
    begin
                ap_predicate_op129_read_state5 <= ((tmp_13_i_i_reg_1248 = ap_const_lv1_1) and (ap_const_lv1_1 = or_cond_i_i_reg_1268));
    end process;


    ap_predicate_op139_read_state6_assign_proc : process(tmp_13_i_i_reg_1248, or_cond_1_i_i_reg_1314)
    begin
                ap_predicate_op139_read_state6 <= ((tmp_13_i_i_reg_1248 = ap_const_lv1_1) and (ap_const_lv1_1 = or_cond_1_i_i_reg_1314));
    end process;


    ap_predicate_op149_read_state7_assign_proc : process(tmp_13_i_i_reg_1248, or_cond_2_i_i_reg_1333)
    begin
                ap_predicate_op149_read_state7 <= ((tmp_13_i_i_reg_1248 = ap_const_lv1_1) and (ap_const_lv1_1 = or_cond_2_i_i_reg_1333));
    end process;


    ap_predicate_op159_read_state8_assign_proc : process(tmp_13_i_i_reg_1248, or_cond_3_i_i_reg_1352)
    begin
                ap_predicate_op159_read_state8 <= ((tmp_13_i_i_reg_1248 = ap_const_lv1_1) and (ap_const_lv1_1 = or_cond_3_i_i_reg_1352));
    end process;


    ap_predicate_op166_write_state8_assign_proc : process(tmp_13_i_i_reg_1248, or_cond1_i_i_reg_1272)
    begin
                ap_predicate_op166_write_state8 <= ((tmp_13_i_i_reg_1248 = ap_const_lv1_1) and (ap_const_lv1_1 = or_cond1_i_i_reg_1272));
    end process;


    ap_predicate_op172_read_state9_assign_proc : process(tmp_13_i_i_reg_1248, or_cond_4_i_i_reg_1371)
    begin
                ap_predicate_op172_read_state9 <= ((tmp_13_i_i_reg_1248 = ap_const_lv1_1) and (ap_const_lv1_1 = or_cond_4_i_i_reg_1371));
    end process;


    ap_predicate_op184_read_state10_assign_proc : process(tmp_13_i_i_reg_1248, or_cond_5_i_i_reg_1390)
    begin
                ap_predicate_op184_read_state10 <= ((tmp_13_i_i_reg_1248 = ap_const_lv1_1) and (ap_const_lv1_1 = or_cond_5_i_i_reg_1390));
    end process;


    ap_predicate_op193_read_state11_assign_proc : process(tmp_13_i_i_reg_1248, or_cond_6_i_i_reg_1394)
    begin
                ap_predicate_op193_read_state11 <= ((tmp_13_i_i_reg_1248 = ap_const_lv1_1) and (ap_const_lv1_1 = or_cond_6_i_i_reg_1394));
    end process;


    ap_predicate_op199_write_state11_assign_proc : process(tmp_13_i_i_reg_1248, or_cond1_1_i_i_reg_1276)
    begin
                ap_predicate_op199_write_state11 <= ((tmp_13_i_i_reg_1248 = ap_const_lv1_1) and (ap_const_lv1_1 = or_cond1_1_i_i_reg_1276));
    end process;


    ap_predicate_op205_read_state12_assign_proc : process(tmp_13_i_i_reg_1248, or_cond_7_i_i_reg_1398)
    begin
                ap_predicate_op205_read_state12 <= ((tmp_13_i_i_reg_1248 = ap_const_lv1_1) and (ap_const_lv1_1 = or_cond_7_i_i_reg_1398));
    end process;


    ap_ready_assign_proc : process(icmp_fu_555_p2, icmp1_fu_577_p2, tmp_i_i_fu_583_p2, icmp2_fu_605_p2, icmp3_fu_627_p2, icmp4_fu_649_p2, exitcond1_i_i_fu_880_p2, ap_CS_fsm_state3)
    begin
        if (((ap_const_logic_1 = ap_CS_fsm_state3) and ((ap_const_lv1_1 = icmp_fu_555_p2) or (ap_const_lv1_1 = icmp1_fu_577_p2) or (ap_const_lv1_1 = tmp_i_i_fu_583_p2) or (ap_const_lv1_1 = icmp2_fu_605_p2) or (ap_const_lv1_1 = icmp3_fu_627_p2) or (ap_const_lv1_0 = icmp4_fu_649_p2) or (ap_const_lv1_1 = exitcond1_i_i_fu_880_p2)))) then 
            ap_ready <= ap_const_logic_1;
        else 
            ap_ready <= ap_const_logic_0;
        end if; 
    end process;


    bytes_plane0_V_V_blk_n_assign_proc : process(bytes_plane0_V_V_full_n, ap_enable_reg_pp0_iter0, tmp_13_i_i_reg_1248, ap_CS_fsm_pp0_stage4, ap_block_pp0_stage4_flag00000000, ap_CS_fsm_pp0_stage7, ap_block_pp0_stage7_flag00000000, ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter1, ap_block_pp0_stage0_flag00000000, or_cond1_i_i_reg_1272, or_cond1_1_i_i_reg_1276, or_cond1_2_i_i_reg_1280)
    begin
        if ((((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (tmp_13_i_i_reg_1248 = ap_const_lv1_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4) and (ap_block_pp0_stage4_flag00000000 = ap_const_boolean_0) and (ap_const_lv1_1 = or_cond1_i_i_reg_1272)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (tmp_13_i_i_reg_1248 = ap_const_lv1_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_block_pp0_stage7_flag00000000 = ap_const_boolean_0) and (ap_const_lv1_1 = or_cond1_1_i_i_reg_1276)) or ((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage0_flag00000000 = ap_const_boolean_0) and (ap_const_lv1_1 = or_cond1_2_i_i_reg_1280)))) then 
            bytes_plane0_V_V_blk_n <= bytes_plane0_V_V_full_n;
        else 
            bytes_plane0_V_V_blk_n <= ap_const_logic_1;
        end if; 
    end process;


    bytes_plane0_V_V_din_assign_proc : process(ap_enable_reg_pp0_iter0, ap_CS_fsm_pp0_stage4, ap_CS_fsm_pp0_stage7, ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter1, or_cond1_2_i_i_reg_1280, ap_predicate_op166_write_state8, ap_predicate_op199_write_state11, tmp_V_fu_956_p9, ap_block_pp0_stage4_flag00001001, tmp_V_1_fu_989_p9, ap_block_pp0_stage7_flag00001001, tmp_V_2_fu_1062_p9, ap_block_pp0_stage0_flag00001001)
    begin
        if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_lv1_1 = or_cond1_2_i_i_reg_1280) and (ap_block_pp0_stage0_flag00001001 = ap_const_boolean_0))) then 
            bytes_plane0_V_V_din <= tmp_V_2_fu_1062_p9;
        elsif (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_const_boolean_1 = ap_predicate_op199_write_state11) and (ap_block_pp0_stage7_flag00001001 = ap_const_boolean_0))) then 
            bytes_plane0_V_V_din <= tmp_V_1_fu_989_p9;
        elsif (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4) and (ap_const_boolean_1 = ap_predicate_op166_write_state8) and (ap_block_pp0_stage4_flag00001001 = ap_const_boolean_0))) then 
            bytes_plane0_V_V_din <= tmp_V_fu_956_p9;
        else 
            bytes_plane0_V_V_din <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
        end if; 
    end process;


    bytes_plane0_V_V_write_assign_proc : process(ap_enable_reg_pp0_iter0, ap_CS_fsm_pp0_stage4, ap_CS_fsm_pp0_stage7, ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter1, or_cond1_2_i_i_reg_1280, ap_block_pp0_stage0_flag00011001, ap_predicate_op166_write_state8, ap_block_pp0_stage4_flag00011001, ap_predicate_op199_write_state11, ap_block_pp0_stage7_flag00011001)
    begin
        if ((((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4) and (ap_const_boolean_1 = ap_predicate_op166_write_state8) and (ap_block_pp0_stage4_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_const_boolean_1 = ap_predicate_op199_write_state11) and (ap_block_pp0_stage7_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_lv1_1 = or_cond1_2_i_i_reg_1280) and (ap_block_pp0_stage0_flag00011001 = ap_const_boolean_0)))) then 
            bytes_plane0_V_V_write <= ap_const_logic_1;
        else 
            bytes_plane0_V_V_write <= ap_const_logic_0;
        end if; 
    end process;

    exitcond1_i_i_fu_880_p2 <= "1" when (y_cast_i_i_fu_876_p1 = tmp_11_cast_i_i_reg_1179) else "0";
    icmp1_fu_577_p2 <= "1" when (tmp_3_fu_567_p4 = ap_const_lv7_0) else "0";
    icmp2_fu_605_p2 <= "1" when (tmp_4_fu_595_p4 = ap_const_lv7_0) else "0";
    icmp3_fu_627_p2 <= "1" when (tmp_5_fu_617_p4 = ap_const_lv7_0) else "0";
    icmp4_fu_649_p2 <= "1" when (tmp_6_fu_639_p4 = ap_const_lv7_0) else "0";
    icmp5_fu_802_p2 <= "0" when (tmp_8_fu_792_p4 = ap_const_lv3_0) else "1";
    icmp6_fu_824_p2 <= "0" when (tmp_9_fu_814_p4 = ap_const_lv2_0) else "1";
    icmp7_fu_864_p2 <= "0" when (tmp_10_fu_854_p4 = ap_const_lv2_0) else "1";
    icmp_fu_555_p2 <= "1" when (tmp_2_fu_545_p4 = ap_const_lv7_0) else "0";
    loopWidth1_cast_i_i_s_fu_665_p4 <= tmp_5_i_i_fu_659_p2(12 downto 3);
    loopWidth_cast_i_i_c_fu_699_p4 <= mul_fu_693_p2(20 downto 12);
    mul_fu_693_p1 <= mul_fu_693_p10(10 - 1 downto 0);
    mul_fu_693_p10 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_6_i_i_reg_1156),22));
    mul_fu_693_p2 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(ap_const_lv22_556) * unsigned(mul_fu_693_p1), 22));
    or_cond1_1_i_i_fu_921_p2 <= (tmp_14_i_i_fu_906_p2 or icmp7_reg_1229);
    or_cond1_2_i_i_fu_926_p2 <= (tmp_14_i_i_fu_906_p2 or tmp_25_2_i_i_reg_1234);
    or_cond1_i_i_fu_916_p2 <= (tmp_14_i_i_fu_906_p2 or tmp_25_i_i_reg_1224);
    or_cond_1_i_i_fu_940_p2 <= (tmp_14_i_i_reg_1257 or icmp5_reg_1194);
    or_cond_2_i_i_fu_944_p2 <= (tmp_14_i_i_reg_1257 or tmp_24_2_i_i_reg_1199);
    or_cond_3_i_i_fu_948_p2 <= (tmp_14_i_i_reg_1257 or icmp6_reg_1204);
    or_cond_4_i_i_fu_952_p2 <= (tmp_14_i_i_reg_1257 or tmp_24_4_i_i_reg_1209);
    or_cond_5_i_i_fu_977_p2 <= (tmp_14_i_i_reg_1257 or tmp_24_5_i_i_reg_1214);
    or_cond_6_i_i_fu_981_p2 <= (tmp_14_i_i_reg_1257 or tmp_24_6_i_i_reg_1219);
    or_cond_7_i_i_fu_985_p2 <= (tmp_14_i_i_reg_1257 or tmp_7_i_i_reg_1174);
    or_cond_i_i_fu_911_p2 <= (tmp_14_i_i_fu_906_p2 or tmp_24_i_i_reg_1189);
    p_shl1_cast_i_i_fu_743_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(p_shl1_i_i_fu_736_p3),9));
    p_shl1_i_i_fu_736_p3 <= (remPix_reg_1161 & ap_const_lv3_0);
    p_shl_cast_i_i_fu_732_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(p_shl_i_i_fu_725_p3),9));
    p_shl_i_i_fu_725_p3 <= (remPix_reg_1161 & ap_const_lv5_0);

    pix_val_V_0_9_i_i_phi_fu_513_p4_assign_proc : process(StrmMPix_V_val_0_V_dout, or_cond_7_i_i_reg_1398, ap_phi_precharge_reg_pp0_iter1_pix_val_V_0_8_i_i_reg_480, ap_phi_precharge_reg_pp0_iter1_pix_val_V_0_9_i_i_reg_510, ap_condition_549)
    begin
        if ((ap_condition_549 = ap_const_boolean_1)) then
            if ((or_cond_7_i_i_reg_1398 = ap_const_lv1_0)) then 
                pix_val_V_0_9_i_i_phi_fu_513_p4 <= ap_phi_precharge_reg_pp0_iter1_pix_val_V_0_8_i_i_reg_480;
            elsif ((ap_const_lv1_1 = or_cond_7_i_i_reg_1398)) then 
                pix_val_V_0_9_i_i_phi_fu_513_p4 <= StrmMPix_V_val_0_V_dout;
            else 
                pix_val_V_0_9_i_i_phi_fu_513_p4 <= ap_phi_precharge_reg_pp0_iter1_pix_val_V_0_9_i_i_reg_510;
            end if;
        else 
            pix_val_V_0_9_i_i_phi_fu_513_p4 <= ap_phi_precharge_reg_pp0_iter1_pix_val_V_0_9_i_i_reg_510;
        end if; 
    end process;


    pix_val_V_1_9_i_i_phi_fu_503_p4_assign_proc : process(StrmMPix_V_val_1_V_dout, or_cond_7_i_i_reg_1398, ap_phi_precharge_reg_pp0_iter1_pix_val_V_1_8_i_i_reg_470, ap_phi_precharge_reg_pp0_iter1_pix_val_V_1_9_i_i_reg_500, ap_condition_549)
    begin
        if ((ap_condition_549 = ap_const_boolean_1)) then
            if ((or_cond_7_i_i_reg_1398 = ap_const_lv1_0)) then 
                pix_val_V_1_9_i_i_phi_fu_503_p4 <= ap_phi_precharge_reg_pp0_iter1_pix_val_V_1_8_i_i_reg_470;
            elsif ((ap_const_lv1_1 = or_cond_7_i_i_reg_1398)) then 
                pix_val_V_1_9_i_i_phi_fu_503_p4 <= StrmMPix_V_val_1_V_dout;
            else 
                pix_val_V_1_9_i_i_phi_fu_503_p4 <= ap_phi_precharge_reg_pp0_iter1_pix_val_V_1_9_i_i_reg_500;
            end if;
        else 
            pix_val_V_1_9_i_i_phi_fu_503_p4 <= ap_phi_precharge_reg_pp0_iter1_pix_val_V_1_9_i_i_reg_500;
        end if; 
    end process;


    pix_val_V_2_9_i_i_phi_fu_493_p4_assign_proc : process(StrmMPix_V_val_2_V_dout, or_cond_7_i_i_reg_1398, ap_phi_precharge_reg_pp0_iter1_pix_val_V_2_8_i_i_reg_460, ap_phi_precharge_reg_pp0_iter1_pix_val_V_2_9_i_i_reg_490, ap_condition_549)
    begin
        if ((ap_condition_549 = ap_const_boolean_1)) then
            if ((or_cond_7_i_i_reg_1398 = ap_const_lv1_0)) then 
                pix_val_V_2_9_i_i_phi_fu_493_p4 <= ap_phi_precharge_reg_pp0_iter1_pix_val_V_2_8_i_i_reg_460;
            elsif ((ap_const_lv1_1 = or_cond_7_i_i_reg_1398)) then 
                pix_val_V_2_9_i_i_phi_fu_493_p4 <= StrmMPix_V_val_2_V_dout;
            else 
                pix_val_V_2_9_i_i_phi_fu_493_p4 <= ap_phi_precharge_reg_pp0_iter1_pix_val_V_2_9_i_i_reg_490;
            end if;
        else 
            pix_val_V_2_9_i_i_phi_fu_493_p4 <= ap_phi_precharge_reg_pp0_iter1_pix_val_V_2_9_i_i_reg_490;
        end if; 
    end process;

    remPix_2_fu_717_p3 <= 
        ap_const_lv4_8 when (tmp_7_i_i_fu_712_p2(0) = '1') else 
        remPix_cast_i_i_fu_709_p1;
    remPix_cast_i_i_fu_709_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(remPix_reg_1161),4));
    remPix_fu_681_p1 <= HwReg_width_cast9_loc_dout(3 - 1 downto 0);
    remainTrx_fu_769_p3 <= 
        ap_const_lv3_3 when (tmp_7_i_i_fu_712_p2(0) = '1') else 
        tmp_10_cast_i_i_fu_759_p4;
    tmp_10_cast_i_i_fu_759_p4 <= tmp_9_i_i_fu_753_p2(8 downto 6);
    tmp_10_fu_854_p4 <= remainTrx_fu_769_p3(2 downto 1);
    tmp_11_cast_i_i_fu_777_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(HwReg_height_cast8_l_reg_1103),17));
    tmp_12_i_i_fu_780_p2 <= std_logic_vector(signed(ap_const_lv9_1FF) + signed(loopWidth_cast_i_i_c_fu_699_p4));
    tmp_13_i_i_fu_895_p2 <= "1" when (signed(x_cast_i_i_cast_fu_891_p1) < signed(loopWidth_cast_i_i_c_reg_1169)) else "0";
    tmp_14_i_i_fu_906_p2 <= "1" when (signed(x_cast_i_i_cast_fu_891_p1) < signed(tmp_12_i_i_reg_1184)) else "0";
    tmp_24_2_i_i_fu_808_p2 <= "1" when (unsigned(remPix_2_fu_717_p3) > unsigned(ap_const_lv4_2)) else "0";
    tmp_24_4_i_i_fu_830_p2 <= "1" when (unsigned(remPix_2_fu_717_p3) > unsigned(ap_const_lv4_4)) else "0";
    tmp_24_5_i_i_fu_836_p2 <= "1" when (unsigned(remPix_2_fu_717_p3) > unsigned(ap_const_lv4_5)) else "0";
    tmp_24_6_i_i_fu_842_p2 <= "1" when (unsigned(remPix_2_fu_717_p3) > unsigned(ap_const_lv4_6)) else "0";
    tmp_24_i_i_fu_786_p2 <= "0" when (remPix_2_fu_717_p3 = ap_const_lv4_0) else "1";
    tmp_25_2_i_i_fu_870_p2 <= "1" when (unsigned(remainTrx_fu_769_p3) > unsigned(ap_const_lv3_2)) else "0";
    tmp_25_i_i_fu_848_p2 <= "0" when (remainTrx_fu_769_p3 = ap_const_lv3_0) else "1";
    tmp_2_fu_545_p4 <= VideoFormat_off_i_i_fu_539_p2(7 downto 1);
    tmp_3_fu_567_p4 <= VideoFormat_off1_i_i_fu_561_p2(7 downto 1);

    tmp_3_loc_blk_n_assign_proc : process(ap_start, ap_done_reg, ap_CS_fsm_state1, tmp_3_loc_empty_n)
    begin
        if (((ap_const_logic_1 = ap_CS_fsm_state1) and not(((ap_const_logic_0 = ap_start) or (ap_done_reg = ap_const_logic_1))))) then 
            tmp_3_loc_blk_n <= tmp_3_loc_empty_n;
        else 
            tmp_3_loc_blk_n <= ap_const_logic_1;
        end if; 
    end process;


    tmp_3_loc_out_blk_n_assign_proc : process(ap_start, ap_done_reg, ap_CS_fsm_state1, tmp_3_loc_out_full_n)
    begin
        if (((ap_const_logic_1 = ap_CS_fsm_state1) and not(((ap_const_logic_0 = ap_start) or (ap_done_reg = ap_const_logic_1))))) then 
            tmp_3_loc_out_blk_n <= tmp_3_loc_out_full_n;
        else 
            tmp_3_loc_out_blk_n <= ap_const_logic_1;
        end if; 
    end process;

    tmp_3_loc_out_din <= tmp_3_loc_dout;

    tmp_3_loc_out_write_assign_proc : process(ap_start, ap_done_reg, ap_CS_fsm_state1, HwReg_height_cast8_loc_empty_n, HwReg_width_cast9_loc_empty_n, tmp_3_loc_empty_n, HwReg_height_cast8_loc_out_full_n, tmp_3_loc_out_full_n)
    begin
        if (((ap_const_logic_1 = ap_CS_fsm_state1) and not(((ap_const_logic_0 = ap_start) or (ap_done_reg = ap_const_logic_1) or (ap_const_logic_0 = HwReg_height_cast8_loc_empty_n) or (ap_const_logic_0 = tmp_3_loc_empty_n) or (ap_const_logic_0 = HwReg_height_cast8_loc_out_full_n) or (ap_const_logic_0 = tmp_3_loc_out_full_n) or (ap_const_logic_0 = HwReg_width_cast9_loc_empty_n))))) then 
            tmp_3_loc_out_write <= ap_const_logic_1;
        else 
            tmp_3_loc_out_write <= ap_const_logic_0;
        end if; 
    end process;


    tmp_3_loc_read_assign_proc : process(ap_start, ap_done_reg, ap_CS_fsm_state1, HwReg_height_cast8_loc_empty_n, HwReg_width_cast9_loc_empty_n, tmp_3_loc_empty_n, HwReg_height_cast8_loc_out_full_n, tmp_3_loc_out_full_n)
    begin
        if (((ap_const_logic_1 = ap_CS_fsm_state1) and not(((ap_const_logic_0 = ap_start) or (ap_done_reg = ap_const_logic_1) or (ap_const_logic_0 = HwReg_height_cast8_loc_empty_n) or (ap_const_logic_0 = tmp_3_loc_empty_n) or (ap_const_logic_0 = HwReg_height_cast8_loc_out_full_n) or (ap_const_logic_0 = tmp_3_loc_out_full_n) or (ap_const_logic_0 = HwReg_width_cast9_loc_empty_n))))) then 
            tmp_3_loc_read <= ap_const_logic_1;
        else 
            tmp_3_loc_read <= ap_const_logic_0;
        end if; 
    end process;

    tmp_4_fu_595_p4 <= VideoFormat_off2_i_i_fu_589_p2(7 downto 1);
    tmp_5_fu_617_p4 <= VideoFormat_off3_i_i_fu_611_p2(7 downto 1);
    tmp_5_i_i_fu_659_p2 <= std_logic_vector(unsigned(ap_const_lv13_7) + unsigned(tmp_cast_i_i_cast_fu_655_p1));
    tmp_6_fu_639_p4 <= VideoFormat_off4_i_i_fu_633_p2(7 downto 1);
    tmp_6_i_i_fu_675_p2 <= std_logic_vector(unsigned(ap_const_lv10_2) + unsigned(loopWidth1_cast_i_i_s_fu_665_p4));
    tmp_7_i_i_fu_712_p2 <= "1" when (remPix_reg_1161 = ap_const_lv3_0) else "0";
    tmp_8_fu_792_p4 <= remPix_2_fu_717_p3(3 downto 1);
    tmp_8_i_i_fu_747_p2 <= std_logic_vector(unsigned(p_shl_cast_i_i_fu_732_p1) - unsigned(p_shl1_cast_i_i_fu_743_p1));
    tmp_9_fu_814_p4 <= remPix_2_fu_717_p3(3 downto 2);
    tmp_9_i_i_fu_753_p2 <= std_logic_vector(unsigned(ap_const_lv9_3F) + unsigned(tmp_8_i_i_fu_747_p2));
    tmp_V_1_fu_989_p9 <= (((((((ap_phi_precharge_reg_pp0_iter0_pix_val_V_0_7_i_i_reg_449 & pix_val_V_2_6_i_i_reg_394) & pix_val_V_1_6_i_i_reg_405) & pix_val_V_0_6_i_i_reg_416) & pix_val_V_2_5_i_i_reg_361) & pix_val_V_1_5_i_i_reg_372) & pix_val_V_0_5_i_i_reg_383) & pix_val_V_2_4_i_i_reg_328);
    tmp_V_2_fu_1062_p9 <= (((((((pix_val_V_2_9_i_i_phi_fu_493_p4 & pix_val_V_1_9_i_i_phi_fu_503_p4) & pix_val_V_0_9_i_i_phi_fu_513_p4) & ap_phi_precharge_reg_pp0_iter1_pix_val_V_2_8_i_i_reg_460) & ap_phi_precharge_reg_pp0_iter1_pix_val_V_1_8_i_i_reg_470) & ap_phi_precharge_reg_pp0_iter1_pix_val_V_0_8_i_i_reg_480) & pix_val_V_2_7_i_i_reg_427) & pix_val_V_1_7_i_i_reg_438);
    tmp_V_fu_956_p9 <= (((((((ap_phi_precharge_reg_pp0_iter0_pix_val_V_1_4_i_i_reg_339 & ap_phi_precharge_reg_pp0_iter0_pix_val_V_0_4_i_i_reg_350) & pix_val_V_2_3_i_i_reg_295) & pix_val_V_1_3_i_i_reg_306) & pix_val_V_0_3_i_i_reg_317) & pix_val_V_2_2_i_i_reg_265) & pix_val_V_1_2_i_i_reg_275) & pix_val_V_0_2_i_i_reg_285);
    tmp_cast_i_i_cast_fu_655_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_3_loc_dout),13));
    tmp_fu_535_p1 <= HwReg_video_format(8 - 1 downto 0);
    tmp_i_i_fu_583_p2 <= "1" when (tmp_fu_535_p1 = ap_const_lv8_C) else "0";
    x_cast_i_i_cast_fu_891_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(x_i_i_phi_fu_258_p4),9));
    x_fu_900_p2 <= std_logic_vector(unsigned(x_i_i_phi_fu_258_p4) + unsigned(ap_const_lv8_1));

    x_i_i_phi_fu_258_p4_assign_proc : process(tmp_13_i_i_reg_1248, ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter1, ap_block_pp0_stage0_flag00000000, x_i_i_reg_254, x_reg_1252)
    begin
        if (((tmp_13_i_i_reg_1248 = ap_const_lv1_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage0_flag00000000 = ap_const_boolean_0))) then 
            x_i_i_phi_fu_258_p4 <= x_reg_1252;
        else 
            x_i_i_phi_fu_258_p4 <= x_i_i_reg_254;
        end if; 
    end process;

    y_cast_i_i_fu_876_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(y_i_i_reg_243),17));
    y_fu_885_p2 <= std_logic_vector(unsigned(y_i_i_reg_243) + unsigned(ap_const_lv16_1));
end behav;
