// ==============================================================
// RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2017.2
// Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved.
// 
// ===========================================================

`timescale 1 ns / 1 ps 

module design_1_v_frmbuf_rd_0_0_v_frmbuf_rd_entry4 (
        ap_clk,
        ap_rst,
        ap_start,
        ap_done,
        ap_continue,
        ap_idle,
        ap_ready,
        HwReg_frm_buffer_V,
        HwReg_frm_buffer_V_out_din,
        HwReg_frm_buffer_V_out_full_n,
        HwReg_frm_buffer_V_out_write
);

parameter    ap_ST_fsm_state1 = 1'd1;

input   ap_clk;
input   ap_rst;
input   ap_start;
output   ap_done;
input   ap_continue;
output   ap_idle;
output   ap_ready;
input  [31:0] HwReg_frm_buffer_V;
output  [31:0] HwReg_frm_buffer_V_out_din;
input   HwReg_frm_buffer_V_out_full_n;
output   HwReg_frm_buffer_V_out_write;

reg ap_done;
reg ap_idle;
reg ap_ready;
reg HwReg_frm_buffer_V_out_write;

reg    ap_done_reg;
(* fsm_encoding = "none" *) reg   [0:0] ap_CS_fsm;
wire    ap_CS_fsm_state1;
reg    HwReg_frm_buffer_V_out_blk_n;
reg    ap_block_state1;
reg   [0:0] ap_NS_fsm;

// power-on initialization
initial begin
#0 ap_done_reg = 1'b0;
#0 ap_CS_fsm = 1'd1;
end

always @ (posedge ap_clk) begin
    if (ap_rst == 1'b1) begin
        ap_CS_fsm <= ap_ST_fsm_state1;
    end else begin
        ap_CS_fsm <= ap_NS_fsm;
    end
end

always @ (posedge ap_clk) begin
    if (ap_rst == 1'b1) begin
        ap_done_reg <= 1'b0;
    end else begin
        if ((1'b1 == ap_continue)) begin
            ap_done_reg <= 1'b0;
        end else if (((1'b1 == ap_CS_fsm_state1) & ~((1'b0 == ap_start) | (1'b0 == HwReg_frm_buffer_V_out_full_n) | (ap_done_reg == 1'b1)))) begin
            ap_done_reg <= 1'b1;
        end
    end
end

always @ (*) begin
    if ((1'b1 == ap_CS_fsm_state1)) begin
        HwReg_frm_buffer_V_out_blk_n = HwReg_frm_buffer_V_out_full_n;
    end else begin
        HwReg_frm_buffer_V_out_blk_n = 1'b1;
    end
end

always @ (*) begin
    if (((1'b1 == ap_CS_fsm_state1) & ~((1'b0 == ap_start) | (1'b0 == HwReg_frm_buffer_V_out_full_n) | (ap_done_reg == 1'b1)))) begin
        HwReg_frm_buffer_V_out_write = 1'b1;
    end else begin
        HwReg_frm_buffer_V_out_write = 1'b0;
    end
end

always @ (*) begin
    if (((1'b1 == ap_CS_fsm_state1) & ~((1'b0 == ap_start) | (1'b0 == HwReg_frm_buffer_V_out_full_n) | (ap_done_reg == 1'b1)))) begin
        ap_done = 1'b1;
    end else begin
        ap_done = ap_done_reg;
    end
end

always @ (*) begin
    if (((1'b0 == ap_start) & (1'b1 == ap_CS_fsm_state1))) begin
        ap_idle = 1'b1;
    end else begin
        ap_idle = 1'b0;
    end
end

always @ (*) begin
    if (((1'b1 == ap_CS_fsm_state1) & ~((1'b0 == ap_start) | (1'b0 == HwReg_frm_buffer_V_out_full_n) | (ap_done_reg == 1'b1)))) begin
        ap_ready = 1'b1;
    end else begin
        ap_ready = 1'b0;
    end
end

always @ (*) begin
    case (ap_CS_fsm)
        ap_ST_fsm_state1 : begin
            ap_NS_fsm = ap_ST_fsm_state1;
        end
        default : begin
            ap_NS_fsm = 'bx;
        end
    endcase
end

assign HwReg_frm_buffer_V_out_din = HwReg_frm_buffer_V;

assign ap_CS_fsm_state1 = ap_CS_fsm[32'd0];

always @ (*) begin
    ap_block_state1 = ((1'b0 == ap_start) | (1'b0 == HwReg_frm_buffer_V_out_full_n) | (ap_done_reg == 1'b1));
end

endmodule //design_1_v_frmbuf_rd_0_0_v_frmbuf_rd_entry4
