-- ==============================================================
-- RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2017.2
-- Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved.
-- 
-- ===========================================================

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;

entity AXIvideo2Mat is
port (
    ap_clk : IN STD_LOGIC;
    ap_rst : IN STD_LOGIC;
    ap_start : IN STD_LOGIC;
    start_full_n : IN STD_LOGIC;
    ap_ready : OUT STD_LOGIC;
    ap_done : OUT STD_LOGIC;
    ap_continue : IN STD_LOGIC;
    ap_idle : OUT STD_LOGIC;
    start_out : OUT STD_LOGIC;
    start_write : OUT STD_LOGIC;
    video_in_TDATA : IN STD_LOGIC_VECTOR (23 downto 0);
    video_in_TVALID : IN STD_LOGIC;
    video_in_TREADY : OUT STD_LOGIC;
    video_in_TKEEP : IN STD_LOGIC_VECTOR (2 downto 0);
    video_in_TSTRB : IN STD_LOGIC_VECTOR (2 downto 0);
    video_in_TUSER : IN STD_LOGIC_VECTOR (0 downto 0);
    video_in_TLAST : IN STD_LOGIC_VECTOR (0 downto 0);
    video_in_TID : IN STD_LOGIC_VECTOR (0 downto 0);
    video_in_TDEST : IN STD_LOGIC_VECTOR (0 downto 0);
    img_rows_V_dout : IN STD_LOGIC_VECTOR (9 downto 0);
    img_rows_V_empty_n : IN STD_LOGIC;
    img_rows_V_read : OUT STD_LOGIC;
    img_cols_V_dout : IN STD_LOGIC_VECTOR (10 downto 0);
    img_cols_V_empty_n : IN STD_LOGIC;
    img_cols_V_read : OUT STD_LOGIC;
    img_data_stream_0_V_din : OUT STD_LOGIC_VECTOR (7 downto 0);
    img_data_stream_0_V_full_n : IN STD_LOGIC;
    img_data_stream_0_V_write : OUT STD_LOGIC;
    img_data_stream_1_V_din : OUT STD_LOGIC_VECTOR (7 downto 0);
    img_data_stream_1_V_full_n : IN STD_LOGIC;
    img_data_stream_1_V_write : OUT STD_LOGIC;
    img_data_stream_2_V_din : OUT STD_LOGIC_VECTOR (7 downto 0);
    img_data_stream_2_V_full_n : IN STD_LOGIC;
    img_data_stream_2_V_write : OUT STD_LOGIC;
    img_rows_V_out_din : OUT STD_LOGIC_VECTOR (9 downto 0);
    img_rows_V_out_full_n : IN STD_LOGIC;
    img_rows_V_out_write : OUT STD_LOGIC;
    img_cols_V_out_din : OUT STD_LOGIC_VECTOR (10 downto 0);
    img_cols_V_out_full_n : IN STD_LOGIC;
    img_cols_V_out_write : OUT STD_LOGIC );
end;


architecture behav of AXIvideo2Mat is 
    constant ap_const_logic_1 : STD_LOGIC := '1';
    constant ap_const_logic_0 : STD_LOGIC := '0';
    constant ap_ST_fsm_state1 : STD_LOGIC_VECTOR (7 downto 0) := "00000001";
    constant ap_ST_fsm_state2 : STD_LOGIC_VECTOR (7 downto 0) := "00000010";
    constant ap_ST_fsm_state3 : STD_LOGIC_VECTOR (7 downto 0) := "00000100";
    constant ap_ST_fsm_state4 : STD_LOGIC_VECTOR (7 downto 0) := "00001000";
    constant ap_ST_fsm_pp1_stage0 : STD_LOGIC_VECTOR (7 downto 0) := "00010000";
    constant ap_ST_fsm_state7 : STD_LOGIC_VECTOR (7 downto 0) := "00100000";
    constant ap_ST_fsm_pp2_stage0 : STD_LOGIC_VECTOR (7 downto 0) := "01000000";
    constant ap_ST_fsm_state10 : STD_LOGIC_VECTOR (7 downto 0) := "10000000";
    constant ap_const_boolean_1 : BOOLEAN := true;
    constant ap_const_lv32_0 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000000";
    constant ap_const_lv1_0 : STD_LOGIC_VECTOR (0 downto 0) := "0";
    constant ap_const_lv1_1 : STD_LOGIC_VECTOR (0 downto 0) := "1";
    constant ap_const_lv2_0 : STD_LOGIC_VECTOR (1 downto 0) := "00";
    constant ap_const_lv2_2 : STD_LOGIC_VECTOR (1 downto 0) := "10";
    constant ap_const_lv2_3 : STD_LOGIC_VECTOR (1 downto 0) := "11";
    constant ap_const_lv2_1 : STD_LOGIC_VECTOR (1 downto 0) := "01";
    constant ap_const_lv32_1 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000001";
    constant ap_const_lv32_4 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000100";
    constant ap_const_boolean_0 : BOOLEAN := false;
    constant ap_const_lv32_6 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000110";
    constant ap_const_lv32_3 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000011";
    constant ap_const_lv32_5 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000101";
    constant ap_const_lv32_7 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000111";
    constant ap_const_lv32_2 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000010";
    constant ap_const_lv9_0 : STD_LOGIC_VECTOR (8 downto 0) := "000000000";
    constant ap_const_lv10_0 : STD_LOGIC_VECTOR (9 downto 0) := "0000000000";
    constant ap_const_lv9_1 : STD_LOGIC_VECTOR (8 downto 0) := "000000001";
    constant ap_const_lv10_1 : STD_LOGIC_VECTOR (9 downto 0) := "0000000001";
    constant ap_const_lv32_8 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001000";
    constant ap_const_lv32_F : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001111";
    constant ap_const_lv32_10 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000010000";
    constant ap_const_lv32_17 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000010111";

    signal real_start : STD_LOGIC;
    signal real_start_status_reg : STD_LOGIC := '0';
    signal internal_ap_ready : STD_LOGIC;
    signal ap_done_reg : STD_LOGIC := '0';
    signal ap_CS_fsm : STD_LOGIC_VECTOR (7 downto 0) := "00000001";
    attribute fsm_encoding : string;
    attribute fsm_encoding of ap_CS_fsm : signal is "none";
    signal ap_CS_fsm_state1 : STD_LOGIC;
    attribute fsm_encoding of ap_CS_fsm_state1 : signal is "none";
    signal start_once_reg : STD_LOGIC := '0';
    signal start_control_reg : STD_LOGIC := '0';
    signal AXI_video_strm_V_data_V_0_data_out : STD_LOGIC_VECTOR (23 downto 0);
    signal AXI_video_strm_V_data_V_0_vld_in : STD_LOGIC;
    signal AXI_video_strm_V_data_V_0_vld_out : STD_LOGIC;
    signal AXI_video_strm_V_data_V_0_ack_in : STD_LOGIC;
    signal AXI_video_strm_V_data_V_0_ack_out : STD_LOGIC;
    signal AXI_video_strm_V_data_V_0_payload_A : STD_LOGIC_VECTOR (23 downto 0);
    signal AXI_video_strm_V_data_V_0_payload_B : STD_LOGIC_VECTOR (23 downto 0);
    signal AXI_video_strm_V_data_V_0_sel_rd : STD_LOGIC := '0';
    signal AXI_video_strm_V_data_V_0_sel_wr : STD_LOGIC := '0';
    signal AXI_video_strm_V_data_V_0_sel : STD_LOGIC;
    signal AXI_video_strm_V_data_V_0_load_A : STD_LOGIC;
    signal AXI_video_strm_V_data_V_0_load_B : STD_LOGIC;
    signal AXI_video_strm_V_data_V_0_state : STD_LOGIC_VECTOR (1 downto 0) := "00";
    signal AXI_video_strm_V_data_V_0_state_cmp_full : STD_LOGIC;
    signal AXI_video_strm_V_user_V_0_data_out : STD_LOGIC_VECTOR (0 downto 0);
    signal AXI_video_strm_V_user_V_0_vld_in : STD_LOGIC;
    signal AXI_video_strm_V_user_V_0_vld_out : STD_LOGIC;
    signal AXI_video_strm_V_user_V_0_ack_in : STD_LOGIC;
    signal AXI_video_strm_V_user_V_0_ack_out : STD_LOGIC;
    signal AXI_video_strm_V_user_V_0_payload_A : STD_LOGIC_VECTOR (0 downto 0);
    signal AXI_video_strm_V_user_V_0_payload_B : STD_LOGIC_VECTOR (0 downto 0);
    signal AXI_video_strm_V_user_V_0_sel_rd : STD_LOGIC := '0';
    signal AXI_video_strm_V_user_V_0_sel_wr : STD_LOGIC := '0';
    signal AXI_video_strm_V_user_V_0_sel : STD_LOGIC;
    signal AXI_video_strm_V_user_V_0_load_A : STD_LOGIC;
    signal AXI_video_strm_V_user_V_0_load_B : STD_LOGIC;
    signal AXI_video_strm_V_user_V_0_state : STD_LOGIC_VECTOR (1 downto 0) := "00";
    signal AXI_video_strm_V_user_V_0_state_cmp_full : STD_LOGIC;
    signal AXI_video_strm_V_last_V_0_data_out : STD_LOGIC_VECTOR (0 downto 0);
    signal AXI_video_strm_V_last_V_0_vld_in : STD_LOGIC;
    signal AXI_video_strm_V_last_V_0_vld_out : STD_LOGIC;
    signal AXI_video_strm_V_last_V_0_ack_in : STD_LOGIC;
    signal AXI_video_strm_V_last_V_0_ack_out : STD_LOGIC;
    signal AXI_video_strm_V_last_V_0_payload_A : STD_LOGIC_VECTOR (0 downto 0);
    signal AXI_video_strm_V_last_V_0_payload_B : STD_LOGIC_VECTOR (0 downto 0);
    signal AXI_video_strm_V_last_V_0_sel_rd : STD_LOGIC := '0';
    signal AXI_video_strm_V_last_V_0_sel_wr : STD_LOGIC := '0';
    signal AXI_video_strm_V_last_V_0_sel : STD_LOGIC;
    signal AXI_video_strm_V_last_V_0_load_A : STD_LOGIC;
    signal AXI_video_strm_V_last_V_0_load_B : STD_LOGIC;
    signal AXI_video_strm_V_last_V_0_state : STD_LOGIC_VECTOR (1 downto 0) := "00";
    signal AXI_video_strm_V_last_V_0_state_cmp_full : STD_LOGIC;
    signal AXI_video_strm_V_dest_V_0_vld_in : STD_LOGIC;
    signal AXI_video_strm_V_dest_V_0_ack_out : STD_LOGIC;
    signal AXI_video_strm_V_dest_V_0_state : STD_LOGIC_VECTOR (1 downto 0) := "00";
    signal video_in_TDATA_blk_n : STD_LOGIC;
    signal ap_CS_fsm_state2 : STD_LOGIC;
    attribute fsm_encoding of ap_CS_fsm_state2 : signal is "none";
    signal ap_CS_fsm_pp1_stage0 : STD_LOGIC;
    attribute fsm_encoding of ap_CS_fsm_pp1_stage0 : signal is "none";
    signal ap_enable_reg_pp1_iter1 : STD_LOGIC := '0';
    signal ap_block_pp1_stage0_flag00000000 : BOOLEAN;
    signal exitcond_i_reg_446 : STD_LOGIC_VECTOR (0 downto 0);
    signal brmerge_i_reg_455 : STD_LOGIC_VECTOR (0 downto 0);
    signal ap_CS_fsm_pp2_stage0 : STD_LOGIC;
    attribute fsm_encoding of ap_CS_fsm_pp2_stage0 : signal is "none";
    signal ap_enable_reg_pp2_iter1 : STD_LOGIC := '0';
    signal ap_block_pp2_stage0_flag00000000 : BOOLEAN;
    signal eol_2_i_reg_282 : STD_LOGIC_VECTOR (0 downto 0);
    signal img_rows_V_blk_n : STD_LOGIC;
    signal img_cols_V_blk_n : STD_LOGIC;
    signal img_data_stream_0_V_blk_n : STD_LOGIC;
    signal img_data_stream_1_V_blk_n : STD_LOGIC;
    signal img_data_stream_2_V_blk_n : STD_LOGIC;
    signal img_rows_V_out_blk_n : STD_LOGIC;
    signal img_cols_V_out_blk_n : STD_LOGIC;
    signal t_V_6_reg_212 : STD_LOGIC_VECTOR (9 downto 0);
    signal eol_i_reg_223 : STD_LOGIC_VECTOR (0 downto 0);
    signal eol_reg_235 : STD_LOGIC_VECTOR (0 downto 0);
    signal axi_data_V_1_i_reg_246 : STD_LOGIC_VECTOR (23 downto 0);
    signal axi_last_V_3_i_reg_293 : STD_LOGIC_VECTOR (0 downto 0);
    signal axi_data_V_3_i_reg_305 : STD_LOGIC_VECTOR (23 downto 0);
    signal img_rows_V_read_reg_407 : STD_LOGIC_VECTOR (9 downto 0);
    signal ap_block_state1 : BOOLEAN;
    signal img_cols_V_read_reg_412 : STD_LOGIC_VECTOR (10 downto 0);
    signal tmp_data_V_reg_417 : STD_LOGIC_VECTOR (23 downto 0);
    signal tmp_last_V_reg_425 : STD_LOGIC_VECTOR (0 downto 0);
    signal exitcond7_i_fu_340_p2 : STD_LOGIC_VECTOR (0 downto 0);
    signal ap_CS_fsm_state4 : STD_LOGIC;
    attribute fsm_encoding of ap_CS_fsm_state4 : signal is "none";
    signal i_V_fu_345_p2 : STD_LOGIC_VECTOR (8 downto 0);
    signal i_V_reg_441 : STD_LOGIC_VECTOR (8 downto 0);
    signal exitcond_i_fu_355_p2 : STD_LOGIC_VECTOR (0 downto 0);
    signal ap_block_state5_pp1_stage0_iter0 : BOOLEAN;
    signal ap_predicate_op73_read_state6 : BOOLEAN;
    signal ap_block_state6_pp1_stage0_iter1 : BOOLEAN;
    signal ap_block_pp1_stage0_flag00011001 : BOOLEAN;
    signal j_V_fu_360_p2 : STD_LOGIC_VECTOR (9 downto 0);
    signal ap_enable_reg_pp1_iter0 : STD_LOGIC := '0';
    signal brmerge_i_fu_369_p2 : STD_LOGIC_VECTOR (0 downto 0);
    signal ap_block_state8_pp2_stage0_iter0 : BOOLEAN;
    signal ap_block_state9_pp2_stage0_iter1 : BOOLEAN;
    signal ap_block_pp2_stage0_flag00011001 : BOOLEAN;
    signal ap_block_pp1_stage0_flag00011011 : BOOLEAN;
    signal ap_enable_reg_pp2_iter0 : STD_LOGIC := '0';
    signal ap_CS_fsm_state7 : STD_LOGIC;
    attribute fsm_encoding of ap_CS_fsm_state7 : signal is "none";
    signal ap_block_pp2_stage0_flag00011011 : BOOLEAN;
    signal eol_2_i_phi_fu_285_p4 : STD_LOGIC_VECTOR (0 downto 0);
    signal axi_last_V1_i_reg_181 : STD_LOGIC_VECTOR (0 downto 0);
    signal ap_CS_fsm_state10 : STD_LOGIC;
    attribute fsm_encoding of ap_CS_fsm_state10 : signal is "none";
    signal ap_CS_fsm_state3 : STD_LOGIC;
    attribute fsm_encoding of ap_CS_fsm_state3 : signal is "none";
    signal axi_data_V1_i_reg_191 : STD_LOGIC_VECTOR (23 downto 0);
    signal t_V_reg_201 : STD_LOGIC_VECTOR (8 downto 0);
    signal eol_i_phi_fu_227_p4 : STD_LOGIC_VECTOR (0 downto 0);
    signal axi_last_V_2_i_phi_fu_262_p4 : STD_LOGIC_VECTOR (0 downto 0);
    signal p_Val2_s_phi_fu_274_p4 : STD_LOGIC_VECTOR (23 downto 0);
    signal ap_phi_precharge_reg_pp1_iter1_axi_last_V_2_i_reg_257 : STD_LOGIC_VECTOR (0 downto 0);
    signal ap_phi_precharge_reg_pp1_iter1_p_Val2_s_reg_270 : STD_LOGIC_VECTOR (23 downto 0);
    signal ap_block_pp1_stage0_flag00001001 : BOOLEAN;
    signal sof_1_i_fu_110 : STD_LOGIC_VECTOR (0 downto 0);
    signal t_V_cast_cast_i_fu_336_p1 : STD_LOGIC_VECTOR (9 downto 0);
    signal t_V_6_cast_cast_i_fu_351_p1 : STD_LOGIC_VECTOR (10 downto 0);
    signal tmp_user_V_fu_327_p1 : STD_LOGIC_VECTOR (0 downto 0);
    signal ap_NS_fsm : STD_LOGIC_VECTOR (7 downto 0);
    signal ap_idle_pp1 : STD_LOGIC;
    signal ap_enable_pp1 : STD_LOGIC;
    signal ap_idle_pp2 : STD_LOGIC;
    signal ap_enable_pp2 : STD_LOGIC;
    signal ap_condition_535 : BOOLEAN;


begin




    AXI_video_strm_V_data_V_0_sel_rd_assign_proc : process(ap_clk)
    begin
        if (ap_clk'event and ap_clk =  '1') then
            if (ap_rst = '1') then
                AXI_video_strm_V_data_V_0_sel_rd <= ap_const_logic_0;
            else
                if (((ap_const_logic_1 = AXI_video_strm_V_data_V_0_ack_out) and (ap_const_logic_1 = AXI_video_strm_V_data_V_0_vld_out))) then 
                                        AXI_video_strm_V_data_V_0_sel_rd <= not(AXI_video_strm_V_data_V_0_sel_rd);
                end if; 
            end if;
        end if;
    end process;


    AXI_video_strm_V_data_V_0_sel_wr_assign_proc : process(ap_clk)
    begin
        if (ap_clk'event and ap_clk =  '1') then
            if (ap_rst = '1') then
                AXI_video_strm_V_data_V_0_sel_wr <= ap_const_logic_0;
            else
                if (((ap_const_logic_1 = AXI_video_strm_V_data_V_0_vld_in) and (ap_const_logic_1 = AXI_video_strm_V_data_V_0_ack_in))) then 
                                        AXI_video_strm_V_data_V_0_sel_wr <= not(AXI_video_strm_V_data_V_0_sel_wr);
                end if; 
            end if;
        end if;
    end process;


    AXI_video_strm_V_data_V_0_state_assign_proc : process(ap_clk)
    begin
        if (ap_clk'event and ap_clk =  '1') then
            if (ap_rst = '1') then
                AXI_video_strm_V_data_V_0_state <= ap_const_lv2_0;
            else
                if ((((ap_const_logic_0 = AXI_video_strm_V_data_V_0_vld_in) and (ap_const_logic_1 = AXI_video_strm_V_data_V_0_ack_out) and (AXI_video_strm_V_data_V_0_state = ap_const_lv2_3)) or ((ap_const_logic_0 = AXI_video_strm_V_data_V_0_vld_in) and (AXI_video_strm_V_data_V_0_state = ap_const_lv2_2)))) then 
                    AXI_video_strm_V_data_V_0_state <= ap_const_lv2_2;
                elsif ((((ap_const_logic_1 = AXI_video_strm_V_data_V_0_vld_in) and (ap_const_logic_0 = AXI_video_strm_V_data_V_0_ack_out) and (AXI_video_strm_V_data_V_0_state = ap_const_lv2_3)) or ((ap_const_logic_0 = AXI_video_strm_V_data_V_0_ack_out) and (AXI_video_strm_V_data_V_0_state = ap_const_lv2_1)))) then 
                    AXI_video_strm_V_data_V_0_state <= ap_const_lv2_1;
                elsif ((((ap_const_logic_1 = AXI_video_strm_V_data_V_0_vld_in) and (AXI_video_strm_V_data_V_0_state = ap_const_lv2_2)) or ((ap_const_logic_1 = AXI_video_strm_V_data_V_0_ack_out) and (AXI_video_strm_V_data_V_0_state = ap_const_lv2_1)) or ((AXI_video_strm_V_data_V_0_state = ap_const_lv2_3) and not(((ap_const_logic_1 = AXI_video_strm_V_data_V_0_vld_in) and (ap_const_logic_0 = AXI_video_strm_V_data_V_0_ack_out))) and not(((ap_const_logic_0 = AXI_video_strm_V_data_V_0_vld_in) and (ap_const_logic_1 = AXI_video_strm_V_data_V_0_ack_out)))))) then 
                    AXI_video_strm_V_data_V_0_state <= ap_const_lv2_3;
                else 
                    AXI_video_strm_V_data_V_0_state <= ap_const_lv2_2;
                end if; 
            end if;
        end if;
    end process;


    AXI_video_strm_V_dest_V_0_state_assign_proc : process(ap_clk)
    begin
        if (ap_clk'event and ap_clk =  '1') then
            if (ap_rst = '1') then
                AXI_video_strm_V_dest_V_0_state <= ap_const_lv2_0;
            else
                if ((((ap_const_logic_0 = AXI_video_strm_V_dest_V_0_vld_in) and (ap_const_logic_1 = AXI_video_strm_V_dest_V_0_ack_out) and (ap_const_lv2_3 = AXI_video_strm_V_dest_V_0_state)) or ((ap_const_logic_0 = AXI_video_strm_V_dest_V_0_vld_in) and (ap_const_lv2_2 = AXI_video_strm_V_dest_V_0_state)))) then 
                    AXI_video_strm_V_dest_V_0_state <= ap_const_lv2_2;
                elsif ((((ap_const_logic_1 = AXI_video_strm_V_dest_V_0_vld_in) and (ap_const_logic_0 = AXI_video_strm_V_dest_V_0_ack_out) and (ap_const_lv2_3 = AXI_video_strm_V_dest_V_0_state)) or ((ap_const_logic_0 = AXI_video_strm_V_dest_V_0_ack_out) and (ap_const_lv2_1 = AXI_video_strm_V_dest_V_0_state)))) then 
                    AXI_video_strm_V_dest_V_0_state <= ap_const_lv2_1;
                elsif ((((ap_const_logic_1 = AXI_video_strm_V_dest_V_0_vld_in) and (ap_const_lv2_2 = AXI_video_strm_V_dest_V_0_state)) or ((ap_const_logic_1 = AXI_video_strm_V_dest_V_0_ack_out) and (ap_const_lv2_1 = AXI_video_strm_V_dest_V_0_state)) or ((ap_const_lv2_3 = AXI_video_strm_V_dest_V_0_state) and not(((ap_const_logic_1 = AXI_video_strm_V_dest_V_0_vld_in) and (ap_const_logic_0 = AXI_video_strm_V_dest_V_0_ack_out))) and not(((ap_const_logic_0 = AXI_video_strm_V_dest_V_0_vld_in) and (ap_const_logic_1 = AXI_video_strm_V_dest_V_0_ack_out)))))) then 
                    AXI_video_strm_V_dest_V_0_state <= ap_const_lv2_3;
                else 
                    AXI_video_strm_V_dest_V_0_state <= ap_const_lv2_2;
                end if; 
            end if;
        end if;
    end process;


    AXI_video_strm_V_last_V_0_sel_rd_assign_proc : process(ap_clk)
    begin
        if (ap_clk'event and ap_clk =  '1') then
            if (ap_rst = '1') then
                AXI_video_strm_V_last_V_0_sel_rd <= ap_const_logic_0;
            else
                if (((ap_const_logic_1 = AXI_video_strm_V_last_V_0_ack_out) and (ap_const_logic_1 = AXI_video_strm_V_last_V_0_vld_out))) then 
                                        AXI_video_strm_V_last_V_0_sel_rd <= not(AXI_video_strm_V_last_V_0_sel_rd);
                end if; 
            end if;
        end if;
    end process;


    AXI_video_strm_V_last_V_0_sel_wr_assign_proc : process(ap_clk)
    begin
        if (ap_clk'event and ap_clk =  '1') then
            if (ap_rst = '1') then
                AXI_video_strm_V_last_V_0_sel_wr <= ap_const_logic_0;
            else
                if (((ap_const_logic_1 = AXI_video_strm_V_last_V_0_vld_in) and (ap_const_logic_1 = AXI_video_strm_V_last_V_0_ack_in))) then 
                                        AXI_video_strm_V_last_V_0_sel_wr <= not(AXI_video_strm_V_last_V_0_sel_wr);
                end if; 
            end if;
        end if;
    end process;


    AXI_video_strm_V_last_V_0_state_assign_proc : process(ap_clk)
    begin
        if (ap_clk'event and ap_clk =  '1') then
            if (ap_rst = '1') then
                AXI_video_strm_V_last_V_0_state <= ap_const_lv2_0;
            else
                if ((((ap_const_logic_0 = AXI_video_strm_V_last_V_0_vld_in) and (ap_const_logic_1 = AXI_video_strm_V_last_V_0_ack_out) and (ap_const_lv2_3 = AXI_video_strm_V_last_V_0_state)) or ((ap_const_logic_0 = AXI_video_strm_V_last_V_0_vld_in) and (ap_const_lv2_2 = AXI_video_strm_V_last_V_0_state)))) then 
                    AXI_video_strm_V_last_V_0_state <= ap_const_lv2_2;
                elsif ((((ap_const_logic_1 = AXI_video_strm_V_last_V_0_vld_in) and (ap_const_logic_0 = AXI_video_strm_V_last_V_0_ack_out) and (ap_const_lv2_3 = AXI_video_strm_V_last_V_0_state)) or ((ap_const_logic_0 = AXI_video_strm_V_last_V_0_ack_out) and (ap_const_lv2_1 = AXI_video_strm_V_last_V_0_state)))) then 
                    AXI_video_strm_V_last_V_0_state <= ap_const_lv2_1;
                elsif ((((ap_const_logic_1 = AXI_video_strm_V_last_V_0_vld_in) and (ap_const_lv2_2 = AXI_video_strm_V_last_V_0_state)) or ((ap_const_logic_1 = AXI_video_strm_V_last_V_0_ack_out) and (ap_const_lv2_1 = AXI_video_strm_V_last_V_0_state)) or ((ap_const_lv2_3 = AXI_video_strm_V_last_V_0_state) and not(((ap_const_logic_1 = AXI_video_strm_V_last_V_0_vld_in) and (ap_const_logic_0 = AXI_video_strm_V_last_V_0_ack_out))) and not(((ap_const_logic_0 = AXI_video_strm_V_last_V_0_vld_in) and (ap_const_logic_1 = AXI_video_strm_V_last_V_0_ack_out)))))) then 
                    AXI_video_strm_V_last_V_0_state <= ap_const_lv2_3;
                else 
                    AXI_video_strm_V_last_V_0_state <= ap_const_lv2_2;
                end if; 
            end if;
        end if;
    end process;


    AXI_video_strm_V_user_V_0_sel_rd_assign_proc : process(ap_clk)
    begin
        if (ap_clk'event and ap_clk =  '1') then
            if (ap_rst = '1') then
                AXI_video_strm_V_user_V_0_sel_rd <= ap_const_logic_0;
            else
                if (((ap_const_logic_1 = AXI_video_strm_V_user_V_0_ack_out) and (ap_const_logic_1 = AXI_video_strm_V_user_V_0_vld_out))) then 
                                        AXI_video_strm_V_user_V_0_sel_rd <= not(AXI_video_strm_V_user_V_0_sel_rd);
                end if; 
            end if;
        end if;
    end process;


    AXI_video_strm_V_user_V_0_sel_wr_assign_proc : process(ap_clk)
    begin
        if (ap_clk'event and ap_clk =  '1') then
            if (ap_rst = '1') then
                AXI_video_strm_V_user_V_0_sel_wr <= ap_const_logic_0;
            else
                if (((ap_const_logic_1 = AXI_video_strm_V_user_V_0_vld_in) and (ap_const_logic_1 = AXI_video_strm_V_user_V_0_ack_in))) then 
                                        AXI_video_strm_V_user_V_0_sel_wr <= not(AXI_video_strm_V_user_V_0_sel_wr);
                end if; 
            end if;
        end if;
    end process;


    AXI_video_strm_V_user_V_0_state_assign_proc : process(ap_clk)
    begin
        if (ap_clk'event and ap_clk =  '1') then
            if (ap_rst = '1') then
                AXI_video_strm_V_user_V_0_state <= ap_const_lv2_0;
            else
                if ((((ap_const_logic_0 = AXI_video_strm_V_user_V_0_vld_in) and (ap_const_logic_1 = AXI_video_strm_V_user_V_0_ack_out) and (ap_const_lv2_3 = AXI_video_strm_V_user_V_0_state)) or ((ap_const_logic_0 = AXI_video_strm_V_user_V_0_vld_in) and (ap_const_lv2_2 = AXI_video_strm_V_user_V_0_state)))) then 
                    AXI_video_strm_V_user_V_0_state <= ap_const_lv2_2;
                elsif ((((ap_const_logic_1 = AXI_video_strm_V_user_V_0_vld_in) and (ap_const_logic_0 = AXI_video_strm_V_user_V_0_ack_out) and (ap_const_lv2_3 = AXI_video_strm_V_user_V_0_state)) or ((ap_const_logic_0 = AXI_video_strm_V_user_V_0_ack_out) and (ap_const_lv2_1 = AXI_video_strm_V_user_V_0_state)))) then 
                    AXI_video_strm_V_user_V_0_state <= ap_const_lv2_1;
                elsif ((((ap_const_logic_1 = AXI_video_strm_V_user_V_0_vld_in) and (ap_const_lv2_2 = AXI_video_strm_V_user_V_0_state)) or ((ap_const_logic_1 = AXI_video_strm_V_user_V_0_ack_out) and (ap_const_lv2_1 = AXI_video_strm_V_user_V_0_state)) or ((ap_const_lv2_3 = AXI_video_strm_V_user_V_0_state) and not(((ap_const_logic_1 = AXI_video_strm_V_user_V_0_vld_in) and (ap_const_logic_0 = AXI_video_strm_V_user_V_0_ack_out))) and not(((ap_const_logic_0 = AXI_video_strm_V_user_V_0_vld_in) and (ap_const_logic_1 = AXI_video_strm_V_user_V_0_ack_out)))))) then 
                    AXI_video_strm_V_user_V_0_state <= ap_const_lv2_3;
                else 
                    AXI_video_strm_V_user_V_0_state <= ap_const_lv2_2;
                end if; 
            end if;
        end if;
    end process;


    ap_CS_fsm_assign_proc : process(ap_clk)
    begin
        if (ap_clk'event and ap_clk =  '1') then
            if (ap_rst = '1') then
                ap_CS_fsm <= ap_ST_fsm_state1;
            else
                ap_CS_fsm <= ap_NS_fsm;
            end if;
        end if;
    end process;


    ap_done_reg_assign_proc : process(ap_clk)
    begin
        if (ap_clk'event and ap_clk =  '1') then
            if (ap_rst = '1') then
                ap_done_reg <= ap_const_logic_0;
            else
                if ((ap_const_logic_1 = ap_continue)) then 
                    ap_done_reg <= ap_const_logic_0;
                elsif (((ap_const_logic_1 = ap_CS_fsm_state4) and (ap_const_lv1_1 = exitcond7_i_fu_340_p2))) then 
                    ap_done_reg <= ap_const_logic_1;
                end if; 
            end if;
        end if;
    end process;


    ap_enable_reg_pp1_iter0_assign_proc : process(ap_clk)
    begin
        if (ap_clk'event and ap_clk =  '1') then
            if (ap_rst = '1') then
                ap_enable_reg_pp1_iter0 <= ap_const_logic_0;
            else
                if (((ap_const_logic_1 = ap_CS_fsm_pp1_stage0) and (ap_block_pp1_stage0_flag00011011 = ap_const_boolean_0) and (ap_const_lv1_1 = exitcond_i_fu_355_p2))) then 
                    ap_enable_reg_pp1_iter0 <= ap_const_logic_0;
                elsif (((ap_const_logic_1 = ap_CS_fsm_state4) and (ap_const_lv1_0 = exitcond7_i_fu_340_p2))) then 
                    ap_enable_reg_pp1_iter0 <= ap_const_logic_1;
                end if; 
            end if;
        end if;
    end process;


    ap_enable_reg_pp1_iter1_assign_proc : process(ap_clk)
    begin
        if (ap_clk'event and ap_clk =  '1') then
            if (ap_rst = '1') then
                ap_enable_reg_pp1_iter1 <= ap_const_logic_0;
            else
                if ((ap_block_pp1_stage0_flag00011011 = ap_const_boolean_0)) then 
                    ap_enable_reg_pp1_iter1 <= ap_enable_reg_pp1_iter0;
                elsif (((ap_const_logic_1 = ap_CS_fsm_state4) and (ap_const_lv1_0 = exitcond7_i_fu_340_p2))) then 
                    ap_enable_reg_pp1_iter1 <= ap_const_logic_0;
                end if; 
            end if;
        end if;
    end process;


    ap_enable_reg_pp2_iter0_assign_proc : process(ap_clk)
    begin
        if (ap_clk'event and ap_clk =  '1') then
            if (ap_rst = '1') then
                ap_enable_reg_pp2_iter0 <= ap_const_logic_0;
            else
                if (((ap_const_logic_1 = ap_CS_fsm_pp2_stage0) and (ap_block_pp2_stage0_flag00011011 = ap_const_boolean_0) and (ap_const_lv1_1 = eol_2_i_phi_fu_285_p4))) then 
                    ap_enable_reg_pp2_iter0 <= ap_const_logic_0;
                elsif ((ap_const_logic_1 = ap_CS_fsm_state7)) then 
                    ap_enable_reg_pp2_iter0 <= ap_const_logic_1;
                end if; 
            end if;
        end if;
    end process;


    ap_enable_reg_pp2_iter1_assign_proc : process(ap_clk)
    begin
        if (ap_clk'event and ap_clk =  '1') then
            if (ap_rst = '1') then
                ap_enable_reg_pp2_iter1 <= ap_const_logic_0;
            else
                if ((ap_block_pp2_stage0_flag00011011 = ap_const_boolean_0)) then 
                    ap_enable_reg_pp2_iter1 <= ap_enable_reg_pp2_iter0;
                elsif ((ap_const_logic_1 = ap_CS_fsm_state7)) then 
                    ap_enable_reg_pp2_iter1 <= ap_const_logic_0;
                end if; 
            end if;
        end if;
    end process;


    real_start_status_reg_assign_proc : process(ap_clk)
    begin
        if (ap_clk'event and ap_clk =  '1') then
            if (ap_rst = '1') then
                real_start_status_reg <= ap_const_logic_0;
            else
                if ((start_full_n = ap_const_logic_1)) then 
                    real_start_status_reg <= ap_const_logic_0;
                elsif (((ap_const_logic_0 = start_full_n) and (ap_const_logic_1 = internal_ap_ready))) then 
                    real_start_status_reg <= ap_const_logic_1;
                end if; 
            end if;
        end if;
    end process;


    start_control_reg_assign_proc : process(ap_clk)
    begin
        if (ap_clk'event and ap_clk =  '1') then
            if (ap_rst = '1') then
                start_control_reg <= ap_const_logic_0;
            else
                if (((ap_const_logic_1 = real_start) and ((ap_const_logic_1 = internal_ap_ready) or (ap_const_logic_0 = start_once_reg)))) then 
                    start_control_reg <= ap_const_logic_1;
                elsif ((ap_const_logic_1 = start_control_reg)) then 
                    start_control_reg <= ap_const_logic_0;
                end if; 
            end if;
        end if;
    end process;


    start_once_reg_assign_proc : process(ap_clk)
    begin
        if (ap_clk'event and ap_clk =  '1') then
            if (ap_rst = '1') then
                start_once_reg <= ap_const_logic_0;
            else
                if ((ap_const_logic_1 = real_start)) then 
                    start_once_reg <= ap_const_logic_1;
                elsif ((ap_const_logic_0 = ap_start)) then 
                    start_once_reg <= ap_const_logic_0;
                end if; 
            end if;
        end if;
    end process;


    axi_data_V1_i_reg_191_assign_proc : process (ap_clk)
    begin
        if (ap_clk'event and ap_clk = '1') then
            if ((ap_const_logic_1 = ap_CS_fsm_state3)) then 
                axi_data_V1_i_reg_191 <= tmp_data_V_reg_417;
            elsif ((ap_const_logic_1 = ap_CS_fsm_state10)) then 
                axi_data_V1_i_reg_191 <= axi_data_V_3_i_reg_305;
            end if; 
        end if;
    end process;

    axi_data_V_1_i_reg_246_assign_proc : process (ap_clk)
    begin
        if (ap_clk'event and ap_clk = '1') then
            if (((ap_const_logic_1 = ap_CS_fsm_pp1_stage0) and (ap_const_logic_1 = ap_enable_reg_pp1_iter1) and (ap_const_lv1_0 = exitcond_i_reg_446) and (ap_block_pp1_stage0_flag00011001 = ap_const_boolean_0))) then 
                axi_data_V_1_i_reg_246 <= p_Val2_s_phi_fu_274_p4;
            elsif (((ap_const_logic_1 = ap_CS_fsm_state4) and (ap_const_lv1_0 = exitcond7_i_fu_340_p2))) then 
                axi_data_V_1_i_reg_246 <= axi_data_V1_i_reg_191;
            end if; 
        end if;
    end process;

    axi_data_V_3_i_reg_305_assign_proc : process (ap_clk)
    begin
        if (ap_clk'event and ap_clk = '1') then
            if ((ap_const_logic_1 = ap_CS_fsm_state7)) then 
                axi_data_V_3_i_reg_305 <= axi_data_V_1_i_reg_246;
            elsif (((ap_const_logic_1 = ap_CS_fsm_pp2_stage0) and (ap_const_logic_1 = ap_enable_reg_pp2_iter1) and (ap_const_lv1_0 = eol_2_i_reg_282) and (ap_block_pp2_stage0_flag00011001 = ap_const_boolean_0))) then 
                axi_data_V_3_i_reg_305 <= AXI_video_strm_V_data_V_0_data_out;
            end if; 
        end if;
    end process;

    axi_last_V1_i_reg_181_assign_proc : process (ap_clk)
    begin
        if (ap_clk'event and ap_clk = '1') then
            if ((ap_const_logic_1 = ap_CS_fsm_state3)) then 
                axi_last_V1_i_reg_181 <= tmp_last_V_reg_425;
            elsif ((ap_const_logic_1 = ap_CS_fsm_state10)) then 
                axi_last_V1_i_reg_181 <= axi_last_V_3_i_reg_293;
            end if; 
        end if;
    end process;

    axi_last_V_3_i_reg_293_assign_proc : process (ap_clk)
    begin
        if (ap_clk'event and ap_clk = '1') then
            if ((ap_const_logic_1 = ap_CS_fsm_state7)) then 
                axi_last_V_3_i_reg_293 <= eol_reg_235;
            elsif (((ap_const_logic_1 = ap_CS_fsm_pp2_stage0) and (ap_const_logic_1 = ap_enable_reg_pp2_iter1) and (ap_const_lv1_0 = eol_2_i_reg_282) and (ap_block_pp2_stage0_flag00011001 = ap_const_boolean_0))) then 
                axi_last_V_3_i_reg_293 <= AXI_video_strm_V_last_V_0_data_out;
            end if; 
        end if;
    end process;

    eol_2_i_reg_282_assign_proc : process (ap_clk)
    begin
        if (ap_clk'event and ap_clk = '1') then
            if ((ap_const_logic_1 = ap_CS_fsm_state7)) then 
                eol_2_i_reg_282 <= eol_i_reg_223;
            elsif (((ap_const_logic_1 = ap_CS_fsm_pp2_stage0) and (ap_const_logic_1 = ap_enable_reg_pp2_iter1) and (ap_const_lv1_0 = eol_2_i_reg_282) and (ap_block_pp2_stage0_flag00011001 = ap_const_boolean_0))) then 
                eol_2_i_reg_282 <= AXI_video_strm_V_last_V_0_data_out;
            end if; 
        end if;
    end process;

    eol_i_reg_223_assign_proc : process (ap_clk)
    begin
        if (ap_clk'event and ap_clk = '1') then
            if (((ap_const_logic_1 = ap_CS_fsm_pp1_stage0) and (ap_const_logic_1 = ap_enable_reg_pp1_iter1) and (ap_const_lv1_0 = exitcond_i_reg_446) and (ap_block_pp1_stage0_flag00011001 = ap_const_boolean_0))) then 
                eol_i_reg_223 <= axi_last_V_2_i_phi_fu_262_p4;
            elsif (((ap_const_logic_1 = ap_CS_fsm_state4) and (ap_const_lv1_0 = exitcond7_i_fu_340_p2))) then 
                eol_i_reg_223 <= ap_const_lv1_0;
            end if; 
        end if;
    end process;

    eol_reg_235_assign_proc : process (ap_clk)
    begin
        if (ap_clk'event and ap_clk = '1') then
            if (((ap_const_logic_1 = ap_CS_fsm_pp1_stage0) and (ap_const_logic_1 = ap_enable_reg_pp1_iter1) and (ap_const_lv1_0 = exitcond_i_reg_446) and (ap_block_pp1_stage0_flag00011001 = ap_const_boolean_0))) then 
                eol_reg_235 <= axi_last_V_2_i_phi_fu_262_p4;
            elsif (((ap_const_logic_1 = ap_CS_fsm_state4) and (ap_const_lv1_0 = exitcond7_i_fu_340_p2))) then 
                eol_reg_235 <= axi_last_V1_i_reg_181;
            end if; 
        end if;
    end process;

    sof_1_i_fu_110_assign_proc : process (ap_clk)
    begin
        if (ap_clk'event and ap_clk = '1') then
            if (((ap_const_logic_1 = ap_CS_fsm_pp1_stage0) and (ap_block_pp1_stage0_flag00011001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp1_iter0) and (ap_const_lv1_0 = exitcond_i_fu_355_p2))) then 
                sof_1_i_fu_110 <= ap_const_lv1_0;
            elsif ((ap_const_logic_1 = ap_CS_fsm_state3)) then 
                sof_1_i_fu_110 <= ap_const_lv1_1;
            end if; 
        end if;
    end process;

    t_V_6_reg_212_assign_proc : process (ap_clk)
    begin
        if (ap_clk'event and ap_clk = '1') then
            if (((ap_const_logic_1 = ap_CS_fsm_pp1_stage0) and (ap_block_pp1_stage0_flag00011001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp1_iter0) and (ap_const_lv1_0 = exitcond_i_fu_355_p2))) then 
                t_V_6_reg_212 <= j_V_fu_360_p2;
            elsif (((ap_const_logic_1 = ap_CS_fsm_state4) and (ap_const_lv1_0 = exitcond7_i_fu_340_p2))) then 
                t_V_6_reg_212 <= ap_const_lv10_0;
            end if; 
        end if;
    end process;

    t_V_reg_201_assign_proc : process (ap_clk)
    begin
        if (ap_clk'event and ap_clk = '1') then
            if ((ap_const_logic_1 = ap_CS_fsm_state3)) then 
                t_V_reg_201 <= ap_const_lv9_0;
            elsif ((ap_const_logic_1 = ap_CS_fsm_state10)) then 
                t_V_reg_201 <= i_V_reg_441;
            end if; 
        end if;
    end process;
    process (ap_clk)
    begin
        if (ap_clk'event and ap_clk = '1') then
            if ((ap_const_logic_1 = AXI_video_strm_V_data_V_0_load_A)) then
                AXI_video_strm_V_data_V_0_payload_A <= video_in_TDATA;
            end if;
        end if;
    end process;
    process (ap_clk)
    begin
        if (ap_clk'event and ap_clk = '1') then
            if ((ap_const_logic_1 = AXI_video_strm_V_data_V_0_load_B)) then
                AXI_video_strm_V_data_V_0_payload_B <= video_in_TDATA;
            end if;
        end if;
    end process;
    process (ap_clk)
    begin
        if (ap_clk'event and ap_clk = '1') then
            if ((ap_const_logic_1 = AXI_video_strm_V_last_V_0_load_A)) then
                AXI_video_strm_V_last_V_0_payload_A <= video_in_TLAST;
            end if;
        end if;
    end process;
    process (ap_clk)
    begin
        if (ap_clk'event and ap_clk = '1') then
            if ((ap_const_logic_1 = AXI_video_strm_V_last_V_0_load_B)) then
                AXI_video_strm_V_last_V_0_payload_B <= video_in_TLAST;
            end if;
        end if;
    end process;
    process (ap_clk)
    begin
        if (ap_clk'event and ap_clk = '1') then
            if ((ap_const_logic_1 = AXI_video_strm_V_user_V_0_load_A)) then
                AXI_video_strm_V_user_V_0_payload_A <= video_in_TUSER;
            end if;
        end if;
    end process;
    process (ap_clk)
    begin
        if (ap_clk'event and ap_clk = '1') then
            if ((ap_const_logic_1 = AXI_video_strm_V_user_V_0_load_B)) then
                AXI_video_strm_V_user_V_0_payload_B <= video_in_TUSER;
            end if;
        end if;
    end process;
    process (ap_clk)
    begin
        if (ap_clk'event and ap_clk = '1') then
            if (((ap_const_logic_1 = ap_CS_fsm_pp1_stage0) and (ap_block_pp1_stage0_flag00011001 = ap_const_boolean_0) and (ap_const_lv1_0 = exitcond_i_fu_355_p2))) then
                brmerge_i_reg_455 <= brmerge_i_fu_369_p2;
            end if;
        end if;
    end process;
    process (ap_clk)
    begin
        if (ap_clk'event and ap_clk = '1') then
            if (((ap_const_logic_1 = ap_CS_fsm_pp1_stage0) and (ap_block_pp1_stage0_flag00011001 = ap_const_boolean_0))) then
                exitcond_i_reg_446 <= exitcond_i_fu_355_p2;
            end if;
        end if;
    end process;
    process (ap_clk)
    begin
        if (ap_clk'event and ap_clk = '1') then
            if ((ap_const_logic_1 = ap_CS_fsm_state4)) then
                i_V_reg_441 <= i_V_fu_345_p2;
            end if;
        end if;
    end process;
    process (ap_clk)
    begin
        if (ap_clk'event and ap_clk = '1') then
            if (((ap_const_logic_1 = ap_CS_fsm_state1) and not(((ap_const_logic_0 = real_start) or (ap_done_reg = ap_const_logic_1) or (ap_const_logic_0 = img_rows_V_empty_n) or (ap_const_logic_0 = img_cols_V_empty_n) or (ap_const_logic_0 = img_rows_V_out_full_n) or (ap_const_logic_0 = img_cols_V_out_full_n))))) then
                img_cols_V_read_reg_412 <= img_cols_V_dout;
                img_rows_V_read_reg_407 <= img_rows_V_dout;
            end if;
        end if;
    end process;
    process (ap_clk)
    begin
        if (ap_clk'event and ap_clk = '1') then
            if (((ap_const_logic_1 = ap_CS_fsm_state2) and (AXI_video_strm_V_data_V_0_vld_out = ap_const_logic_1))) then
                tmp_data_V_reg_417 <= AXI_video_strm_V_data_V_0_data_out;
                tmp_last_V_reg_425 <= AXI_video_strm_V_last_V_0_data_out;
            end if;
        end if;
    end process;

    ap_NS_fsm_assign_proc : process (real_start, ap_done_reg, ap_CS_fsm, ap_CS_fsm_state1, AXI_video_strm_V_data_V_0_vld_out, img_rows_V_empty_n, img_cols_V_empty_n, img_rows_V_out_full_n, img_cols_V_out_full_n, ap_CS_fsm_state2, ap_CS_fsm_pp1_stage0, ap_enable_reg_pp1_iter1, ap_CS_fsm_pp2_stage0, ap_enable_reg_pp2_iter1, exitcond7_i_fu_340_p2, ap_CS_fsm_state4, ap_enable_reg_pp1_iter0, ap_block_pp1_stage0_flag00011011, ap_enable_reg_pp2_iter0, ap_block_pp2_stage0_flag00011011, tmp_user_V_fu_327_p1)
    begin
        case ap_CS_fsm is
            when ap_ST_fsm_state1 => 
                if (((ap_const_logic_1 = ap_CS_fsm_state1) and not(((ap_const_logic_0 = real_start) or (ap_done_reg = ap_const_logic_1) or (ap_const_logic_0 = img_rows_V_empty_n) or (ap_const_logic_0 = img_cols_V_empty_n) or (ap_const_logic_0 = img_rows_V_out_full_n) or (ap_const_logic_0 = img_cols_V_out_full_n))))) then
                    ap_NS_fsm <= ap_ST_fsm_state2;
                else
                    ap_NS_fsm <= ap_ST_fsm_state1;
                end if;
            when ap_ST_fsm_state2 => 
                if (((ap_const_logic_1 = ap_CS_fsm_state2) and (AXI_video_strm_V_data_V_0_vld_out = ap_const_logic_1) and (ap_const_lv1_0 = tmp_user_V_fu_327_p1))) then
                    ap_NS_fsm <= ap_ST_fsm_state2;
                elsif (((ap_const_logic_1 = ap_CS_fsm_state2) and (AXI_video_strm_V_data_V_0_vld_out = ap_const_logic_1) and (ap_const_lv1_1 = tmp_user_V_fu_327_p1))) then
                    ap_NS_fsm <= ap_ST_fsm_state3;
                else
                    ap_NS_fsm <= ap_ST_fsm_state2;
                end if;
            when ap_ST_fsm_state3 => 
                ap_NS_fsm <= ap_ST_fsm_state4;
            when ap_ST_fsm_state4 => 
                if (((ap_const_logic_1 = ap_CS_fsm_state4) and (ap_const_lv1_1 = exitcond7_i_fu_340_p2))) then
                    ap_NS_fsm <= ap_ST_fsm_state1;
                else
                    ap_NS_fsm <= ap_ST_fsm_pp1_stage0;
                end if;
            when ap_ST_fsm_pp1_stage0 => 
                if (not(((ap_const_logic_1 = ap_CS_fsm_pp1_stage0) and (ap_const_logic_1 = ap_enable_reg_pp1_iter1) and (ap_block_pp1_stage0_flag00011011 = ap_const_boolean_0) and (ap_enable_reg_pp1_iter0 = ap_const_logic_0)))) then
                    ap_NS_fsm <= ap_ST_fsm_pp1_stage0;
                elsif (((ap_const_logic_1 = ap_CS_fsm_pp1_stage0) and (ap_const_logic_1 = ap_enable_reg_pp1_iter1) and (ap_block_pp1_stage0_flag00011011 = ap_const_boolean_0) and (ap_enable_reg_pp1_iter0 = ap_const_logic_0))) then
                    ap_NS_fsm <= ap_ST_fsm_state7;
                else
                    ap_NS_fsm <= ap_ST_fsm_pp1_stage0;
                end if;
            when ap_ST_fsm_state7 => 
                ap_NS_fsm <= ap_ST_fsm_pp2_stage0;
            when ap_ST_fsm_pp2_stage0 => 
                if (not(((ap_const_logic_1 = ap_CS_fsm_pp2_stage0) and (ap_const_logic_1 = ap_enable_reg_pp2_iter1) and (ap_block_pp2_stage0_flag00011011 = ap_const_boolean_0) and (ap_enable_reg_pp2_iter0 = ap_const_logic_0)))) then
                    ap_NS_fsm <= ap_ST_fsm_pp2_stage0;
                elsif (((ap_const_logic_1 = ap_CS_fsm_pp2_stage0) and (ap_const_logic_1 = ap_enable_reg_pp2_iter1) and (ap_block_pp2_stage0_flag00011011 = ap_const_boolean_0) and (ap_enable_reg_pp2_iter0 = ap_const_logic_0))) then
                    ap_NS_fsm <= ap_ST_fsm_state10;
                else
                    ap_NS_fsm <= ap_ST_fsm_pp2_stage0;
                end if;
            when ap_ST_fsm_state10 => 
                ap_NS_fsm <= ap_ST_fsm_state4;
            when others =>  
                ap_NS_fsm <= "XXXXXXXX";
        end case;
    end process;
    AXI_video_strm_V_data_V_0_ack_in <= AXI_video_strm_V_data_V_0_state(1);

    AXI_video_strm_V_data_V_0_ack_out_assign_proc : process(AXI_video_strm_V_data_V_0_vld_out, ap_CS_fsm_state2, ap_CS_fsm_pp1_stage0, ap_enable_reg_pp1_iter1, ap_CS_fsm_pp2_stage0, ap_enable_reg_pp2_iter1, eol_2_i_reg_282, ap_predicate_op73_read_state6, ap_block_pp1_stage0_flag00011001, ap_block_pp2_stage0_flag00011001)
    begin
        if ((((ap_const_logic_1 = ap_CS_fsm_state2) and (AXI_video_strm_V_data_V_0_vld_out = ap_const_logic_1)) or ((ap_const_logic_1 = ap_CS_fsm_pp2_stage0) and (ap_const_logic_1 = ap_enable_reg_pp2_iter1) and (ap_const_lv1_0 = eol_2_i_reg_282) and (ap_block_pp2_stage0_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_CS_fsm_pp1_stage0) and (ap_const_logic_1 = ap_enable_reg_pp1_iter1) and (ap_const_boolean_1 = ap_predicate_op73_read_state6) and (ap_block_pp1_stage0_flag00011001 = ap_const_boolean_0)))) then 
            AXI_video_strm_V_data_V_0_ack_out <= ap_const_logic_1;
        else 
            AXI_video_strm_V_data_V_0_ack_out <= ap_const_logic_0;
        end if; 
    end process;


    AXI_video_strm_V_data_V_0_data_out_assign_proc : process(AXI_video_strm_V_data_V_0_payload_A, AXI_video_strm_V_data_V_0_payload_B, AXI_video_strm_V_data_V_0_sel)
    begin
        if ((ap_const_logic_1 = AXI_video_strm_V_data_V_0_sel)) then 
            AXI_video_strm_V_data_V_0_data_out <= AXI_video_strm_V_data_V_0_payload_B;
        else 
            AXI_video_strm_V_data_V_0_data_out <= AXI_video_strm_V_data_V_0_payload_A;
        end if; 
    end process;

    AXI_video_strm_V_data_V_0_load_A <= (AXI_video_strm_V_data_V_0_state_cmp_full and not(AXI_video_strm_V_data_V_0_sel_wr));
    AXI_video_strm_V_data_V_0_load_B <= (AXI_video_strm_V_data_V_0_sel_wr and AXI_video_strm_V_data_V_0_state_cmp_full);
    AXI_video_strm_V_data_V_0_sel <= AXI_video_strm_V_data_V_0_sel_rd;
    AXI_video_strm_V_data_V_0_state_cmp_full <= '0' when (AXI_video_strm_V_data_V_0_state = ap_const_lv2_1) else '1';
    AXI_video_strm_V_data_V_0_vld_in <= video_in_TVALID;
    AXI_video_strm_V_data_V_0_vld_out <= AXI_video_strm_V_data_V_0_state(0);

    AXI_video_strm_V_dest_V_0_ack_out_assign_proc : process(AXI_video_strm_V_data_V_0_vld_out, ap_CS_fsm_state2, ap_CS_fsm_pp1_stage0, ap_enable_reg_pp1_iter1, ap_CS_fsm_pp2_stage0, ap_enable_reg_pp2_iter1, eol_2_i_reg_282, ap_predicate_op73_read_state6, ap_block_pp1_stage0_flag00011001, ap_block_pp2_stage0_flag00011001)
    begin
        if ((((ap_const_logic_1 = ap_CS_fsm_state2) and (AXI_video_strm_V_data_V_0_vld_out = ap_const_logic_1)) or ((ap_const_logic_1 = ap_CS_fsm_pp2_stage0) and (ap_const_logic_1 = ap_enable_reg_pp2_iter1) and (ap_const_lv1_0 = eol_2_i_reg_282) and (ap_block_pp2_stage0_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_CS_fsm_pp1_stage0) and (ap_const_logic_1 = ap_enable_reg_pp1_iter1) and (ap_const_boolean_1 = ap_predicate_op73_read_state6) and (ap_block_pp1_stage0_flag00011001 = ap_const_boolean_0)))) then 
            AXI_video_strm_V_dest_V_0_ack_out <= ap_const_logic_1;
        else 
            AXI_video_strm_V_dest_V_0_ack_out <= ap_const_logic_0;
        end if; 
    end process;

    AXI_video_strm_V_dest_V_0_vld_in <= video_in_TVALID;
    AXI_video_strm_V_last_V_0_ack_in <= AXI_video_strm_V_last_V_0_state(1);

    AXI_video_strm_V_last_V_0_ack_out_assign_proc : process(AXI_video_strm_V_data_V_0_vld_out, ap_CS_fsm_state2, ap_CS_fsm_pp1_stage0, ap_enable_reg_pp1_iter1, ap_CS_fsm_pp2_stage0, ap_enable_reg_pp2_iter1, eol_2_i_reg_282, ap_predicate_op73_read_state6, ap_block_pp1_stage0_flag00011001, ap_block_pp2_stage0_flag00011001)
    begin
        if ((((ap_const_logic_1 = ap_CS_fsm_state2) and (AXI_video_strm_V_data_V_0_vld_out = ap_const_logic_1)) or ((ap_const_logic_1 = ap_CS_fsm_pp2_stage0) and (ap_const_logic_1 = ap_enable_reg_pp2_iter1) and (ap_const_lv1_0 = eol_2_i_reg_282) and (ap_block_pp2_stage0_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_CS_fsm_pp1_stage0) and (ap_const_logic_1 = ap_enable_reg_pp1_iter1) and (ap_const_boolean_1 = ap_predicate_op73_read_state6) and (ap_block_pp1_stage0_flag00011001 = ap_const_boolean_0)))) then 
            AXI_video_strm_V_last_V_0_ack_out <= ap_const_logic_1;
        else 
            AXI_video_strm_V_last_V_0_ack_out <= ap_const_logic_0;
        end if; 
    end process;


    AXI_video_strm_V_last_V_0_data_out_assign_proc : process(AXI_video_strm_V_last_V_0_payload_A, AXI_video_strm_V_last_V_0_payload_B, AXI_video_strm_V_last_V_0_sel)
    begin
        if ((ap_const_logic_1 = AXI_video_strm_V_last_V_0_sel)) then 
            AXI_video_strm_V_last_V_0_data_out <= AXI_video_strm_V_last_V_0_payload_B;
        else 
            AXI_video_strm_V_last_V_0_data_out <= AXI_video_strm_V_last_V_0_payload_A;
        end if; 
    end process;

    AXI_video_strm_V_last_V_0_load_A <= (AXI_video_strm_V_last_V_0_state_cmp_full and not(AXI_video_strm_V_last_V_0_sel_wr));
    AXI_video_strm_V_last_V_0_load_B <= (AXI_video_strm_V_last_V_0_sel_wr and AXI_video_strm_V_last_V_0_state_cmp_full);
    AXI_video_strm_V_last_V_0_sel <= AXI_video_strm_V_last_V_0_sel_rd;
    AXI_video_strm_V_last_V_0_state_cmp_full <= '0' when (AXI_video_strm_V_last_V_0_state = ap_const_lv2_1) else '1';
    AXI_video_strm_V_last_V_0_vld_in <= video_in_TVALID;
    AXI_video_strm_V_last_V_0_vld_out <= AXI_video_strm_V_last_V_0_state(0);
    AXI_video_strm_V_user_V_0_ack_in <= AXI_video_strm_V_user_V_0_state(1);

    AXI_video_strm_V_user_V_0_ack_out_assign_proc : process(AXI_video_strm_V_data_V_0_vld_out, ap_CS_fsm_state2, ap_CS_fsm_pp1_stage0, ap_enable_reg_pp1_iter1, ap_CS_fsm_pp2_stage0, ap_enable_reg_pp2_iter1, eol_2_i_reg_282, ap_predicate_op73_read_state6, ap_block_pp1_stage0_flag00011001, ap_block_pp2_stage0_flag00011001)
    begin
        if ((((ap_const_logic_1 = ap_CS_fsm_state2) and (AXI_video_strm_V_data_V_0_vld_out = ap_const_logic_1)) or ((ap_const_logic_1 = ap_CS_fsm_pp2_stage0) and (ap_const_logic_1 = ap_enable_reg_pp2_iter1) and (ap_const_lv1_0 = eol_2_i_reg_282) and (ap_block_pp2_stage0_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_CS_fsm_pp1_stage0) and (ap_const_logic_1 = ap_enable_reg_pp1_iter1) and (ap_const_boolean_1 = ap_predicate_op73_read_state6) and (ap_block_pp1_stage0_flag00011001 = ap_const_boolean_0)))) then 
            AXI_video_strm_V_user_V_0_ack_out <= ap_const_logic_1;
        else 
            AXI_video_strm_V_user_V_0_ack_out <= ap_const_logic_0;
        end if; 
    end process;


    AXI_video_strm_V_user_V_0_data_out_assign_proc : process(AXI_video_strm_V_user_V_0_payload_A, AXI_video_strm_V_user_V_0_payload_B, AXI_video_strm_V_user_V_0_sel)
    begin
        if ((ap_const_logic_1 = AXI_video_strm_V_user_V_0_sel)) then 
            AXI_video_strm_V_user_V_0_data_out <= AXI_video_strm_V_user_V_0_payload_B;
        else 
            AXI_video_strm_V_user_V_0_data_out <= AXI_video_strm_V_user_V_0_payload_A;
        end if; 
    end process;

    AXI_video_strm_V_user_V_0_load_A <= (AXI_video_strm_V_user_V_0_state_cmp_full and not(AXI_video_strm_V_user_V_0_sel_wr));
    AXI_video_strm_V_user_V_0_load_B <= (AXI_video_strm_V_user_V_0_sel_wr and AXI_video_strm_V_user_V_0_state_cmp_full);
    AXI_video_strm_V_user_V_0_sel <= AXI_video_strm_V_user_V_0_sel_rd;
    AXI_video_strm_V_user_V_0_state_cmp_full <= '0' when (AXI_video_strm_V_user_V_0_state = ap_const_lv2_1) else '1';
    AXI_video_strm_V_user_V_0_vld_in <= video_in_TVALID;
    AXI_video_strm_V_user_V_0_vld_out <= AXI_video_strm_V_user_V_0_state(0);
    ap_CS_fsm_pp1_stage0 <= ap_CS_fsm(4);
    ap_CS_fsm_pp2_stage0 <= ap_CS_fsm(6);
    ap_CS_fsm_state1 <= ap_CS_fsm(0);
    ap_CS_fsm_state10 <= ap_CS_fsm(7);
    ap_CS_fsm_state2 <= ap_CS_fsm(1);
    ap_CS_fsm_state3 <= ap_CS_fsm(2);
    ap_CS_fsm_state4 <= ap_CS_fsm(3);
    ap_CS_fsm_state7 <= ap_CS_fsm(5);
        ap_block_pp1_stage0_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1));

    ap_block_pp1_stage0_flag00001001_assign_proc : process(AXI_video_strm_V_data_V_0_vld_out, img_data_stream_0_V_full_n, img_data_stream_1_V_full_n, img_data_stream_2_V_full_n, ap_enable_reg_pp1_iter1, exitcond_i_reg_446, ap_predicate_op73_read_state6)
    begin
                ap_block_pp1_stage0_flag00001001 <= ((ap_const_logic_1 = ap_enable_reg_pp1_iter1) and (((ap_const_logic_0 = AXI_video_strm_V_data_V_0_vld_out) and (ap_const_boolean_1 = ap_predicate_op73_read_state6)) or ((ap_const_lv1_0 = exitcond_i_reg_446) and (ap_const_logic_0 = img_data_stream_0_V_full_n)) or ((ap_const_lv1_0 = exitcond_i_reg_446) and (ap_const_logic_0 = img_data_stream_1_V_full_n)) or ((ap_const_lv1_0 = exitcond_i_reg_446) and (ap_const_logic_0 = img_data_stream_2_V_full_n))));
    end process;


    ap_block_pp1_stage0_flag00011001_assign_proc : process(AXI_video_strm_V_data_V_0_vld_out, img_data_stream_0_V_full_n, img_data_stream_1_V_full_n, img_data_stream_2_V_full_n, ap_enable_reg_pp1_iter1, exitcond_i_reg_446, ap_predicate_op73_read_state6)
    begin
                ap_block_pp1_stage0_flag00011001 <= ((ap_const_logic_1 = ap_enable_reg_pp1_iter1) and (((ap_const_logic_0 = AXI_video_strm_V_data_V_0_vld_out) and (ap_const_boolean_1 = ap_predicate_op73_read_state6)) or ((ap_const_lv1_0 = exitcond_i_reg_446) and (ap_const_logic_0 = img_data_stream_0_V_full_n)) or ((ap_const_lv1_0 = exitcond_i_reg_446) and (ap_const_logic_0 = img_data_stream_1_V_full_n)) or ((ap_const_lv1_0 = exitcond_i_reg_446) and (ap_const_logic_0 = img_data_stream_2_V_full_n))));
    end process;


    ap_block_pp1_stage0_flag00011011_assign_proc : process(AXI_video_strm_V_data_V_0_vld_out, img_data_stream_0_V_full_n, img_data_stream_1_V_full_n, img_data_stream_2_V_full_n, ap_enable_reg_pp1_iter1, exitcond_i_reg_446, ap_predicate_op73_read_state6)
    begin
                ap_block_pp1_stage0_flag00011011 <= ((ap_const_logic_1 = ap_enable_reg_pp1_iter1) and (((ap_const_logic_0 = AXI_video_strm_V_data_V_0_vld_out) and (ap_const_boolean_1 = ap_predicate_op73_read_state6)) or ((ap_const_lv1_0 = exitcond_i_reg_446) and (ap_const_logic_0 = img_data_stream_0_V_full_n)) or ((ap_const_lv1_0 = exitcond_i_reg_446) and (ap_const_logic_0 = img_data_stream_1_V_full_n)) or ((ap_const_lv1_0 = exitcond_i_reg_446) and (ap_const_logic_0 = img_data_stream_2_V_full_n))));
    end process;

        ap_block_pp2_stage0_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1));

    ap_block_pp2_stage0_flag00011001_assign_proc : process(AXI_video_strm_V_data_V_0_vld_out, ap_enable_reg_pp2_iter1, eol_2_i_reg_282)
    begin
                ap_block_pp2_stage0_flag00011001 <= ((ap_const_logic_1 = ap_enable_reg_pp2_iter1) and (ap_const_lv1_0 = eol_2_i_reg_282) and (ap_const_logic_0 = AXI_video_strm_V_data_V_0_vld_out));
    end process;


    ap_block_pp2_stage0_flag00011011_assign_proc : process(AXI_video_strm_V_data_V_0_vld_out, ap_enable_reg_pp2_iter1, eol_2_i_reg_282)
    begin
                ap_block_pp2_stage0_flag00011011 <= ((ap_const_logic_1 = ap_enable_reg_pp2_iter1) and (ap_const_lv1_0 = eol_2_i_reg_282) and (ap_const_logic_0 = AXI_video_strm_V_data_V_0_vld_out));
    end process;


    ap_block_state1_assign_proc : process(real_start, ap_done_reg, img_rows_V_empty_n, img_cols_V_empty_n, img_rows_V_out_full_n, img_cols_V_out_full_n)
    begin
                ap_block_state1 <= ((ap_const_logic_0 = real_start) or (ap_done_reg = ap_const_logic_1) or (ap_const_logic_0 = img_rows_V_empty_n) or (ap_const_logic_0 = img_cols_V_empty_n) or (ap_const_logic_0 = img_rows_V_out_full_n) or (ap_const_logic_0 = img_cols_V_out_full_n));
    end process;

        ap_block_state5_pp1_stage0_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1));

    ap_block_state6_pp1_stage0_iter1_assign_proc : process(AXI_video_strm_V_data_V_0_vld_out, img_data_stream_0_V_full_n, img_data_stream_1_V_full_n, img_data_stream_2_V_full_n, exitcond_i_reg_446, ap_predicate_op73_read_state6)
    begin
                ap_block_state6_pp1_stage0_iter1 <= (((ap_const_logic_0 = AXI_video_strm_V_data_V_0_vld_out) and (ap_const_boolean_1 = ap_predicate_op73_read_state6)) or ((ap_const_lv1_0 = exitcond_i_reg_446) and (ap_const_logic_0 = img_data_stream_0_V_full_n)) or ((ap_const_lv1_0 = exitcond_i_reg_446) and (ap_const_logic_0 = img_data_stream_1_V_full_n)) or ((ap_const_lv1_0 = exitcond_i_reg_446) and (ap_const_logic_0 = img_data_stream_2_V_full_n)));
    end process;

        ap_block_state8_pp2_stage0_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1));

    ap_block_state9_pp2_stage0_iter1_assign_proc : process(AXI_video_strm_V_data_V_0_vld_out, eol_2_i_reg_282)
    begin
                ap_block_state9_pp2_stage0_iter1 <= ((ap_const_lv1_0 = eol_2_i_reg_282) and (ap_const_logic_0 = AXI_video_strm_V_data_V_0_vld_out));
    end process;


    ap_condition_535_assign_proc : process(ap_CS_fsm_pp1_stage0, ap_enable_reg_pp1_iter1, ap_block_pp1_stage0_flag00000000, exitcond_i_reg_446)
    begin
                ap_condition_535 <= ((ap_const_logic_1 = ap_CS_fsm_pp1_stage0) and (ap_const_logic_1 = ap_enable_reg_pp1_iter1) and (ap_block_pp1_stage0_flag00000000 = ap_const_boolean_0) and (ap_const_lv1_0 = exitcond_i_reg_446));
    end process;


    ap_done_assign_proc : process(ap_done_reg, exitcond7_i_fu_340_p2, ap_CS_fsm_state4)
    begin
        if (((ap_const_logic_1 = ap_CS_fsm_state4) and (ap_const_lv1_1 = exitcond7_i_fu_340_p2))) then 
            ap_done <= ap_const_logic_1;
        else 
            ap_done <= ap_done_reg;
        end if; 
    end process;

    ap_enable_pp1 <= (ap_idle_pp1 xor ap_const_logic_1);
    ap_enable_pp2 <= (ap_idle_pp2 xor ap_const_logic_1);

    ap_idle_assign_proc : process(real_start, ap_CS_fsm_state1)
    begin
        if (((ap_const_logic_0 = real_start) and (ap_const_logic_1 = ap_CS_fsm_state1))) then 
            ap_idle <= ap_const_logic_1;
        else 
            ap_idle <= ap_const_logic_0;
        end if; 
    end process;


    ap_idle_pp1_assign_proc : process(ap_enable_reg_pp1_iter1, ap_enable_reg_pp1_iter0)
    begin
        if (((ap_const_logic_0 = ap_enable_reg_pp1_iter0) and (ap_const_logic_0 = ap_enable_reg_pp1_iter1))) then 
            ap_idle_pp1 <= ap_const_logic_1;
        else 
            ap_idle_pp1 <= ap_const_logic_0;
        end if; 
    end process;


    ap_idle_pp2_assign_proc : process(ap_enable_reg_pp2_iter1, ap_enable_reg_pp2_iter0)
    begin
        if (((ap_const_logic_0 = ap_enable_reg_pp2_iter0) and (ap_const_logic_0 = ap_enable_reg_pp2_iter1))) then 
            ap_idle_pp2 <= ap_const_logic_1;
        else 
            ap_idle_pp2 <= ap_const_logic_0;
        end if; 
    end process;

    ap_phi_precharge_reg_pp1_iter1_axi_last_V_2_i_reg_257 <= "X";
    ap_phi_precharge_reg_pp1_iter1_p_Val2_s_reg_270 <= "XXXXXXXXXXXXXXXXXXXXXXXX";

    ap_predicate_op73_read_state6_assign_proc : process(exitcond_i_reg_446, brmerge_i_reg_455)
    begin
                ap_predicate_op73_read_state6 <= ((ap_const_lv1_0 = exitcond_i_reg_446) and (ap_const_lv1_0 = brmerge_i_reg_455));
    end process;

    ap_ready <= internal_ap_ready;

    axi_last_V_2_i_phi_fu_262_p4_assign_proc : process(AXI_video_strm_V_last_V_0_data_out, brmerge_i_reg_455, eol_reg_235, ap_phi_precharge_reg_pp1_iter1_axi_last_V_2_i_reg_257, ap_condition_535)
    begin
        if ((ap_condition_535 = ap_const_boolean_1)) then
            if ((ap_const_lv1_1 = brmerge_i_reg_455)) then 
                axi_last_V_2_i_phi_fu_262_p4 <= eol_reg_235;
            elsif ((ap_const_lv1_0 = brmerge_i_reg_455)) then 
                axi_last_V_2_i_phi_fu_262_p4 <= AXI_video_strm_V_last_V_0_data_out;
            else 
                axi_last_V_2_i_phi_fu_262_p4 <= ap_phi_precharge_reg_pp1_iter1_axi_last_V_2_i_reg_257;
            end if;
        else 
            axi_last_V_2_i_phi_fu_262_p4 <= ap_phi_precharge_reg_pp1_iter1_axi_last_V_2_i_reg_257;
        end if; 
    end process;

    brmerge_i_fu_369_p2 <= (sof_1_i_fu_110 or eol_i_phi_fu_227_p4);

    eol_2_i_phi_fu_285_p4_assign_proc : process(AXI_video_strm_V_last_V_0_data_out, ap_CS_fsm_pp2_stage0, ap_enable_reg_pp2_iter1, ap_block_pp2_stage0_flag00000000, eol_2_i_reg_282)
    begin
        if (((ap_const_logic_1 = ap_CS_fsm_pp2_stage0) and (ap_const_logic_1 = ap_enable_reg_pp2_iter1) and (ap_block_pp2_stage0_flag00000000 = ap_const_boolean_0) and (ap_const_lv1_0 = eol_2_i_reg_282))) then 
            eol_2_i_phi_fu_285_p4 <= AXI_video_strm_V_last_V_0_data_out;
        else 
            eol_2_i_phi_fu_285_p4 <= eol_2_i_reg_282;
        end if; 
    end process;


    eol_i_phi_fu_227_p4_assign_proc : process(ap_CS_fsm_pp1_stage0, ap_enable_reg_pp1_iter1, ap_block_pp1_stage0_flag00000000, exitcond_i_reg_446, eol_i_reg_223, axi_last_V_2_i_phi_fu_262_p4)
    begin
        if (((ap_const_logic_1 = ap_CS_fsm_pp1_stage0) and (ap_const_logic_1 = ap_enable_reg_pp1_iter1) and (ap_block_pp1_stage0_flag00000000 = ap_const_boolean_0) and (ap_const_lv1_0 = exitcond_i_reg_446))) then 
            eol_i_phi_fu_227_p4 <= axi_last_V_2_i_phi_fu_262_p4;
        else 
            eol_i_phi_fu_227_p4 <= eol_i_reg_223;
        end if; 
    end process;

    exitcond7_i_fu_340_p2 <= "1" when (t_V_cast_cast_i_fu_336_p1 = img_rows_V_read_reg_407) else "0";
    exitcond_i_fu_355_p2 <= "1" when (t_V_6_cast_cast_i_fu_351_p1 = img_cols_V_read_reg_412) else "0";
    i_V_fu_345_p2 <= std_logic_vector(unsigned(t_V_reg_201) + unsigned(ap_const_lv9_1));

    img_cols_V_blk_n_assign_proc : process(real_start, ap_done_reg, ap_CS_fsm_state1, img_cols_V_empty_n)
    begin
        if (((ap_const_logic_1 = ap_CS_fsm_state1) and not(((ap_const_logic_0 = real_start) or (ap_done_reg = ap_const_logic_1))))) then 
            img_cols_V_blk_n <= img_cols_V_empty_n;
        else 
            img_cols_V_blk_n <= ap_const_logic_1;
        end if; 
    end process;


    img_cols_V_out_blk_n_assign_proc : process(real_start, ap_done_reg, ap_CS_fsm_state1, img_cols_V_out_full_n)
    begin
        if (((ap_const_logic_1 = ap_CS_fsm_state1) and not(((ap_const_logic_0 = real_start) or (ap_done_reg = ap_const_logic_1))))) then 
            img_cols_V_out_blk_n <= img_cols_V_out_full_n;
        else 
            img_cols_V_out_blk_n <= ap_const_logic_1;
        end if; 
    end process;

    img_cols_V_out_din <= img_cols_V_dout;

    img_cols_V_out_write_assign_proc : process(real_start, ap_done_reg, ap_CS_fsm_state1, img_rows_V_empty_n, img_cols_V_empty_n, img_rows_V_out_full_n, img_cols_V_out_full_n)
    begin
        if (((ap_const_logic_1 = ap_CS_fsm_state1) and not(((ap_const_logic_0 = real_start) or (ap_done_reg = ap_const_logic_1) or (ap_const_logic_0 = img_rows_V_empty_n) or (ap_const_logic_0 = img_cols_V_empty_n) or (ap_const_logic_0 = img_rows_V_out_full_n) or (ap_const_logic_0 = img_cols_V_out_full_n))))) then 
            img_cols_V_out_write <= ap_const_logic_1;
        else 
            img_cols_V_out_write <= ap_const_logic_0;
        end if; 
    end process;


    img_cols_V_read_assign_proc : process(real_start, ap_done_reg, ap_CS_fsm_state1, img_rows_V_empty_n, img_cols_V_empty_n, img_rows_V_out_full_n, img_cols_V_out_full_n)
    begin
        if (((ap_const_logic_1 = ap_CS_fsm_state1) and not(((ap_const_logic_0 = real_start) or (ap_done_reg = ap_const_logic_1) or (ap_const_logic_0 = img_rows_V_empty_n) or (ap_const_logic_0 = img_cols_V_empty_n) or (ap_const_logic_0 = img_rows_V_out_full_n) or (ap_const_logic_0 = img_cols_V_out_full_n))))) then 
            img_cols_V_read <= ap_const_logic_1;
        else 
            img_cols_V_read <= ap_const_logic_0;
        end if; 
    end process;


    img_data_stream_0_V_blk_n_assign_proc : process(img_data_stream_0_V_full_n, ap_CS_fsm_pp1_stage0, ap_enable_reg_pp1_iter1, ap_block_pp1_stage0_flag00000000, exitcond_i_reg_446)
    begin
        if (((ap_const_logic_1 = ap_CS_fsm_pp1_stage0) and (ap_const_logic_1 = ap_enable_reg_pp1_iter1) and (ap_block_pp1_stage0_flag00000000 = ap_const_boolean_0) and (ap_const_lv1_0 = exitcond_i_reg_446))) then 
            img_data_stream_0_V_blk_n <= img_data_stream_0_V_full_n;
        else 
            img_data_stream_0_V_blk_n <= ap_const_logic_1;
        end if; 
    end process;

    img_data_stream_0_V_din <= p_Val2_s_phi_fu_274_p4(8 - 1 downto 0);

    img_data_stream_0_V_write_assign_proc : process(ap_CS_fsm_pp1_stage0, ap_enable_reg_pp1_iter1, exitcond_i_reg_446, ap_block_pp1_stage0_flag00011001)
    begin
        if (((ap_const_logic_1 = ap_CS_fsm_pp1_stage0) and (ap_const_logic_1 = ap_enable_reg_pp1_iter1) and (ap_const_lv1_0 = exitcond_i_reg_446) and (ap_block_pp1_stage0_flag00011001 = ap_const_boolean_0))) then 
            img_data_stream_0_V_write <= ap_const_logic_1;
        else 
            img_data_stream_0_V_write <= ap_const_logic_0;
        end if; 
    end process;


    img_data_stream_1_V_blk_n_assign_proc : process(img_data_stream_1_V_full_n, ap_CS_fsm_pp1_stage0, ap_enable_reg_pp1_iter1, ap_block_pp1_stage0_flag00000000, exitcond_i_reg_446)
    begin
        if (((ap_const_logic_1 = ap_CS_fsm_pp1_stage0) and (ap_const_logic_1 = ap_enable_reg_pp1_iter1) and (ap_block_pp1_stage0_flag00000000 = ap_const_boolean_0) and (ap_const_lv1_0 = exitcond_i_reg_446))) then 
            img_data_stream_1_V_blk_n <= img_data_stream_1_V_full_n;
        else 
            img_data_stream_1_V_blk_n <= ap_const_logic_1;
        end if; 
    end process;

    img_data_stream_1_V_din <= p_Val2_s_phi_fu_274_p4(15 downto 8);

    img_data_stream_1_V_write_assign_proc : process(ap_CS_fsm_pp1_stage0, ap_enable_reg_pp1_iter1, exitcond_i_reg_446, ap_block_pp1_stage0_flag00011001)
    begin
        if (((ap_const_logic_1 = ap_CS_fsm_pp1_stage0) and (ap_const_logic_1 = ap_enable_reg_pp1_iter1) and (ap_const_lv1_0 = exitcond_i_reg_446) and (ap_block_pp1_stage0_flag00011001 = ap_const_boolean_0))) then 
            img_data_stream_1_V_write <= ap_const_logic_1;
        else 
            img_data_stream_1_V_write <= ap_const_logic_0;
        end if; 
    end process;


    img_data_stream_2_V_blk_n_assign_proc : process(img_data_stream_2_V_full_n, ap_CS_fsm_pp1_stage0, ap_enable_reg_pp1_iter1, ap_block_pp1_stage0_flag00000000, exitcond_i_reg_446)
    begin
        if (((ap_const_logic_1 = ap_CS_fsm_pp1_stage0) and (ap_const_logic_1 = ap_enable_reg_pp1_iter1) and (ap_block_pp1_stage0_flag00000000 = ap_const_boolean_0) and (ap_const_lv1_0 = exitcond_i_reg_446))) then 
            img_data_stream_2_V_blk_n <= img_data_stream_2_V_full_n;
        else 
            img_data_stream_2_V_blk_n <= ap_const_logic_1;
        end if; 
    end process;

    img_data_stream_2_V_din <= p_Val2_s_phi_fu_274_p4(23 downto 16);

    img_data_stream_2_V_write_assign_proc : process(ap_CS_fsm_pp1_stage0, ap_enable_reg_pp1_iter1, exitcond_i_reg_446, ap_block_pp1_stage0_flag00011001)
    begin
        if (((ap_const_logic_1 = ap_CS_fsm_pp1_stage0) and (ap_const_logic_1 = ap_enable_reg_pp1_iter1) and (ap_const_lv1_0 = exitcond_i_reg_446) and (ap_block_pp1_stage0_flag00011001 = ap_const_boolean_0))) then 
            img_data_stream_2_V_write <= ap_const_logic_1;
        else 
            img_data_stream_2_V_write <= ap_const_logic_0;
        end if; 
    end process;


    img_rows_V_blk_n_assign_proc : process(real_start, ap_done_reg, ap_CS_fsm_state1, img_rows_V_empty_n)
    begin
        if (((ap_const_logic_1 = ap_CS_fsm_state1) and not(((ap_const_logic_0 = real_start) or (ap_done_reg = ap_const_logic_1))))) then 
            img_rows_V_blk_n <= img_rows_V_empty_n;
        else 
            img_rows_V_blk_n <= ap_const_logic_1;
        end if; 
    end process;


    img_rows_V_out_blk_n_assign_proc : process(real_start, ap_done_reg, ap_CS_fsm_state1, img_rows_V_out_full_n)
    begin
        if (((ap_const_logic_1 = ap_CS_fsm_state1) and not(((ap_const_logic_0 = real_start) or (ap_done_reg = ap_const_logic_1))))) then 
            img_rows_V_out_blk_n <= img_rows_V_out_full_n;
        else 
            img_rows_V_out_blk_n <= ap_const_logic_1;
        end if; 
    end process;

    img_rows_V_out_din <= img_rows_V_dout;

    img_rows_V_out_write_assign_proc : process(real_start, ap_done_reg, ap_CS_fsm_state1, img_rows_V_empty_n, img_cols_V_empty_n, img_rows_V_out_full_n, img_cols_V_out_full_n)
    begin
        if (((ap_const_logic_1 = ap_CS_fsm_state1) and not(((ap_const_logic_0 = real_start) or (ap_done_reg = ap_const_logic_1) or (ap_const_logic_0 = img_rows_V_empty_n) or (ap_const_logic_0 = img_cols_V_empty_n) or (ap_const_logic_0 = img_rows_V_out_full_n) or (ap_const_logic_0 = img_cols_V_out_full_n))))) then 
            img_rows_V_out_write <= ap_const_logic_1;
        else 
            img_rows_V_out_write <= ap_const_logic_0;
        end if; 
    end process;


    img_rows_V_read_assign_proc : process(real_start, ap_done_reg, ap_CS_fsm_state1, img_rows_V_empty_n, img_cols_V_empty_n, img_rows_V_out_full_n, img_cols_V_out_full_n)
    begin
        if (((ap_const_logic_1 = ap_CS_fsm_state1) and not(((ap_const_logic_0 = real_start) or (ap_done_reg = ap_const_logic_1) or (ap_const_logic_0 = img_rows_V_empty_n) or (ap_const_logic_0 = img_cols_V_empty_n) or (ap_const_logic_0 = img_rows_V_out_full_n) or (ap_const_logic_0 = img_cols_V_out_full_n))))) then 
            img_rows_V_read <= ap_const_logic_1;
        else 
            img_rows_V_read <= ap_const_logic_0;
        end if; 
    end process;


    internal_ap_ready_assign_proc : process(exitcond7_i_fu_340_p2, ap_CS_fsm_state4)
    begin
        if (((ap_const_logic_1 = ap_CS_fsm_state4) and (ap_const_lv1_1 = exitcond7_i_fu_340_p2))) then 
            internal_ap_ready <= ap_const_logic_1;
        else 
            internal_ap_ready <= ap_const_logic_0;
        end if; 
    end process;

    j_V_fu_360_p2 <= std_logic_vector(unsigned(t_V_6_reg_212) + unsigned(ap_const_lv10_1));

    p_Val2_s_phi_fu_274_p4_assign_proc : process(AXI_video_strm_V_data_V_0_data_out, brmerge_i_reg_455, axi_data_V_1_i_reg_246, ap_phi_precharge_reg_pp1_iter1_p_Val2_s_reg_270, ap_condition_535)
    begin
        if ((ap_condition_535 = ap_const_boolean_1)) then
            if ((ap_const_lv1_1 = brmerge_i_reg_455)) then 
                p_Val2_s_phi_fu_274_p4 <= axi_data_V_1_i_reg_246;
            elsif ((ap_const_lv1_0 = brmerge_i_reg_455)) then 
                p_Val2_s_phi_fu_274_p4 <= AXI_video_strm_V_data_V_0_data_out;
            else 
                p_Val2_s_phi_fu_274_p4 <= ap_phi_precharge_reg_pp1_iter1_p_Val2_s_reg_270;
            end if;
        else 
            p_Val2_s_phi_fu_274_p4 <= ap_phi_precharge_reg_pp1_iter1_p_Val2_s_reg_270;
        end if; 
    end process;


    real_start_assign_proc : process(ap_start, real_start_status_reg)
    begin
        if ((ap_const_logic_1 = real_start_status_reg)) then 
            real_start <= ap_const_logic_0;
        else 
            real_start <= ap_start;
        end if; 
    end process;

    start_out <= real_start;
    start_write <= (ap_start and start_control_reg);
    t_V_6_cast_cast_i_fu_351_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(t_V_6_reg_212),11));
    t_V_cast_cast_i_fu_336_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(t_V_reg_201),10));
    tmp_user_V_fu_327_p1 <= AXI_video_strm_V_user_V_0_data_out;

    video_in_TDATA_blk_n_assign_proc : process(AXI_video_strm_V_data_V_0_state, ap_CS_fsm_state2, ap_CS_fsm_pp1_stage0, ap_enable_reg_pp1_iter1, ap_block_pp1_stage0_flag00000000, exitcond_i_reg_446, brmerge_i_reg_455, ap_CS_fsm_pp2_stage0, ap_enable_reg_pp2_iter1, ap_block_pp2_stage0_flag00000000, eol_2_i_reg_282)
    begin
        if (((ap_const_logic_1 = ap_CS_fsm_state2) or ((ap_const_logic_1 = ap_CS_fsm_pp1_stage0) and (ap_const_logic_1 = ap_enable_reg_pp1_iter1) and (ap_block_pp1_stage0_flag00000000 = ap_const_boolean_0) and (ap_const_lv1_0 = exitcond_i_reg_446) and (ap_const_lv1_0 = brmerge_i_reg_455)) or ((ap_const_logic_1 = ap_CS_fsm_pp2_stage0) and (ap_const_logic_1 = ap_enable_reg_pp2_iter1) and (ap_block_pp2_stage0_flag00000000 = ap_const_boolean_0) and (ap_const_lv1_0 = eol_2_i_reg_282)))) then 
            video_in_TDATA_blk_n <= AXI_video_strm_V_data_V_0_state(0);
        else 
            video_in_TDATA_blk_n <= ap_const_logic_1;
        end if; 
    end process;

    video_in_TREADY <= AXI_video_strm_V_dest_V_0_state(1);
end behav;
