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-- IP VLNV: xilinx.com:module_ref:debounce:1.0
-- IP Revision: 1

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;

ENTITY design_1_debounce_0_0 IS
  PORT (
    button1 : IN STD_LOGIC;
    button2 : IN STD_LOGIC;
    clk : IN STD_LOGIC;
    out1 : OUT STD_LOGIC;
    out2n : OUT STD_LOGIC
  );
END design_1_debounce_0_0;

ARCHITECTURE design_1_debounce_0_0_arch OF design_1_debounce_0_0 IS
  ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
  ATTRIBUTE DowngradeIPIdentifiedWarnings OF design_1_debounce_0_0_arch: ARCHITECTURE IS "yes";
  COMPONENT debounce IS
    PORT (
      button1 : IN STD_LOGIC;
      button2 : IN STD_LOGIC;
      clk : IN STD_LOGIC;
      out1 : OUT STD_LOGIC;
      out2n : OUT STD_LOGIC
    );
  END COMPONENT debounce;
  ATTRIBUTE X_CORE_INFO : STRING;
  ATTRIBUTE X_CORE_INFO OF design_1_debounce_0_0_arch: ARCHITECTURE IS "debounce,Vivado 2017.2.1";
  ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
  ATTRIBUTE CHECK_LICENSE_TYPE OF design_1_debounce_0_0_arch : ARCHITECTURE IS "design_1_debounce_0_0,debounce,{}";
  ATTRIBUTE CORE_GENERATION_INFO : STRING;
  ATTRIBUTE CORE_GENERATION_INFO OF design_1_debounce_0_0_arch: ARCHITECTURE IS "design_1_debounce_0_0,debounce,{x_ipProduct=Vivado 2017.2.1,x_ipVendor=xilinx.com,x_ipLibrary=module_ref,x_ipName=debounce,x_ipVersion=1.0,x_ipCoreRevision=1,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED}";
  ATTRIBUTE X_INTERFACE_INFO : STRING;
  ATTRIBUTE X_INTERFACE_INFO OF clk: SIGNAL IS "xilinx.com:signal:clock:1.0 clk CLK";
  ATTRIBUTE X_INTERFACE_INFO OF out2n: SIGNAL IS "xilinx.com:signal:reset:1.0 out2n RST";
BEGIN
  U0 : debounce
    PORT MAP (
      button1 => button1,
      button2 => button2,
      clk => clk,
      out1 => out1,
      out2n => out2n
    );
END design_1_debounce_0_0_arch;
