// ==============================================================
// RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2017.2
// Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved.
// 
// ===========================================================

`timescale 1 ns / 1 ps 

module Duplicate (
        ap_clk,
        ap_rst,
        ap_start,
        ap_done,
        ap_continue,
        ap_idle,
        ap_ready,
        src_data_stream_0_V_dout,
        src_data_stream_0_V_empty_n,
        src_data_stream_0_V_read,
        src_data_stream_1_V_dout,
        src_data_stream_1_V_empty_n,
        src_data_stream_1_V_read,
        src_data_stream_2_V_dout,
        src_data_stream_2_V_empty_n,
        src_data_stream_2_V_read,
        dst1_data_stream_0_V,
        dst1_data_stream_0_V_ap_vld,
        dst1_data_stream_1_V,
        dst1_data_stream_1_V_ap_vld,
        dst1_data_stream_2_V,
        dst1_data_stream_2_V_ap_vld,
        dst2_data_stream_0_V_din,
        dst2_data_stream_0_V_full_n,
        dst2_data_stream_0_V_write,
        dst2_data_stream_1_V_din,
        dst2_data_stream_1_V_full_n,
        dst2_data_stream_1_V_write,
        dst2_data_stream_2_V_din,
        dst2_data_stream_2_V_full_n,
        dst2_data_stream_2_V_write
);

parameter    ap_ST_fsm_state1 = 4'd1;
parameter    ap_ST_fsm_state2 = 4'd2;
parameter    ap_ST_fsm_pp0_stage0 = 4'd4;
parameter    ap_ST_fsm_state5 = 4'd8;

input   ap_clk;
input   ap_rst;
input   ap_start;
output   ap_done;
input   ap_continue;
output   ap_idle;
output   ap_ready;
input  [7:0] src_data_stream_0_V_dout;
input   src_data_stream_0_V_empty_n;
output   src_data_stream_0_V_read;
input  [7:0] src_data_stream_1_V_dout;
input   src_data_stream_1_V_empty_n;
output   src_data_stream_1_V_read;
input  [7:0] src_data_stream_2_V_dout;
input   src_data_stream_2_V_empty_n;
output   src_data_stream_2_V_read;
output  [7:0] dst1_data_stream_0_V;
output   dst1_data_stream_0_V_ap_vld;
output  [7:0] dst1_data_stream_1_V;
output   dst1_data_stream_1_V_ap_vld;
output  [7:0] dst1_data_stream_2_V;
output   dst1_data_stream_2_V_ap_vld;
output  [7:0] dst2_data_stream_0_V_din;
input   dst2_data_stream_0_V_full_n;
output   dst2_data_stream_0_V_write;
output  [7:0] dst2_data_stream_1_V_din;
input   dst2_data_stream_1_V_full_n;
output   dst2_data_stream_1_V_write;
output  [7:0] dst2_data_stream_2_V_din;
input   dst2_data_stream_2_V_full_n;
output   dst2_data_stream_2_V_write;

reg ap_done;
reg ap_idle;
reg ap_ready;
reg src_data_stream_0_V_read;
reg src_data_stream_1_V_read;
reg src_data_stream_2_V_read;
reg[7:0] dst1_data_stream_0_V;
reg dst1_data_stream_0_V_ap_vld;
reg[7:0] dst1_data_stream_1_V;
reg dst1_data_stream_1_V_ap_vld;
reg[7:0] dst1_data_stream_2_V;
reg dst1_data_stream_2_V_ap_vld;
reg dst2_data_stream_0_V_write;
reg dst2_data_stream_1_V_write;
reg dst2_data_stream_2_V_write;

reg    ap_done_reg;
(* fsm_encoding = "none" *) reg   [3:0] ap_CS_fsm;
wire    ap_CS_fsm_state1;
reg    src_data_stream_0_V_blk_n;
wire    ap_CS_fsm_pp0_stage0;
reg    ap_enable_reg_pp0_iter1;
wire    ap_block_pp0_stage0_flag00000000;
reg   [0:0] exitcond_reg_197;
reg    src_data_stream_1_V_blk_n;
reg    src_data_stream_2_V_blk_n;
reg    dst2_data_stream_0_V_blk_n;
reg    dst2_data_stream_1_V_blk_n;
reg    dst2_data_stream_2_V_blk_n;
reg   [9:0] t_V_5_reg_153;
wire   [0:0] exitcond6_fu_164_p2;
wire    ap_CS_fsm_state2;
wire   [8:0] i_V_fu_170_p2;
reg   [8:0] i_V_reg_192;
wire   [0:0] exitcond_fu_176_p2;
wire    ap_block_state3_pp0_stage0_iter0;
reg    ap_block_state4_pp0_stage0_iter1;
reg    ap_block_pp0_stage0_flag00011001;
wire   [9:0] j_V_fu_182_p2;
reg    ap_enable_reg_pp0_iter0;
reg    ap_block_pp0_stage0_flag00011011;
reg    ap_condition_pp0_exit_iter0_state3;
reg   [8:0] t_V_reg_142;
reg    ap_block_state1;
wire    ap_CS_fsm_state5;
reg    ap_block_pp0_stage0_flag00001001;
reg   [7:0] dst1_data_stream_0_V_preg;
reg   [7:0] dst1_data_stream_1_V_preg;
reg   [7:0] dst1_data_stream_2_V_preg;
reg   [3:0] ap_NS_fsm;
reg    ap_idle_pp0;
wire    ap_enable_pp0;

// power-on initialization
initial begin
#0 ap_done_reg = 1'b0;
#0 ap_CS_fsm = 4'd1;
#0 ap_enable_reg_pp0_iter1 = 1'b0;
#0 ap_enable_reg_pp0_iter0 = 1'b0;
#0 dst1_data_stream_0_V_preg = 8'd0;
#0 dst1_data_stream_1_V_preg = 8'd0;
#0 dst1_data_stream_2_V_preg = 8'd0;
end

always @ (posedge ap_clk) begin
    if (ap_rst == 1'b1) begin
        ap_CS_fsm <= ap_ST_fsm_state1;
    end else begin
        ap_CS_fsm <= ap_NS_fsm;
    end
end

always @ (posedge ap_clk) begin
    if (ap_rst == 1'b1) begin
        ap_done_reg <= 1'b0;
    end else begin
        if ((1'b1 == ap_continue)) begin
            ap_done_reg <= 1'b0;
        end else if (((1'b1 == ap_CS_fsm_state2) & (exitcond6_fu_164_p2 == 1'd1))) begin
            ap_done_reg <= 1'b1;
        end
    end
end

always @ (posedge ap_clk) begin
    if (ap_rst == 1'b1) begin
        ap_enable_reg_pp0_iter0 <= 1'b0;
    end else begin
        if (((1'b1 == ap_CS_fsm_pp0_stage0) & (ap_block_pp0_stage0_flag00011011 == 1'b0) & (1'b1 == ap_condition_pp0_exit_iter0_state3))) begin
            ap_enable_reg_pp0_iter0 <= 1'b0;
        end else if (((1'b1 == ap_CS_fsm_state2) & (1'd0 == exitcond6_fu_164_p2))) begin
            ap_enable_reg_pp0_iter0 <= 1'b1;
        end
    end
end

always @ (posedge ap_clk) begin
    if (ap_rst == 1'b1) begin
        ap_enable_reg_pp0_iter1 <= 1'b0;
    end else begin
        if (((ap_block_pp0_stage0_flag00011011 == 1'b0) & (1'b1 == ap_condition_pp0_exit_iter0_state3))) begin
            ap_enable_reg_pp0_iter1 <= (ap_condition_pp0_exit_iter0_state3 ^ 1'b1);
        end else if ((ap_block_pp0_stage0_flag00011011 == 1'b0)) begin
            ap_enable_reg_pp0_iter1 <= ap_enable_reg_pp0_iter0;
        end else if (((1'b1 == ap_CS_fsm_state2) & (1'd0 == exitcond6_fu_164_p2))) begin
            ap_enable_reg_pp0_iter1 <= 1'b0;
        end
    end
end

always @ (posedge ap_clk) begin
    if (ap_rst == 1'b1) begin
        dst1_data_stream_0_V_preg <= 8'd0;
    end else begin
        if (((1'b1 == ap_CS_fsm_pp0_stage0) & (1'b1 == ap_enable_reg_pp0_iter1) & (exitcond_reg_197 == 1'd0) & (ap_block_pp0_stage0_flag00001001 == 1'b0))) begin
            dst1_data_stream_0_V_preg <= src_data_stream_0_V_dout;
        end
    end
end

always @ (posedge ap_clk) begin
    if (ap_rst == 1'b1) begin
        dst1_data_stream_1_V_preg <= 8'd0;
    end else begin
        if (((1'b1 == ap_CS_fsm_pp0_stage0) & (1'b1 == ap_enable_reg_pp0_iter1) & (exitcond_reg_197 == 1'd0) & (ap_block_pp0_stage0_flag00001001 == 1'b0))) begin
            dst1_data_stream_1_V_preg <= src_data_stream_1_V_dout;
        end
    end
end

always @ (posedge ap_clk) begin
    if (ap_rst == 1'b1) begin
        dst1_data_stream_2_V_preg <= 8'd0;
    end else begin
        if (((1'b1 == ap_CS_fsm_pp0_stage0) & (1'b1 == ap_enable_reg_pp0_iter1) & (exitcond_reg_197 == 1'd0) & (ap_block_pp0_stage0_flag00001001 == 1'b0))) begin
            dst1_data_stream_2_V_preg <= src_data_stream_2_V_dout;
        end
    end
end

always @ (posedge ap_clk) begin
    if (((1'b1 == ap_CS_fsm_pp0_stage0) & (ap_block_pp0_stage0_flag00011001 == 1'b0) & (1'b1 == ap_enable_reg_pp0_iter0) & (1'd0 == exitcond_fu_176_p2))) begin
        t_V_5_reg_153 <= j_V_fu_182_p2;
    end else if (((1'b1 == ap_CS_fsm_state2) & (1'd0 == exitcond6_fu_164_p2))) begin
        t_V_5_reg_153 <= 10'd0;
    end
end

always @ (posedge ap_clk) begin
    if ((1'b1 == ap_CS_fsm_state5)) begin
        t_V_reg_142 <= i_V_reg_192;
    end else if (((1'b1 == ap_CS_fsm_state1) & ~((1'b0 == ap_start) | (ap_done_reg == 1'b1)))) begin
        t_V_reg_142 <= 9'd0;
    end
end

always @ (posedge ap_clk) begin
    if (((1'b1 == ap_CS_fsm_pp0_stage0) & (ap_block_pp0_stage0_flag00011001 == 1'b0))) begin
        exitcond_reg_197 <= exitcond_fu_176_p2;
    end
end

always @ (posedge ap_clk) begin
    if ((1'b1 == ap_CS_fsm_state2)) begin
        i_V_reg_192 <= i_V_fu_170_p2;
    end
end

always @ (*) begin
    if ((exitcond_fu_176_p2 == 1'd1)) begin
        ap_condition_pp0_exit_iter0_state3 = 1'b1;
    end else begin
        ap_condition_pp0_exit_iter0_state3 = 1'b0;
    end
end

always @ (*) begin
    if (((1'b1 == ap_CS_fsm_state2) & (exitcond6_fu_164_p2 == 1'd1))) begin
        ap_done = 1'b1;
    end else begin
        ap_done = ap_done_reg;
    end
end

always @ (*) begin
    if (((1'b0 == ap_start) & (1'b1 == ap_CS_fsm_state1))) begin
        ap_idle = 1'b1;
    end else begin
        ap_idle = 1'b0;
    end
end

always @ (*) begin
    if (((1'b0 == ap_enable_reg_pp0_iter0) & (1'b0 == ap_enable_reg_pp0_iter1))) begin
        ap_idle_pp0 = 1'b1;
    end else begin
        ap_idle_pp0 = 1'b0;
    end
end

always @ (*) begin
    if (((1'b1 == ap_CS_fsm_state2) & (exitcond6_fu_164_p2 == 1'd1))) begin
        ap_ready = 1'b1;
    end else begin
        ap_ready = 1'b0;
    end
end

always @ (*) begin
    if (((1'b1 == ap_CS_fsm_pp0_stage0) & (1'b1 == ap_enable_reg_pp0_iter1) & (exitcond_reg_197 == 1'd0) & (ap_block_pp0_stage0_flag00001001 == 1'b0))) begin
        dst1_data_stream_0_V = src_data_stream_0_V_dout;
    end else begin
        dst1_data_stream_0_V = dst1_data_stream_0_V_preg;
    end
end

always @ (*) begin
    if (((1'b1 == ap_CS_fsm_pp0_stage0) & (1'b1 == ap_enable_reg_pp0_iter1) & (exitcond_reg_197 == 1'd0) & (ap_block_pp0_stage0_flag00001001 == 1'b0))) begin
        dst1_data_stream_0_V_ap_vld = 1'b1;
    end else begin
        dst1_data_stream_0_V_ap_vld = 1'b0;
    end
end

always @ (*) begin
    if (((1'b1 == ap_CS_fsm_pp0_stage0) & (1'b1 == ap_enable_reg_pp0_iter1) & (exitcond_reg_197 == 1'd0) & (ap_block_pp0_stage0_flag00001001 == 1'b0))) begin
        dst1_data_stream_1_V = src_data_stream_1_V_dout;
    end else begin
        dst1_data_stream_1_V = dst1_data_stream_1_V_preg;
    end
end

always @ (*) begin
    if (((1'b1 == ap_CS_fsm_pp0_stage0) & (1'b1 == ap_enable_reg_pp0_iter1) & (exitcond_reg_197 == 1'd0) & (ap_block_pp0_stage0_flag00001001 == 1'b0))) begin
        dst1_data_stream_1_V_ap_vld = 1'b1;
    end else begin
        dst1_data_stream_1_V_ap_vld = 1'b0;
    end
end

always @ (*) begin
    if (((1'b1 == ap_CS_fsm_pp0_stage0) & (1'b1 == ap_enable_reg_pp0_iter1) & (exitcond_reg_197 == 1'd0) & (ap_block_pp0_stage0_flag00001001 == 1'b0))) begin
        dst1_data_stream_2_V = src_data_stream_2_V_dout;
    end else begin
        dst1_data_stream_2_V = dst1_data_stream_2_V_preg;
    end
end

always @ (*) begin
    if (((1'b1 == ap_CS_fsm_pp0_stage0) & (1'b1 == ap_enable_reg_pp0_iter1) & (exitcond_reg_197 == 1'd0) & (ap_block_pp0_stage0_flag00001001 == 1'b0))) begin
        dst1_data_stream_2_V_ap_vld = 1'b1;
    end else begin
        dst1_data_stream_2_V_ap_vld = 1'b0;
    end
end

always @ (*) begin
    if (((1'b1 == ap_CS_fsm_pp0_stage0) & (1'b1 == ap_enable_reg_pp0_iter1) & (ap_block_pp0_stage0_flag00000000 == 1'b0) & (exitcond_reg_197 == 1'd0))) begin
        dst2_data_stream_0_V_blk_n = dst2_data_stream_0_V_full_n;
    end else begin
        dst2_data_stream_0_V_blk_n = 1'b1;
    end
end

always @ (*) begin
    if (((1'b1 == ap_CS_fsm_pp0_stage0) & (1'b1 == ap_enable_reg_pp0_iter1) & (exitcond_reg_197 == 1'd0) & (ap_block_pp0_stage0_flag00011001 == 1'b0))) begin
        dst2_data_stream_0_V_write = 1'b1;
    end else begin
        dst2_data_stream_0_V_write = 1'b0;
    end
end

always @ (*) begin
    if (((1'b1 == ap_CS_fsm_pp0_stage0) & (1'b1 == ap_enable_reg_pp0_iter1) & (ap_block_pp0_stage0_flag00000000 == 1'b0) & (exitcond_reg_197 == 1'd0))) begin
        dst2_data_stream_1_V_blk_n = dst2_data_stream_1_V_full_n;
    end else begin
        dst2_data_stream_1_V_blk_n = 1'b1;
    end
end

always @ (*) begin
    if (((1'b1 == ap_CS_fsm_pp0_stage0) & (1'b1 == ap_enable_reg_pp0_iter1) & (exitcond_reg_197 == 1'd0) & (ap_block_pp0_stage0_flag00011001 == 1'b0))) begin
        dst2_data_stream_1_V_write = 1'b1;
    end else begin
        dst2_data_stream_1_V_write = 1'b0;
    end
end

always @ (*) begin
    if (((1'b1 == ap_CS_fsm_pp0_stage0) & (1'b1 == ap_enable_reg_pp0_iter1) & (ap_block_pp0_stage0_flag00000000 == 1'b0) & (exitcond_reg_197 == 1'd0))) begin
        dst2_data_stream_2_V_blk_n = dst2_data_stream_2_V_full_n;
    end else begin
        dst2_data_stream_2_V_blk_n = 1'b1;
    end
end

always @ (*) begin
    if (((1'b1 == ap_CS_fsm_pp0_stage0) & (1'b1 == ap_enable_reg_pp0_iter1) & (exitcond_reg_197 == 1'd0) & (ap_block_pp0_stage0_flag00011001 == 1'b0))) begin
        dst2_data_stream_2_V_write = 1'b1;
    end else begin
        dst2_data_stream_2_V_write = 1'b0;
    end
end

always @ (*) begin
    if (((1'b1 == ap_CS_fsm_pp0_stage0) & (1'b1 == ap_enable_reg_pp0_iter1) & (ap_block_pp0_stage0_flag00000000 == 1'b0) & (exitcond_reg_197 == 1'd0))) begin
        src_data_stream_0_V_blk_n = src_data_stream_0_V_empty_n;
    end else begin
        src_data_stream_0_V_blk_n = 1'b1;
    end
end

always @ (*) begin
    if (((1'b1 == ap_CS_fsm_pp0_stage0) & (1'b1 == ap_enable_reg_pp0_iter1) & (exitcond_reg_197 == 1'd0) & (ap_block_pp0_stage0_flag00011001 == 1'b0))) begin
        src_data_stream_0_V_read = 1'b1;
    end else begin
        src_data_stream_0_V_read = 1'b0;
    end
end

always @ (*) begin
    if (((1'b1 == ap_CS_fsm_pp0_stage0) & (1'b1 == ap_enable_reg_pp0_iter1) & (ap_block_pp0_stage0_flag00000000 == 1'b0) & (exitcond_reg_197 == 1'd0))) begin
        src_data_stream_1_V_blk_n = src_data_stream_1_V_empty_n;
    end else begin
        src_data_stream_1_V_blk_n = 1'b1;
    end
end

always @ (*) begin
    if (((1'b1 == ap_CS_fsm_pp0_stage0) & (1'b1 == ap_enable_reg_pp0_iter1) & (exitcond_reg_197 == 1'd0) & (ap_block_pp0_stage0_flag00011001 == 1'b0))) begin
        src_data_stream_1_V_read = 1'b1;
    end else begin
        src_data_stream_1_V_read = 1'b0;
    end
end

always @ (*) begin
    if (((1'b1 == ap_CS_fsm_pp0_stage0) & (1'b1 == ap_enable_reg_pp0_iter1) & (ap_block_pp0_stage0_flag00000000 == 1'b0) & (exitcond_reg_197 == 1'd0))) begin
        src_data_stream_2_V_blk_n = src_data_stream_2_V_empty_n;
    end else begin
        src_data_stream_2_V_blk_n = 1'b1;
    end
end

always @ (*) begin
    if (((1'b1 == ap_CS_fsm_pp0_stage0) & (1'b1 == ap_enable_reg_pp0_iter1) & (exitcond_reg_197 == 1'd0) & (ap_block_pp0_stage0_flag00011001 == 1'b0))) begin
        src_data_stream_2_V_read = 1'b1;
    end else begin
        src_data_stream_2_V_read = 1'b0;
    end
end

always @ (*) begin
    case (ap_CS_fsm)
        ap_ST_fsm_state1 : begin
            if (((1'b1 == ap_CS_fsm_state1) & ~((1'b0 == ap_start) | (ap_done_reg == 1'b1)))) begin
                ap_NS_fsm = ap_ST_fsm_state2;
            end else begin
                ap_NS_fsm = ap_ST_fsm_state1;
            end
        end
        ap_ST_fsm_state2 : begin
            if (((1'b1 == ap_CS_fsm_state2) & (exitcond6_fu_164_p2 == 1'd1))) begin
                ap_NS_fsm = ap_ST_fsm_state1;
            end else begin
                ap_NS_fsm = ap_ST_fsm_pp0_stage0;
            end
        end
        ap_ST_fsm_pp0_stage0 : begin
            if (~((1'b1 == ap_enable_reg_pp0_iter0) & (ap_block_pp0_stage0_flag00011011 == 1'b0) & (exitcond_fu_176_p2 == 1'd1))) begin
                ap_NS_fsm = ap_ST_fsm_pp0_stage0;
            end else if (((1'b1 == ap_enable_reg_pp0_iter0) & (ap_block_pp0_stage0_flag00011011 == 1'b0) & (exitcond_fu_176_p2 == 1'd1))) begin
                ap_NS_fsm = ap_ST_fsm_state5;
            end else begin
                ap_NS_fsm = ap_ST_fsm_pp0_stage0;
            end
        end
        ap_ST_fsm_state5 : begin
            ap_NS_fsm = ap_ST_fsm_state2;
        end
        default : begin
            ap_NS_fsm = 'bx;
        end
    endcase
end

assign ap_CS_fsm_pp0_stage0 = ap_CS_fsm[32'd2];

assign ap_CS_fsm_state1 = ap_CS_fsm[32'd0];

assign ap_CS_fsm_state2 = ap_CS_fsm[32'd1];

assign ap_CS_fsm_state5 = ap_CS_fsm[32'd3];

assign ap_block_pp0_stage0_flag00000000 = ~(1'b1 == 1'b1);

always @ (*) begin
    ap_block_pp0_stage0_flag00001001 = ((1'b1 == ap_enable_reg_pp0_iter1) & (((exitcond_reg_197 == 1'd0) & (1'b0 == src_data_stream_0_V_empty_n)) | ((exitcond_reg_197 == 1'd0) & (1'b0 == src_data_stream_1_V_empty_n)) | ((exitcond_reg_197 == 1'd0) & (1'b0 == src_data_stream_2_V_empty_n)) | ((exitcond_reg_197 == 1'd0) & (1'b0 == dst2_data_stream_0_V_full_n)) | ((exitcond_reg_197 == 1'd0) & (1'b0 == dst2_data_stream_1_V_full_n)) | ((exitcond_reg_197 == 1'd0) & (1'b0 == dst2_data_stream_2_V_full_n))));
end

always @ (*) begin
    ap_block_pp0_stage0_flag00011001 = ((1'b1 == ap_enable_reg_pp0_iter1) & (((exitcond_reg_197 == 1'd0) & (1'b0 == src_data_stream_0_V_empty_n)) | ((exitcond_reg_197 == 1'd0) & (1'b0 == src_data_stream_1_V_empty_n)) | ((exitcond_reg_197 == 1'd0) & (1'b0 == src_data_stream_2_V_empty_n)) | ((exitcond_reg_197 == 1'd0) & (1'b0 == dst2_data_stream_0_V_full_n)) | ((exitcond_reg_197 == 1'd0) & (1'b0 == dst2_data_stream_1_V_full_n)) | ((exitcond_reg_197 == 1'd0) & (1'b0 == dst2_data_stream_2_V_full_n))));
end

always @ (*) begin
    ap_block_pp0_stage0_flag00011011 = ((1'b1 == ap_enable_reg_pp0_iter1) & (((exitcond_reg_197 == 1'd0) & (1'b0 == src_data_stream_0_V_empty_n)) | ((exitcond_reg_197 == 1'd0) & (1'b0 == src_data_stream_1_V_empty_n)) | ((exitcond_reg_197 == 1'd0) & (1'b0 == src_data_stream_2_V_empty_n)) | ((exitcond_reg_197 == 1'd0) & (1'b0 == dst2_data_stream_0_V_full_n)) | ((exitcond_reg_197 == 1'd0) & (1'b0 == dst2_data_stream_1_V_full_n)) | ((exitcond_reg_197 == 1'd0) & (1'b0 == dst2_data_stream_2_V_full_n))));
end

always @ (*) begin
    ap_block_state1 = ((1'b0 == ap_start) | (ap_done_reg == 1'b1));
end

assign ap_block_state3_pp0_stage0_iter0 = ~(1'b1 == 1'b1);

always @ (*) begin
    ap_block_state4_pp0_stage0_iter1 = (((exitcond_reg_197 == 1'd0) & (1'b0 == src_data_stream_0_V_empty_n)) | ((exitcond_reg_197 == 1'd0) & (1'b0 == src_data_stream_1_V_empty_n)) | ((exitcond_reg_197 == 1'd0) & (1'b0 == src_data_stream_2_V_empty_n)) | ((exitcond_reg_197 == 1'd0) & (1'b0 == dst2_data_stream_0_V_full_n)) | ((exitcond_reg_197 == 1'd0) & (1'b0 == dst2_data_stream_1_V_full_n)) | ((exitcond_reg_197 == 1'd0) & (1'b0 == dst2_data_stream_2_V_full_n)));
end

assign ap_enable_pp0 = (ap_idle_pp0 ^ 1'b1);

assign dst2_data_stream_0_V_din = src_data_stream_0_V_dout;

assign dst2_data_stream_1_V_din = src_data_stream_1_V_dout;

assign dst2_data_stream_2_V_din = src_data_stream_2_V_dout;

assign exitcond6_fu_164_p2 = ((t_V_reg_142 == 9'd480) ? 1'b1 : 1'b0);

assign exitcond_fu_176_p2 = ((t_V_5_reg_153 == 10'd640) ? 1'b1 : 1'b0);

assign i_V_fu_170_p2 = (t_V_reg_142 + 9'd1);

assign j_V_fu_182_p2 = (t_V_5_reg_153 + 10'd1);

endmodule //Duplicate
