-- ==============================================================
-- RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2017.2
-- Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved.
-- 
-- ===========================================================

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;

entity design_1_v_frmbuf_rd_0_0_MultiPixStream2AXIvi is
port (
    ap_clk : IN STD_LOGIC;
    ap_rst : IN STD_LOGIC;
    ap_start : IN STD_LOGIC;
    ap_done : OUT STD_LOGIC;
    ap_continue : IN STD_LOGIC;
    ap_idle : OUT STD_LOGIC;
    ap_ready : OUT STD_LOGIC;
    StrmMPix_V_val_0_V_dout : IN STD_LOGIC_VECTOR (7 downto 0);
    StrmMPix_V_val_0_V_empty_n : IN STD_LOGIC;
    StrmMPix_V_val_0_V_read : OUT STD_LOGIC;
    StrmMPix_V_val_1_V_dout : IN STD_LOGIC_VECTOR (7 downto 0);
    StrmMPix_V_val_1_V_empty_n : IN STD_LOGIC;
    StrmMPix_V_val_1_V_read : OUT STD_LOGIC;
    StrmMPix_V_val_2_V_dout : IN STD_LOGIC_VECTOR (7 downto 0);
    StrmMPix_V_val_2_V_empty_n : IN STD_LOGIC;
    StrmMPix_V_val_2_V_read : OUT STD_LOGIC;
    m_axis_video_TDATA : OUT STD_LOGIC_VECTOR (23 downto 0);
    m_axis_video_TVALID : OUT STD_LOGIC;
    m_axis_video_TREADY : IN STD_LOGIC;
    m_axis_video_TKEEP : OUT STD_LOGIC_VECTOR (2 downto 0);
    m_axis_video_TSTRB : OUT STD_LOGIC_VECTOR (2 downto 0);
    m_axis_video_TUSER : OUT STD_LOGIC_VECTOR (0 downto 0);
    m_axis_video_TLAST : OUT STD_LOGIC_VECTOR (0 downto 0);
    m_axis_video_TID : OUT STD_LOGIC_VECTOR (0 downto 0);
    m_axis_video_TDEST : OUT STD_LOGIC_VECTOR (0 downto 0);
    HwReg_height_cast9_loc_dout : IN STD_LOGIC_VECTOR (8 downto 0);
    HwReg_height_cast9_loc_empty_n : IN STD_LOGIC;
    HwReg_height_cast9_loc_read : OUT STD_LOGIC;
    HwReg_width : IN STD_LOGIC_VECTOR (15 downto 0);
    tmp_4_loc_dout : IN STD_LOGIC_VECTOR (1 downto 0);
    tmp_4_loc_empty_n : IN STD_LOGIC;
    tmp_4_loc_read : OUT STD_LOGIC );
end;


architecture behav of design_1_v_frmbuf_rd_0_0_MultiPixStream2AXIvi is 
    constant ap_const_logic_1 : STD_LOGIC := '1';
    constant ap_const_logic_0 : STD_LOGIC := '0';
    constant ap_ST_fsm_state1 : STD_LOGIC_VECTOR (6 downto 0) := "0000001";
    constant ap_ST_fsm_state2 : STD_LOGIC_VECTOR (6 downto 0) := "0000010";
    constant ap_ST_fsm_state3 : STD_LOGIC_VECTOR (6 downto 0) := "0000100";
    constant ap_ST_fsm_state4 : STD_LOGIC_VECTOR (6 downto 0) := "0001000";
    constant ap_ST_fsm_state5 : STD_LOGIC_VECTOR (6 downto 0) := "0010000";
    constant ap_ST_fsm_pp0_stage0 : STD_LOGIC_VECTOR (6 downto 0) := "0100000";
    constant ap_ST_fsm_state9 : STD_LOGIC_VECTOR (6 downto 0) := "1000000";
    constant ap_const_lv32_0 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000000";
    constant ap_const_boolean_1 : BOOLEAN := true;
    constant ap_const_lv1_0 : STD_LOGIC_VECTOR (0 downto 0) := "0";
    constant ap_const_lv1_1 : STD_LOGIC_VECTOR (0 downto 0) := "1";
    constant ap_const_lv2_0 : STD_LOGIC_VECTOR (1 downto 0) := "00";
    constant ap_const_lv2_2 : STD_LOGIC_VECTOR (1 downto 0) := "10";
    constant ap_const_lv2_3 : STD_LOGIC_VECTOR (1 downto 0) := "11";
    constant ap_const_lv2_1 : STD_LOGIC_VECTOR (1 downto 0) := "01";
    constant ap_const_lv32_5 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000101";
    constant ap_const_boolean_0 : BOOLEAN := false;
    constant ap_const_lv32_1 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000001";
    constant ap_const_lv32_2 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000010";
    constant ap_const_lv32_3 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000011";
    constant ap_const_lv32_4 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000100";
    constant ap_const_lv9_0 : STD_LOGIC_VECTOR (8 downto 0) := "000000000";
    constant ap_const_lv32_6 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000110";
    constant ap_const_lv10_0 : STD_LOGIC_VECTOR (9 downto 0) := "0000000000";
    constant ap_const_lv3_7 : STD_LOGIC_VECTOR (2 downto 0) := "111";
    constant ap_const_lv3_0 : STD_LOGIC_VECTOR (2 downto 0) := "000";
    constant ap_const_lv11_7FF : STD_LOGIC_VECTOR (10 downto 0) := "11111111111";
    constant ap_const_lv9_1 : STD_LOGIC_VECTOR (8 downto 0) := "000000001";
    constant ap_const_lv10_1 : STD_LOGIC_VECTOR (9 downto 0) := "0000000001";

    signal ap_done_reg : STD_LOGIC := '0';
    signal ap_CS_fsm : STD_LOGIC_VECTOR (6 downto 0) := "0000001";
    attribute fsm_encoding : string;
    attribute fsm_encoding of ap_CS_fsm : signal is "none";
    signal ap_CS_fsm_state1 : STD_LOGIC;
    attribute fsm_encoding of ap_CS_fsm_state1 : signal is "none";
    signal AXI_video_strm_V_data_V_1_data_out : STD_LOGIC_VECTOR (23 downto 0);
    signal AXI_video_strm_V_data_V_1_vld_in : STD_LOGIC;
    signal AXI_video_strm_V_data_V_1_vld_out : STD_LOGIC;
    signal AXI_video_strm_V_data_V_1_ack_in : STD_LOGIC;
    signal AXI_video_strm_V_data_V_1_ack_out : STD_LOGIC;
    signal AXI_video_strm_V_data_V_1_payload_A : STD_LOGIC_VECTOR (23 downto 0);
    signal AXI_video_strm_V_data_V_1_payload_B : STD_LOGIC_VECTOR (23 downto 0);
    signal AXI_video_strm_V_data_V_1_sel_rd : STD_LOGIC := '0';
    signal AXI_video_strm_V_data_V_1_sel_wr : STD_LOGIC := '0';
    signal AXI_video_strm_V_data_V_1_sel : STD_LOGIC;
    signal AXI_video_strm_V_data_V_1_load_A : STD_LOGIC;
    signal AXI_video_strm_V_data_V_1_load_B : STD_LOGIC;
    signal AXI_video_strm_V_data_V_1_state : STD_LOGIC_VECTOR (1 downto 0) := "00";
    signal AXI_video_strm_V_data_V_1_state_cmp_full : STD_LOGIC;
    signal AXI_video_strm_V_keep_V_1_data_out : STD_LOGIC_VECTOR (2 downto 0);
    signal AXI_video_strm_V_keep_V_1_vld_in : STD_LOGIC;
    signal AXI_video_strm_V_keep_V_1_vld_out : STD_LOGIC;
    signal AXI_video_strm_V_keep_V_1_ack_in : STD_LOGIC;
    signal AXI_video_strm_V_keep_V_1_ack_out : STD_LOGIC;
    signal AXI_video_strm_V_keep_V_1_sel_rd : STD_LOGIC := '0';
    signal AXI_video_strm_V_keep_V_1_sel : STD_LOGIC;
    signal AXI_video_strm_V_keep_V_1_state : STD_LOGIC_VECTOR (1 downto 0) := "00";
    signal AXI_video_strm_V_strb_V_1_data_out : STD_LOGIC_VECTOR (2 downto 0);
    signal AXI_video_strm_V_strb_V_1_vld_in : STD_LOGIC;
    signal AXI_video_strm_V_strb_V_1_vld_out : STD_LOGIC;
    signal AXI_video_strm_V_strb_V_1_ack_in : STD_LOGIC;
    signal AXI_video_strm_V_strb_V_1_ack_out : STD_LOGIC;
    signal AXI_video_strm_V_strb_V_1_sel_rd : STD_LOGIC := '0';
    signal AXI_video_strm_V_strb_V_1_sel : STD_LOGIC;
    signal AXI_video_strm_V_strb_V_1_state : STD_LOGIC_VECTOR (1 downto 0) := "00";
    signal AXI_video_strm_V_user_V_1_data_out : STD_LOGIC_VECTOR (0 downto 0);
    signal AXI_video_strm_V_user_V_1_vld_in : STD_LOGIC;
    signal AXI_video_strm_V_user_V_1_vld_out : STD_LOGIC;
    signal AXI_video_strm_V_user_V_1_ack_in : STD_LOGIC;
    signal AXI_video_strm_V_user_V_1_ack_out : STD_LOGIC;
    signal AXI_video_strm_V_user_V_1_payload_A : STD_LOGIC_VECTOR (0 downto 0);
    signal AXI_video_strm_V_user_V_1_payload_B : STD_LOGIC_VECTOR (0 downto 0);
    signal AXI_video_strm_V_user_V_1_sel_rd : STD_LOGIC := '0';
    signal AXI_video_strm_V_user_V_1_sel_wr : STD_LOGIC := '0';
    signal AXI_video_strm_V_user_V_1_sel : STD_LOGIC;
    signal AXI_video_strm_V_user_V_1_load_A : STD_LOGIC;
    signal AXI_video_strm_V_user_V_1_load_B : STD_LOGIC;
    signal AXI_video_strm_V_user_V_1_state : STD_LOGIC_VECTOR (1 downto 0) := "00";
    signal AXI_video_strm_V_user_V_1_state_cmp_full : STD_LOGIC;
    signal AXI_video_strm_V_last_V_1_data_out : STD_LOGIC_VECTOR (0 downto 0);
    signal AXI_video_strm_V_last_V_1_vld_in : STD_LOGIC;
    signal AXI_video_strm_V_last_V_1_vld_out : STD_LOGIC;
    signal AXI_video_strm_V_last_V_1_ack_in : STD_LOGIC;
    signal AXI_video_strm_V_last_V_1_ack_out : STD_LOGIC;
    signal AXI_video_strm_V_last_V_1_payload_A : STD_LOGIC_VECTOR (0 downto 0);
    signal AXI_video_strm_V_last_V_1_payload_B : STD_LOGIC_VECTOR (0 downto 0);
    signal AXI_video_strm_V_last_V_1_sel_rd : STD_LOGIC := '0';
    signal AXI_video_strm_V_last_V_1_sel_wr : STD_LOGIC := '0';
    signal AXI_video_strm_V_last_V_1_sel : STD_LOGIC;
    signal AXI_video_strm_V_last_V_1_load_A : STD_LOGIC;
    signal AXI_video_strm_V_last_V_1_load_B : STD_LOGIC;
    signal AXI_video_strm_V_last_V_1_state : STD_LOGIC_VECTOR (1 downto 0) := "00";
    signal AXI_video_strm_V_last_V_1_state_cmp_full : STD_LOGIC;
    signal AXI_video_strm_V_id_V_1_data_out : STD_LOGIC_VECTOR (0 downto 0);
    signal AXI_video_strm_V_id_V_1_vld_in : STD_LOGIC;
    signal AXI_video_strm_V_id_V_1_vld_out : STD_LOGIC;
    signal AXI_video_strm_V_id_V_1_ack_in : STD_LOGIC;
    signal AXI_video_strm_V_id_V_1_ack_out : STD_LOGIC;
    signal AXI_video_strm_V_id_V_1_sel_rd : STD_LOGIC := '0';
    signal AXI_video_strm_V_id_V_1_sel : STD_LOGIC;
    signal AXI_video_strm_V_id_V_1_state : STD_LOGIC_VECTOR (1 downto 0) := "00";
    signal AXI_video_strm_V_dest_V_1_data_out : STD_LOGIC_VECTOR (0 downto 0);
    signal AXI_video_strm_V_dest_V_1_vld_in : STD_LOGIC;
    signal AXI_video_strm_V_dest_V_1_vld_out : STD_LOGIC;
    signal AXI_video_strm_V_dest_V_1_ack_in : STD_LOGIC;
    signal AXI_video_strm_V_dest_V_1_ack_out : STD_LOGIC;
    signal AXI_video_strm_V_dest_V_1_sel_rd : STD_LOGIC := '0';
    signal AXI_video_strm_V_dest_V_1_sel : STD_LOGIC;
    signal AXI_video_strm_V_dest_V_1_state : STD_LOGIC_VECTOR (1 downto 0) := "00";
    signal mapComp_address0 : STD_LOGIC_VECTOR (3 downto 0);
    signal mapComp_ce0 : STD_LOGIC;
    signal mapComp_q0 : STD_LOGIC_VECTOR (1 downto 0);
    signal StrmMPix_V_val_0_V_blk_n : STD_LOGIC;
    signal ap_CS_fsm_pp0_stage0 : STD_LOGIC;
    attribute fsm_encoding of ap_CS_fsm_pp0_stage0 : signal is "none";
    signal ap_enable_reg_pp0_iter1 : STD_LOGIC := '0';
    signal ap_block_pp0_stage0_flag00000000 : BOOLEAN;
    signal exitcond3_i_i_reg_603 : STD_LOGIC_VECTOR (0 downto 0);
    signal StrmMPix_V_val_1_V_blk_n : STD_LOGIC;
    signal StrmMPix_V_val_2_V_blk_n : STD_LOGIC;
    signal m_axis_video_TDATA_blk_n : STD_LOGIC;
    signal ap_enable_reg_pp0_iter2 : STD_LOGIC := '0';
    signal ap_reg_pp0_iter1_exitcond3_i_i_reg_603 : STD_LOGIC_VECTOR (0 downto 0);
    signal HwReg_height_cast9_loc_blk_n : STD_LOGIC;
    signal tmp_4_loc_blk_n : STD_LOGIC;
    signal j_i_i_reg_244 : STD_LOGIC_VECTOR (9 downto 0);
    signal ap_block_state1 : BOOLEAN;
    signal tmp_4_loc_read_reg_508 : STD_LOGIC_VECTOR (1 downto 0);
    signal Height_cast_i_i_fu_259_p1 : STD_LOGIC_VECTOR (9 downto 0);
    signal Height_cast_i_i_reg_514 : STD_LOGIC_VECTOR (9 downto 0);
    signal grp_reg_unsigned_short_s_fu_263_ap_return : STD_LOGIC_VECTOR (9 downto 0);
    signal tmp_i_i_reg_519 : STD_LOGIC_VECTOR (9 downto 0);
    signal ap_CS_fsm_state2 : STD_LOGIC;
    attribute fsm_encoding of ap_CS_fsm_state2 : signal is "none";
    signal grp_reg_unsigned_short_s_fu_263_ap_done : STD_LOGIC;
    signal grp_reg_unsigned_short_s_fu_269_ap_done : STD_LOGIC;
    signal ap_block_state2_on_subcall_done : BOOLEAN;
    signal grp_reg_unsigned_short_s_fu_269_ap_return : STD_LOGIC_VECTOR (9 downto 0);
    signal tmp_i_i_61_reg_524 : STD_LOGIC_VECTOR (9 downto 0);
    signal cols_cast_i_i_fu_275_p1 : STD_LOGIC_VECTOR (10 downto 0);
    signal cols_cast_i_i_reg_529 : STD_LOGIC_VECTOR (10 downto 0);
    signal tmp_4_fu_293_p2 : STD_LOGIC_VECTOR (4 downto 0);
    signal tmp_4_reg_534 : STD_LOGIC_VECTOR (4 downto 0);
    signal ap_CS_fsm_state3 : STD_LOGIC;
    attribute fsm_encoding of ap_CS_fsm_state3 : signal is "none";
    signal i_fu_319_p2 : STD_LOGIC_VECTOR (1 downto 0);
    signal i_reg_547 : STD_LOGIC_VECTOR (1 downto 0);
    signal tmp_7_i_i_fu_325_p2 : STD_LOGIC_VECTOR (10 downto 0);
    signal tmp_7_i_i_reg_559 : STD_LOGIC_VECTOR (10 downto 0);
    signal exitcond1_i_i_fu_313_p2 : STD_LOGIC_VECTOR (0 downto 0);
    signal tmp_7_fu_330_p1 : STD_LOGIC_VECTOR (1 downto 0);
    signal tmp_7_reg_564 : STD_LOGIC_VECTOR (1 downto 0);
    signal tmp_8_fu_334_p1 : STD_LOGIC_VECTOR (1 downto 0);
    signal tmp_8_reg_569 : STD_LOGIC_VECTOR (1 downto 0);
    signal tmp_9_fu_338_p1 : STD_LOGIC_VECTOR (1 downto 0);
    signal tmp_9_reg_574 : STD_LOGIC_VECTOR (1 downto 0);
    signal map_2_V_1_fu_371_p3 : STD_LOGIC_VECTOR (4 downto 0);
    signal ap_CS_fsm_state4 : STD_LOGIC;
    attribute fsm_encoding of ap_CS_fsm_state4 : signal is "none";
    signal map_2_V_3_fu_387_p3 : STD_LOGIC_VECTOR (4 downto 0);
    signal map_2_V_5_fu_395_p3 : STD_LOGIC_VECTOR (4 downto 0);
    signal exitcond2_i_i_fu_407_p2 : STD_LOGIC_VECTOR (0 downto 0);
    signal ap_CS_fsm_state5 : STD_LOGIC;
    attribute fsm_encoding of ap_CS_fsm_state5 : signal is "none";
    signal ap_block_state5 : BOOLEAN;
    signal i_1_fu_412_p2 : STD_LOGIC_VECTOR (8 downto 0);
    signal i_1_reg_598 : STD_LOGIC_VECTOR (8 downto 0);
    signal exitcond3_i_i_fu_422_p2 : STD_LOGIC_VECTOR (0 downto 0);
    signal ap_block_state6_pp0_stage0_iter0 : BOOLEAN;
    signal StrmMPix_V_val_0_V0_status : STD_LOGIC;
    signal ap_block_state7_pp0_stage0_iter1 : BOOLEAN;
    signal ap_block_state7_io : BOOLEAN;
    signal ap_block_state8_pp0_stage0_iter2 : BOOLEAN;
    signal ap_block_state8_io : BOOLEAN;
    signal ap_block_pp0_stage0_flag00011001 : BOOLEAN;
    signal j_fu_427_p2 : STD_LOGIC_VECTOR (9 downto 0);
    signal ap_enable_reg_pp0_iter0 : STD_LOGIC := '0';
    signal axi_last_V_fu_433_p2 : STD_LOGIC_VECTOR (0 downto 0);
    signal axi_last_V_reg_612 : STD_LOGIC_VECTOR (0 downto 0);
    signal tmp_data_V_fu_487_p4 : STD_LOGIC_VECTOR (23 downto 0);
    signal ap_block_pp0_stage0_flag00011011 : BOOLEAN;
    signal ap_condition_pp0_exit_iter0_state6 : STD_LOGIC;
    signal grp_reg_unsigned_short_s_fu_263_ap_start : STD_LOGIC;
    signal grp_reg_unsigned_short_s_fu_263_ap_idle : STD_LOGIC;
    signal grp_reg_unsigned_short_s_fu_263_ap_ready : STD_LOGIC;
    signal grp_reg_unsigned_short_s_fu_269_ap_start : STD_LOGIC;
    signal grp_reg_unsigned_short_s_fu_269_ap_idle : STD_LOGIC;
    signal grp_reg_unsigned_short_s_fu_269_ap_ready : STD_LOGIC;
    signal grp_reg_unsigned_short_s_fu_269_in_r : STD_LOGIC_VECTOR (9 downto 0);
    signal map_V_2_i_i_reg_185 : STD_LOGIC_VECTOR (4 downto 0);
    signal map_V_1_i_i_reg_197 : STD_LOGIC_VECTOR (4 downto 0);
    signal map_2_V_4_reg_209 : STD_LOGIC_VECTOR (4 downto 0);
    signal i_i_i_reg_221 : STD_LOGIC_VECTOR (1 downto 0);
    signal i1_i_i_reg_233 : STD_LOGIC_VECTOR (8 downto 0);
    signal ap_CS_fsm_state9 : STD_LOGIC;
    attribute fsm_encoding of ap_CS_fsm_state9 : signal is "none";
    signal ap_reg_grp_reg_unsigned_short_s_fu_263_ap_start : STD_LOGIC := '0';
    signal ap_block_state1_ignore_call18 : BOOLEAN;
    signal ap_reg_grp_reg_unsigned_short_s_fu_269_ap_start : STD_LOGIC := '0';
    signal ap_block_state1_ignore_call19 : BOOLEAN;
    signal tmp_5_cast_fu_308_p1 : STD_LOGIC_VECTOR (31 downto 0);
    signal StrmMPix_V_val_0_V0_update : STD_LOGIC;
    signal tmp_user_V_fu_112 : STD_LOGIC_VECTOR (0 downto 0);
    signal ap_block_pp0_stage0_flag00001001 : BOOLEAN;
    signal tmp_3_fu_282_p3 : STD_LOGIC_VECTOR (3 downto 0);
    signal p_shl_cast_fu_289_p1 : STD_LOGIC_VECTOR (4 downto 0);
    signal tmp_5_i_i_cast_fu_279_p1 : STD_LOGIC_VECTOR (4 downto 0);
    signal i_cast6_i_i_cast_fu_299_p1 : STD_LOGIC_VECTOR (4 downto 0);
    signal tmp_5_fu_303_p2 : STD_LOGIC_VECTOR (4 downto 0);
    signal sel_tmp_fu_351_p2 : STD_LOGIC_VECTOR (0 downto 0);
    signal map_0_V_cast_fu_347_p1 : STD_LOGIC_VECTOR (4 downto 0);
    signal sel_tmp2_fu_365_p2 : STD_LOGIC_VECTOR (0 downto 0);
    signal map_2_V_fu_357_p3 : STD_LOGIC_VECTOR (4 downto 0);
    signal map_2_V_2_fu_379_p3 : STD_LOGIC_VECTOR (4 downto 0);
    signal i1_cast_i_i_fu_403_p1 : STD_LOGIC_VECTOR (9 downto 0);
    signal j_cast_i_i_fu_418_p1 : STD_LOGIC_VECTOR (10 downto 0);
    signal tmp_2_fu_476_p5 : STD_LOGIC_VECTOR (7 downto 0);
    signal tmp_1_fu_465_p5 : STD_LOGIC_VECTOR (7 downto 0);
    signal tmp_fu_454_p5 : STD_LOGIC_VECTOR (7 downto 0);
    signal ap_NS_fsm : STD_LOGIC_VECTOR (6 downto 0);
    signal ap_idle_pp0 : STD_LOGIC;
    signal ap_enable_pp0 : STD_LOGIC;

    component design_1_v_frmbuf_rd_0_0_reg_unsigned_short_s IS
    port (
        ap_clk : IN STD_LOGIC;
        ap_rst : IN STD_LOGIC;
        ap_start : IN STD_LOGIC;
        ap_done : OUT STD_LOGIC;
        ap_idle : OUT STD_LOGIC;
        ap_ready : OUT STD_LOGIC;
        in_r : IN STD_LOGIC_VECTOR (9 downto 0);
        ap_return : OUT STD_LOGIC_VECTOR (9 downto 0) );
    end component;


    component design_1_v_frmbuf_rd_0_0_v_frmbuf_rd_mux_3g8j IS
    generic (
        ID : INTEGER;
        NUM_STAGE : INTEGER;
        din1_WIDTH : INTEGER;
        din2_WIDTH : INTEGER;
        din3_WIDTH : INTEGER;
        din4_WIDTH : INTEGER;
        dout_WIDTH : INTEGER );
    port (
        din1 : IN STD_LOGIC_VECTOR (7 downto 0);
        din2 : IN STD_LOGIC_VECTOR (7 downto 0);
        din3 : IN STD_LOGIC_VECTOR (7 downto 0);
        din4 : IN STD_LOGIC_VECTOR (1 downto 0);
        dout : OUT STD_LOGIC_VECTOR (7 downto 0) );
    end component;


    component design_1_v_frmbuf_rd_0_0_MultiPixStream2AXfYi IS
    generic (
        DataWidth : INTEGER;
        AddressRange : INTEGER;
        AddressWidth : INTEGER );
    port (
        clk : IN STD_LOGIC;
        reset : IN STD_LOGIC;
        address0 : IN STD_LOGIC_VECTOR (3 downto 0);
        ce0 : IN STD_LOGIC;
        q0 : OUT STD_LOGIC_VECTOR (1 downto 0) );
    end component;



begin
    mapComp_U : component design_1_v_frmbuf_rd_0_0_MultiPixStream2AXfYi
    generic map (
        DataWidth => 2,
        AddressRange => 12,
        AddressWidth => 4)
    port map (
        clk => ap_clk,
        reset => ap_rst,
        address0 => mapComp_address0,
        ce0 => mapComp_ce0,
        q0 => mapComp_q0);

    grp_reg_unsigned_short_s_fu_263 : component design_1_v_frmbuf_rd_0_0_reg_unsigned_short_s
    port map (
        ap_clk => ap_clk,
        ap_rst => ap_rst,
        ap_start => grp_reg_unsigned_short_s_fu_263_ap_start,
        ap_done => grp_reg_unsigned_short_s_fu_263_ap_done,
        ap_idle => grp_reg_unsigned_short_s_fu_263_ap_idle,
        ap_ready => grp_reg_unsigned_short_s_fu_263_ap_ready,
        in_r => Height_cast_i_i_reg_514,
        ap_return => grp_reg_unsigned_short_s_fu_263_ap_return);

    grp_reg_unsigned_short_s_fu_269 : component design_1_v_frmbuf_rd_0_0_reg_unsigned_short_s
    port map (
        ap_clk => ap_clk,
        ap_rst => ap_rst,
        ap_start => grp_reg_unsigned_short_s_fu_269_ap_start,
        ap_done => grp_reg_unsigned_short_s_fu_269_ap_done,
        ap_idle => grp_reg_unsigned_short_s_fu_269_ap_idle,
        ap_ready => grp_reg_unsigned_short_s_fu_269_ap_ready,
        in_r => grp_reg_unsigned_short_s_fu_269_in_r,
        ap_return => grp_reg_unsigned_short_s_fu_269_ap_return);

    v_frmbuf_rd_mux_3g8j_U31 : component design_1_v_frmbuf_rd_0_0_v_frmbuf_rd_mux_3g8j
    generic map (
        ID => 1,
        NUM_STAGE => 1,
        din1_WIDTH => 8,
        din2_WIDTH => 8,
        din3_WIDTH => 8,
        din4_WIDTH => 2,
        dout_WIDTH => 8)
    port map (
        din1 => StrmMPix_V_val_0_V_dout,
        din2 => StrmMPix_V_val_1_V_dout,
        din3 => StrmMPix_V_val_2_V_dout,
        din4 => tmp_7_reg_564,
        dout => tmp_fu_454_p5);

    v_frmbuf_rd_mux_3g8j_U32 : component design_1_v_frmbuf_rd_0_0_v_frmbuf_rd_mux_3g8j
    generic map (
        ID => 1,
        NUM_STAGE => 1,
        din1_WIDTH => 8,
        din2_WIDTH => 8,
        din3_WIDTH => 8,
        din4_WIDTH => 2,
        dout_WIDTH => 8)
    port map (
        din1 => StrmMPix_V_val_0_V_dout,
        din2 => StrmMPix_V_val_1_V_dout,
        din3 => StrmMPix_V_val_2_V_dout,
        din4 => tmp_8_reg_569,
        dout => tmp_1_fu_465_p5);

    v_frmbuf_rd_mux_3g8j_U33 : component design_1_v_frmbuf_rd_0_0_v_frmbuf_rd_mux_3g8j
    generic map (
        ID => 1,
        NUM_STAGE => 1,
        din1_WIDTH => 8,
        din2_WIDTH => 8,
        din3_WIDTH => 8,
        din4_WIDTH => 2,
        dout_WIDTH => 8)
    port map (
        din1 => StrmMPix_V_val_0_V_dout,
        din2 => StrmMPix_V_val_1_V_dout,
        din3 => StrmMPix_V_val_2_V_dout,
        din4 => tmp_9_reg_574,
        dout => tmp_2_fu_476_p5);





    AXI_video_strm_V_data_V_1_sel_rd_assign_proc : process(ap_clk)
    begin
        if (ap_clk'event and ap_clk =  '1') then
            if (ap_rst = '1') then
                AXI_video_strm_V_data_V_1_sel_rd <= ap_const_logic_0;
            else
                if (((ap_const_logic_1 = AXI_video_strm_V_data_V_1_ack_out) and (ap_const_logic_1 = AXI_video_strm_V_data_V_1_vld_out))) then 
                                        AXI_video_strm_V_data_V_1_sel_rd <= not(AXI_video_strm_V_data_V_1_sel_rd);
                end if; 
            end if;
        end if;
    end process;


    AXI_video_strm_V_data_V_1_sel_wr_assign_proc : process(ap_clk)
    begin
        if (ap_clk'event and ap_clk =  '1') then
            if (ap_rst = '1') then
                AXI_video_strm_V_data_V_1_sel_wr <= ap_const_logic_0;
            else
                if (((ap_const_logic_1 = AXI_video_strm_V_data_V_1_vld_in) and (ap_const_logic_1 = AXI_video_strm_V_data_V_1_ack_in))) then 
                                        AXI_video_strm_V_data_V_1_sel_wr <= not(AXI_video_strm_V_data_V_1_sel_wr);
                end if; 
            end if;
        end if;
    end process;


    AXI_video_strm_V_data_V_1_state_assign_proc : process(ap_clk)
    begin
        if (ap_clk'event and ap_clk =  '1') then
            if (ap_rst = '1') then
                AXI_video_strm_V_data_V_1_state <= ap_const_lv2_0;
            else
                if ((((ap_const_logic_0 = AXI_video_strm_V_data_V_1_vld_in) and (ap_const_logic_1 = AXI_video_strm_V_data_V_1_ack_out) and (AXI_video_strm_V_data_V_1_state = ap_const_lv2_3)) or ((ap_const_logic_0 = AXI_video_strm_V_data_V_1_vld_in) and (AXI_video_strm_V_data_V_1_state = ap_const_lv2_2)))) then 
                    AXI_video_strm_V_data_V_1_state <= ap_const_lv2_2;
                elsif ((((ap_const_logic_1 = AXI_video_strm_V_data_V_1_vld_in) and (ap_const_logic_0 = AXI_video_strm_V_data_V_1_ack_out) and (AXI_video_strm_V_data_V_1_state = ap_const_lv2_3)) or ((ap_const_logic_0 = AXI_video_strm_V_data_V_1_ack_out) and (AXI_video_strm_V_data_V_1_state = ap_const_lv2_1)))) then 
                    AXI_video_strm_V_data_V_1_state <= ap_const_lv2_1;
                elsif ((((ap_const_logic_1 = AXI_video_strm_V_data_V_1_vld_in) and (AXI_video_strm_V_data_V_1_state = ap_const_lv2_2)) or ((ap_const_logic_1 = AXI_video_strm_V_data_V_1_ack_out) and (AXI_video_strm_V_data_V_1_state = ap_const_lv2_1)) or ((AXI_video_strm_V_data_V_1_state = ap_const_lv2_3) and not(((ap_const_logic_1 = AXI_video_strm_V_data_V_1_vld_in) and (ap_const_logic_0 = AXI_video_strm_V_data_V_1_ack_out))) and not(((ap_const_logic_0 = AXI_video_strm_V_data_V_1_vld_in) and (ap_const_logic_1 = AXI_video_strm_V_data_V_1_ack_out)))))) then 
                    AXI_video_strm_V_data_V_1_state <= ap_const_lv2_3;
                else 
                    AXI_video_strm_V_data_V_1_state <= ap_const_lv2_2;
                end if; 
            end if;
        end if;
    end process;


    AXI_video_strm_V_dest_V_1_sel_rd_assign_proc : process(ap_clk)
    begin
        if (ap_clk'event and ap_clk =  '1') then
            if (ap_rst = '1') then
                AXI_video_strm_V_dest_V_1_sel_rd <= ap_const_logic_0;
            else
                if (((ap_const_logic_1 = AXI_video_strm_V_dest_V_1_ack_out) and (ap_const_logic_1 = AXI_video_strm_V_dest_V_1_vld_out))) then 
                                        AXI_video_strm_V_dest_V_1_sel_rd <= not(AXI_video_strm_V_dest_V_1_sel_rd);
                end if; 
            end if;
        end if;
    end process;


    AXI_video_strm_V_dest_V_1_state_assign_proc : process(ap_clk)
    begin
        if (ap_clk'event and ap_clk =  '1') then
            if (ap_rst = '1') then
                AXI_video_strm_V_dest_V_1_state <= ap_const_lv2_0;
            else
                if ((((ap_const_logic_0 = AXI_video_strm_V_dest_V_1_vld_in) and (ap_const_logic_1 = AXI_video_strm_V_dest_V_1_ack_out) and (ap_const_lv2_3 = AXI_video_strm_V_dest_V_1_state)) or ((ap_const_logic_0 = AXI_video_strm_V_dest_V_1_vld_in) and (ap_const_lv2_2 = AXI_video_strm_V_dest_V_1_state)))) then 
                    AXI_video_strm_V_dest_V_1_state <= ap_const_lv2_2;
                elsif ((((ap_const_logic_1 = AXI_video_strm_V_dest_V_1_vld_in) and (ap_const_logic_0 = AXI_video_strm_V_dest_V_1_ack_out) and (ap_const_lv2_3 = AXI_video_strm_V_dest_V_1_state)) or ((ap_const_logic_0 = AXI_video_strm_V_dest_V_1_ack_out) and (ap_const_lv2_1 = AXI_video_strm_V_dest_V_1_state)))) then 
                    AXI_video_strm_V_dest_V_1_state <= ap_const_lv2_1;
                elsif ((((ap_const_logic_1 = AXI_video_strm_V_dest_V_1_vld_in) and (ap_const_lv2_2 = AXI_video_strm_V_dest_V_1_state)) or ((ap_const_logic_1 = AXI_video_strm_V_dest_V_1_ack_out) and (ap_const_lv2_1 = AXI_video_strm_V_dest_V_1_state)) or ((ap_const_lv2_3 = AXI_video_strm_V_dest_V_1_state) and not(((ap_const_logic_1 = AXI_video_strm_V_dest_V_1_vld_in) and (ap_const_logic_0 = AXI_video_strm_V_dest_V_1_ack_out))) and not(((ap_const_logic_0 = AXI_video_strm_V_dest_V_1_vld_in) and (ap_const_logic_1 = AXI_video_strm_V_dest_V_1_ack_out)))))) then 
                    AXI_video_strm_V_dest_V_1_state <= ap_const_lv2_3;
                else 
                    AXI_video_strm_V_dest_V_1_state <= ap_const_lv2_2;
                end if; 
            end if;
        end if;
    end process;


    AXI_video_strm_V_id_V_1_sel_rd_assign_proc : process(ap_clk)
    begin
        if (ap_clk'event and ap_clk =  '1') then
            if (ap_rst = '1') then
                AXI_video_strm_V_id_V_1_sel_rd <= ap_const_logic_0;
            else
                if (((ap_const_logic_1 = AXI_video_strm_V_id_V_1_ack_out) and (ap_const_logic_1 = AXI_video_strm_V_id_V_1_vld_out))) then 
                                        AXI_video_strm_V_id_V_1_sel_rd <= not(AXI_video_strm_V_id_V_1_sel_rd);
                end if; 
            end if;
        end if;
    end process;


    AXI_video_strm_V_id_V_1_state_assign_proc : process(ap_clk)
    begin
        if (ap_clk'event and ap_clk =  '1') then
            if (ap_rst = '1') then
                AXI_video_strm_V_id_V_1_state <= ap_const_lv2_0;
            else
                if ((((ap_const_logic_0 = AXI_video_strm_V_id_V_1_vld_in) and (ap_const_logic_1 = AXI_video_strm_V_id_V_1_ack_out) and (ap_const_lv2_3 = AXI_video_strm_V_id_V_1_state)) or ((ap_const_logic_0 = AXI_video_strm_V_id_V_1_vld_in) and (ap_const_lv2_2 = AXI_video_strm_V_id_V_1_state)))) then 
                    AXI_video_strm_V_id_V_1_state <= ap_const_lv2_2;
                elsif ((((ap_const_logic_1 = AXI_video_strm_V_id_V_1_vld_in) and (ap_const_logic_0 = AXI_video_strm_V_id_V_1_ack_out) and (ap_const_lv2_3 = AXI_video_strm_V_id_V_1_state)) or ((ap_const_logic_0 = AXI_video_strm_V_id_V_1_ack_out) and (ap_const_lv2_1 = AXI_video_strm_V_id_V_1_state)))) then 
                    AXI_video_strm_V_id_V_1_state <= ap_const_lv2_1;
                elsif ((((ap_const_logic_1 = AXI_video_strm_V_id_V_1_vld_in) and (ap_const_lv2_2 = AXI_video_strm_V_id_V_1_state)) or ((ap_const_logic_1 = AXI_video_strm_V_id_V_1_ack_out) and (ap_const_lv2_1 = AXI_video_strm_V_id_V_1_state)) or ((ap_const_lv2_3 = AXI_video_strm_V_id_V_1_state) and not(((ap_const_logic_1 = AXI_video_strm_V_id_V_1_vld_in) and (ap_const_logic_0 = AXI_video_strm_V_id_V_1_ack_out))) and not(((ap_const_logic_0 = AXI_video_strm_V_id_V_1_vld_in) and (ap_const_logic_1 = AXI_video_strm_V_id_V_1_ack_out)))))) then 
                    AXI_video_strm_V_id_V_1_state <= ap_const_lv2_3;
                else 
                    AXI_video_strm_V_id_V_1_state <= ap_const_lv2_2;
                end if; 
            end if;
        end if;
    end process;


    AXI_video_strm_V_keep_V_1_sel_rd_assign_proc : process(ap_clk)
    begin
        if (ap_clk'event and ap_clk =  '1') then
            if (ap_rst = '1') then
                AXI_video_strm_V_keep_V_1_sel_rd <= ap_const_logic_0;
            else
                if (((ap_const_logic_1 = AXI_video_strm_V_keep_V_1_ack_out) and (ap_const_logic_1 = AXI_video_strm_V_keep_V_1_vld_out))) then 
                                        AXI_video_strm_V_keep_V_1_sel_rd <= not(AXI_video_strm_V_keep_V_1_sel_rd);
                end if; 
            end if;
        end if;
    end process;


    AXI_video_strm_V_keep_V_1_state_assign_proc : process(ap_clk)
    begin
        if (ap_clk'event and ap_clk =  '1') then
            if (ap_rst = '1') then
                AXI_video_strm_V_keep_V_1_state <= ap_const_lv2_0;
            else
                if ((((ap_const_logic_0 = AXI_video_strm_V_keep_V_1_vld_in) and (ap_const_logic_1 = AXI_video_strm_V_keep_V_1_ack_out) and (ap_const_lv2_3 = AXI_video_strm_V_keep_V_1_state)) or ((ap_const_logic_0 = AXI_video_strm_V_keep_V_1_vld_in) and (ap_const_lv2_2 = AXI_video_strm_V_keep_V_1_state)))) then 
                    AXI_video_strm_V_keep_V_1_state <= ap_const_lv2_2;
                elsif ((((ap_const_logic_1 = AXI_video_strm_V_keep_V_1_vld_in) and (ap_const_logic_0 = AXI_video_strm_V_keep_V_1_ack_out) and (ap_const_lv2_3 = AXI_video_strm_V_keep_V_1_state)) or ((ap_const_logic_0 = AXI_video_strm_V_keep_V_1_ack_out) and (ap_const_lv2_1 = AXI_video_strm_V_keep_V_1_state)))) then 
                    AXI_video_strm_V_keep_V_1_state <= ap_const_lv2_1;
                elsif ((((ap_const_logic_1 = AXI_video_strm_V_keep_V_1_vld_in) and (ap_const_lv2_2 = AXI_video_strm_V_keep_V_1_state)) or ((ap_const_logic_1 = AXI_video_strm_V_keep_V_1_ack_out) and (ap_const_lv2_1 = AXI_video_strm_V_keep_V_1_state)) or ((ap_const_lv2_3 = AXI_video_strm_V_keep_V_1_state) and not(((ap_const_logic_1 = AXI_video_strm_V_keep_V_1_vld_in) and (ap_const_logic_0 = AXI_video_strm_V_keep_V_1_ack_out))) and not(((ap_const_logic_0 = AXI_video_strm_V_keep_V_1_vld_in) and (ap_const_logic_1 = AXI_video_strm_V_keep_V_1_ack_out)))))) then 
                    AXI_video_strm_V_keep_V_1_state <= ap_const_lv2_3;
                else 
                    AXI_video_strm_V_keep_V_1_state <= ap_const_lv2_2;
                end if; 
            end if;
        end if;
    end process;


    AXI_video_strm_V_last_V_1_sel_rd_assign_proc : process(ap_clk)
    begin
        if (ap_clk'event and ap_clk =  '1') then
            if (ap_rst = '1') then
                AXI_video_strm_V_last_V_1_sel_rd <= ap_const_logic_0;
            else
                if (((ap_const_logic_1 = AXI_video_strm_V_last_V_1_ack_out) and (ap_const_logic_1 = AXI_video_strm_V_last_V_1_vld_out))) then 
                                        AXI_video_strm_V_last_V_1_sel_rd <= not(AXI_video_strm_V_last_V_1_sel_rd);
                end if; 
            end if;
        end if;
    end process;


    AXI_video_strm_V_last_V_1_sel_wr_assign_proc : process(ap_clk)
    begin
        if (ap_clk'event and ap_clk =  '1') then
            if (ap_rst = '1') then
                AXI_video_strm_V_last_V_1_sel_wr <= ap_const_logic_0;
            else
                if (((ap_const_logic_1 = AXI_video_strm_V_last_V_1_vld_in) and (ap_const_logic_1 = AXI_video_strm_V_last_V_1_ack_in))) then 
                                        AXI_video_strm_V_last_V_1_sel_wr <= not(AXI_video_strm_V_last_V_1_sel_wr);
                end if; 
            end if;
        end if;
    end process;


    AXI_video_strm_V_last_V_1_state_assign_proc : process(ap_clk)
    begin
        if (ap_clk'event and ap_clk =  '1') then
            if (ap_rst = '1') then
                AXI_video_strm_V_last_V_1_state <= ap_const_lv2_0;
            else
                if ((((ap_const_logic_0 = AXI_video_strm_V_last_V_1_vld_in) and (ap_const_logic_1 = AXI_video_strm_V_last_V_1_ack_out) and (ap_const_lv2_3 = AXI_video_strm_V_last_V_1_state)) or ((ap_const_logic_0 = AXI_video_strm_V_last_V_1_vld_in) and (ap_const_lv2_2 = AXI_video_strm_V_last_V_1_state)))) then 
                    AXI_video_strm_V_last_V_1_state <= ap_const_lv2_2;
                elsif ((((ap_const_logic_1 = AXI_video_strm_V_last_V_1_vld_in) and (ap_const_logic_0 = AXI_video_strm_V_last_V_1_ack_out) and (ap_const_lv2_3 = AXI_video_strm_V_last_V_1_state)) or ((ap_const_logic_0 = AXI_video_strm_V_last_V_1_ack_out) and (ap_const_lv2_1 = AXI_video_strm_V_last_V_1_state)))) then 
                    AXI_video_strm_V_last_V_1_state <= ap_const_lv2_1;
                elsif ((((ap_const_logic_1 = AXI_video_strm_V_last_V_1_vld_in) and (ap_const_lv2_2 = AXI_video_strm_V_last_V_1_state)) or ((ap_const_logic_1 = AXI_video_strm_V_last_V_1_ack_out) and (ap_const_lv2_1 = AXI_video_strm_V_last_V_1_state)) or ((ap_const_lv2_3 = AXI_video_strm_V_last_V_1_state) and not(((ap_const_logic_1 = AXI_video_strm_V_last_V_1_vld_in) and (ap_const_logic_0 = AXI_video_strm_V_last_V_1_ack_out))) and not(((ap_const_logic_0 = AXI_video_strm_V_last_V_1_vld_in) and (ap_const_logic_1 = AXI_video_strm_V_last_V_1_ack_out)))))) then 
                    AXI_video_strm_V_last_V_1_state <= ap_const_lv2_3;
                else 
                    AXI_video_strm_V_last_V_1_state <= ap_const_lv2_2;
                end if; 
            end if;
        end if;
    end process;


    AXI_video_strm_V_strb_V_1_sel_rd_assign_proc : process(ap_clk)
    begin
        if (ap_clk'event and ap_clk =  '1') then
            if (ap_rst = '1') then
                AXI_video_strm_V_strb_V_1_sel_rd <= ap_const_logic_0;
            else
                if (((ap_const_logic_1 = AXI_video_strm_V_strb_V_1_ack_out) and (ap_const_logic_1 = AXI_video_strm_V_strb_V_1_vld_out))) then 
                                        AXI_video_strm_V_strb_V_1_sel_rd <= not(AXI_video_strm_V_strb_V_1_sel_rd);
                end if; 
            end if;
        end if;
    end process;


    AXI_video_strm_V_strb_V_1_state_assign_proc : process(ap_clk)
    begin
        if (ap_clk'event and ap_clk =  '1') then
            if (ap_rst = '1') then
                AXI_video_strm_V_strb_V_1_state <= ap_const_lv2_0;
            else
                if ((((ap_const_logic_0 = AXI_video_strm_V_strb_V_1_vld_in) and (ap_const_logic_1 = AXI_video_strm_V_strb_V_1_ack_out) and (ap_const_lv2_3 = AXI_video_strm_V_strb_V_1_state)) or ((ap_const_logic_0 = AXI_video_strm_V_strb_V_1_vld_in) and (ap_const_lv2_2 = AXI_video_strm_V_strb_V_1_state)))) then 
                    AXI_video_strm_V_strb_V_1_state <= ap_const_lv2_2;
                elsif ((((ap_const_logic_1 = AXI_video_strm_V_strb_V_1_vld_in) and (ap_const_logic_0 = AXI_video_strm_V_strb_V_1_ack_out) and (ap_const_lv2_3 = AXI_video_strm_V_strb_V_1_state)) or ((ap_const_logic_0 = AXI_video_strm_V_strb_V_1_ack_out) and (ap_const_lv2_1 = AXI_video_strm_V_strb_V_1_state)))) then 
                    AXI_video_strm_V_strb_V_1_state <= ap_const_lv2_1;
                elsif ((((ap_const_logic_1 = AXI_video_strm_V_strb_V_1_vld_in) and (ap_const_lv2_2 = AXI_video_strm_V_strb_V_1_state)) or ((ap_const_logic_1 = AXI_video_strm_V_strb_V_1_ack_out) and (ap_const_lv2_1 = AXI_video_strm_V_strb_V_1_state)) or ((ap_const_lv2_3 = AXI_video_strm_V_strb_V_1_state) and not(((ap_const_logic_1 = AXI_video_strm_V_strb_V_1_vld_in) and (ap_const_logic_0 = AXI_video_strm_V_strb_V_1_ack_out))) and not(((ap_const_logic_0 = AXI_video_strm_V_strb_V_1_vld_in) and (ap_const_logic_1 = AXI_video_strm_V_strb_V_1_ack_out)))))) then 
                    AXI_video_strm_V_strb_V_1_state <= ap_const_lv2_3;
                else 
                    AXI_video_strm_V_strb_V_1_state <= ap_const_lv2_2;
                end if; 
            end if;
        end if;
    end process;


    AXI_video_strm_V_user_V_1_sel_rd_assign_proc : process(ap_clk)
    begin
        if (ap_clk'event and ap_clk =  '1') then
            if (ap_rst = '1') then
                AXI_video_strm_V_user_V_1_sel_rd <= ap_const_logic_0;
            else
                if (((ap_const_logic_1 = AXI_video_strm_V_user_V_1_ack_out) and (ap_const_logic_1 = AXI_video_strm_V_user_V_1_vld_out))) then 
                                        AXI_video_strm_V_user_V_1_sel_rd <= not(AXI_video_strm_V_user_V_1_sel_rd);
                end if; 
            end if;
        end if;
    end process;


    AXI_video_strm_V_user_V_1_sel_wr_assign_proc : process(ap_clk)
    begin
        if (ap_clk'event and ap_clk =  '1') then
            if (ap_rst = '1') then
                AXI_video_strm_V_user_V_1_sel_wr <= ap_const_logic_0;
            else
                if (((ap_const_logic_1 = AXI_video_strm_V_user_V_1_vld_in) and (ap_const_logic_1 = AXI_video_strm_V_user_V_1_ack_in))) then 
                                        AXI_video_strm_V_user_V_1_sel_wr <= not(AXI_video_strm_V_user_V_1_sel_wr);
                end if; 
            end if;
        end if;
    end process;


    AXI_video_strm_V_user_V_1_state_assign_proc : process(ap_clk)
    begin
        if (ap_clk'event and ap_clk =  '1') then
            if (ap_rst = '1') then
                AXI_video_strm_V_user_V_1_state <= ap_const_lv2_0;
            else
                if ((((ap_const_logic_0 = AXI_video_strm_V_user_V_1_vld_in) and (ap_const_logic_1 = AXI_video_strm_V_user_V_1_ack_out) and (ap_const_lv2_3 = AXI_video_strm_V_user_V_1_state)) or ((ap_const_logic_0 = AXI_video_strm_V_user_V_1_vld_in) and (ap_const_lv2_2 = AXI_video_strm_V_user_V_1_state)))) then 
                    AXI_video_strm_V_user_V_1_state <= ap_const_lv2_2;
                elsif ((((ap_const_logic_1 = AXI_video_strm_V_user_V_1_vld_in) and (ap_const_logic_0 = AXI_video_strm_V_user_V_1_ack_out) and (ap_const_lv2_3 = AXI_video_strm_V_user_V_1_state)) or ((ap_const_logic_0 = AXI_video_strm_V_user_V_1_ack_out) and (ap_const_lv2_1 = AXI_video_strm_V_user_V_1_state)))) then 
                    AXI_video_strm_V_user_V_1_state <= ap_const_lv2_1;
                elsif ((((ap_const_logic_1 = AXI_video_strm_V_user_V_1_vld_in) and (ap_const_lv2_2 = AXI_video_strm_V_user_V_1_state)) or ((ap_const_logic_1 = AXI_video_strm_V_user_V_1_ack_out) and (ap_const_lv2_1 = AXI_video_strm_V_user_V_1_state)) or ((ap_const_lv2_3 = AXI_video_strm_V_user_V_1_state) and not(((ap_const_logic_1 = AXI_video_strm_V_user_V_1_vld_in) and (ap_const_logic_0 = AXI_video_strm_V_user_V_1_ack_out))) and not(((ap_const_logic_0 = AXI_video_strm_V_user_V_1_vld_in) and (ap_const_logic_1 = AXI_video_strm_V_user_V_1_ack_out)))))) then 
                    AXI_video_strm_V_user_V_1_state <= ap_const_lv2_3;
                else 
                    AXI_video_strm_V_user_V_1_state <= ap_const_lv2_2;
                end if; 
            end if;
        end if;
    end process;


    ap_CS_fsm_assign_proc : process(ap_clk)
    begin
        if (ap_clk'event and ap_clk =  '1') then
            if (ap_rst = '1') then
                ap_CS_fsm <= ap_ST_fsm_state1;
            else
                ap_CS_fsm <= ap_NS_fsm;
            end if;
        end if;
    end process;


    ap_done_reg_assign_proc : process(ap_clk)
    begin
        if (ap_clk'event and ap_clk =  '1') then
            if (ap_rst = '1') then
                ap_done_reg <= ap_const_logic_0;
            else
                if ((ap_const_logic_1 = ap_continue)) then 
                    ap_done_reg <= ap_const_logic_0;
                elsif (((ap_const_logic_1 = ap_CS_fsm_state5) and not(((ap_const_logic_0 = AXI_video_strm_V_data_V_1_ack_in) or (ap_const_logic_0 = AXI_video_strm_V_keep_V_1_ack_in) or (ap_const_logic_0 = AXI_video_strm_V_strb_V_1_ack_in) or (ap_const_logic_0 = AXI_video_strm_V_user_V_1_ack_in) or (ap_const_logic_0 = AXI_video_strm_V_last_V_1_ack_in) or (ap_const_logic_0 = AXI_video_strm_V_id_V_1_ack_in) or (ap_const_logic_0 = AXI_video_strm_V_dest_V_1_ack_in))) and (ap_const_lv1_1 = exitcond2_i_i_fu_407_p2))) then 
                    ap_done_reg <= ap_const_logic_1;
                end if; 
            end if;
        end if;
    end process;


    ap_enable_reg_pp0_iter0_assign_proc : process(ap_clk)
    begin
        if (ap_clk'event and ap_clk =  '1') then
            if (ap_rst = '1') then
                ap_enable_reg_pp0_iter0 <= ap_const_logic_0;
            else
                if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_block_pp0_stage0_flag00011011 = ap_const_boolean_0) and (ap_const_logic_1 = ap_condition_pp0_exit_iter0_state6))) then 
                    ap_enable_reg_pp0_iter0 <= ap_const_logic_0;
                elsif (((ap_const_logic_1 = ap_CS_fsm_state5) and not(((ap_const_logic_0 = AXI_video_strm_V_data_V_1_ack_in) or (ap_const_logic_0 = AXI_video_strm_V_keep_V_1_ack_in) or (ap_const_logic_0 = AXI_video_strm_V_strb_V_1_ack_in) or (ap_const_logic_0 = AXI_video_strm_V_user_V_1_ack_in) or (ap_const_logic_0 = AXI_video_strm_V_last_V_1_ack_in) or (ap_const_logic_0 = AXI_video_strm_V_id_V_1_ack_in) or (ap_const_logic_0 = AXI_video_strm_V_dest_V_1_ack_in))) and (ap_const_lv1_0 = exitcond2_i_i_fu_407_p2))) then 
                    ap_enable_reg_pp0_iter0 <= ap_const_logic_1;
                end if; 
            end if;
        end if;
    end process;


    ap_enable_reg_pp0_iter1_assign_proc : process(ap_clk)
    begin
        if (ap_clk'event and ap_clk =  '1') then
            if (ap_rst = '1') then
                ap_enable_reg_pp0_iter1 <= ap_const_logic_0;
            else
                if ((ap_block_pp0_stage0_flag00011011 = ap_const_boolean_0)) then
                    if ((ap_const_logic_1 = ap_condition_pp0_exit_iter0_state6)) then 
                        ap_enable_reg_pp0_iter1 <= (ap_condition_pp0_exit_iter0_state6 xor ap_const_logic_1);
                    elsif ((ap_const_boolean_1 = ap_const_boolean_1)) then 
                        ap_enable_reg_pp0_iter1 <= ap_enable_reg_pp0_iter0;
                    end if;
                end if; 
            end if;
        end if;
    end process;


    ap_enable_reg_pp0_iter2_assign_proc : process(ap_clk)
    begin
        if (ap_clk'event and ap_clk =  '1') then
            if (ap_rst = '1') then
                ap_enable_reg_pp0_iter2 <= ap_const_logic_0;
            else
                if ((ap_block_pp0_stage0_flag00011011 = ap_const_boolean_0)) then 
                    ap_enable_reg_pp0_iter2 <= ap_enable_reg_pp0_iter1;
                elsif (((ap_const_logic_1 = ap_CS_fsm_state5) and not(((ap_const_logic_0 = AXI_video_strm_V_data_V_1_ack_in) or (ap_const_logic_0 = AXI_video_strm_V_keep_V_1_ack_in) or (ap_const_logic_0 = AXI_video_strm_V_strb_V_1_ack_in) or (ap_const_logic_0 = AXI_video_strm_V_user_V_1_ack_in) or (ap_const_logic_0 = AXI_video_strm_V_last_V_1_ack_in) or (ap_const_logic_0 = AXI_video_strm_V_id_V_1_ack_in) or (ap_const_logic_0 = AXI_video_strm_V_dest_V_1_ack_in))) and (ap_const_lv1_0 = exitcond2_i_i_fu_407_p2))) then 
                    ap_enable_reg_pp0_iter2 <= ap_const_logic_0;
                end if; 
            end if;
        end if;
    end process;


    ap_reg_grp_reg_unsigned_short_s_fu_263_ap_start_assign_proc : process(ap_clk)
    begin
        if (ap_clk'event and ap_clk =  '1') then
            if (ap_rst = '1') then
                ap_reg_grp_reg_unsigned_short_s_fu_263_ap_start <= ap_const_logic_0;
            else
                if (((ap_const_logic_1 = ap_CS_fsm_state1) and not(((ap_const_logic_0 = ap_start) or (ap_done_reg = ap_const_logic_1) or (ap_const_logic_0 = HwReg_height_cast9_loc_empty_n) or (ap_const_logic_0 = tmp_4_loc_empty_n))))) then 
                    ap_reg_grp_reg_unsigned_short_s_fu_263_ap_start <= ap_const_logic_1;
                elsif ((ap_const_logic_1 = grp_reg_unsigned_short_s_fu_263_ap_ready)) then 
                    ap_reg_grp_reg_unsigned_short_s_fu_263_ap_start <= ap_const_logic_0;
                end if; 
            end if;
        end if;
    end process;


    ap_reg_grp_reg_unsigned_short_s_fu_269_ap_start_assign_proc : process(ap_clk)
    begin
        if (ap_clk'event and ap_clk =  '1') then
            if (ap_rst = '1') then
                ap_reg_grp_reg_unsigned_short_s_fu_269_ap_start <= ap_const_logic_0;
            else
                if (((ap_const_logic_1 = ap_CS_fsm_state1) and not(((ap_const_logic_0 = ap_start) or (ap_done_reg = ap_const_logic_1) or (ap_const_logic_0 = HwReg_height_cast9_loc_empty_n) or (ap_const_logic_0 = tmp_4_loc_empty_n))))) then 
                    ap_reg_grp_reg_unsigned_short_s_fu_269_ap_start <= ap_const_logic_1;
                elsif ((ap_const_logic_1 = grp_reg_unsigned_short_s_fu_269_ap_ready)) then 
                    ap_reg_grp_reg_unsigned_short_s_fu_269_ap_start <= ap_const_logic_0;
                end if; 
            end if;
        end if;
    end process;


    i1_i_i_reg_233_assign_proc : process (ap_clk)
    begin
        if (ap_clk'event and ap_clk = '1') then
            if ((ap_const_logic_1 = ap_CS_fsm_state9)) then 
                i1_i_i_reg_233 <= i_1_reg_598;
            elsif (((ap_const_logic_1 = ap_CS_fsm_state3) and (ap_const_lv1_1 = exitcond1_i_i_fu_313_p2))) then 
                i1_i_i_reg_233 <= ap_const_lv9_0;
            end if; 
        end if;
    end process;

    i_i_i_reg_221_assign_proc : process (ap_clk)
    begin
        if (ap_clk'event and ap_clk = '1') then
            if ((ap_const_logic_1 = ap_CS_fsm_state4)) then 
                i_i_i_reg_221 <= i_reg_547;
            elsif (((ap_const_logic_1 = ap_CS_fsm_state2) and (ap_block_state2_on_subcall_done = ap_const_boolean_0))) then 
                i_i_i_reg_221 <= ap_const_lv2_0;
            end if; 
        end if;
    end process;

    j_i_i_reg_244_assign_proc : process (ap_clk)
    begin
        if (ap_clk'event and ap_clk = '1') then
            if (((ap_const_logic_1 = ap_CS_fsm_state5) and not(((ap_const_logic_0 = AXI_video_strm_V_data_V_1_ack_in) or (ap_const_logic_0 = AXI_video_strm_V_keep_V_1_ack_in) or (ap_const_logic_0 = AXI_video_strm_V_strb_V_1_ack_in) or (ap_const_logic_0 = AXI_video_strm_V_user_V_1_ack_in) or (ap_const_logic_0 = AXI_video_strm_V_last_V_1_ack_in) or (ap_const_logic_0 = AXI_video_strm_V_id_V_1_ack_in) or (ap_const_logic_0 = AXI_video_strm_V_dest_V_1_ack_in))) and (ap_const_lv1_0 = exitcond2_i_i_fu_407_p2))) then 
                j_i_i_reg_244 <= ap_const_lv10_0;
            elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_block_pp0_stage0_flag00011001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_lv1_0 = exitcond3_i_i_fu_422_p2))) then 
                j_i_i_reg_244 <= j_fu_427_p2;
            end if; 
        end if;
    end process;

    tmp_user_V_fu_112_assign_proc : process (ap_clk)
    begin
        if (ap_clk'event and ap_clk = '1') then
            if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_lv1_0 = exitcond3_i_i_reg_603) and (ap_block_pp0_stage0_flag00011001 = ap_const_boolean_0))) then 
                tmp_user_V_fu_112 <= ap_const_lv1_0;
            elsif (((ap_const_logic_1 = ap_CS_fsm_state3) and (ap_const_lv1_1 = exitcond1_i_i_fu_313_p2))) then 
                tmp_user_V_fu_112 <= ap_const_lv1_1;
            end if; 
        end if;
    end process;
    process (ap_clk)
    begin
        if (ap_clk'event and ap_clk = '1') then
            if ((ap_const_logic_1 = AXI_video_strm_V_data_V_1_load_A)) then
                AXI_video_strm_V_data_V_1_payload_A <= tmp_data_V_fu_487_p4;
            end if;
        end if;
    end process;
    process (ap_clk)
    begin
        if (ap_clk'event and ap_clk = '1') then
            if ((ap_const_logic_1 = AXI_video_strm_V_data_V_1_load_B)) then
                AXI_video_strm_V_data_V_1_payload_B <= tmp_data_V_fu_487_p4;
            end if;
        end if;
    end process;
    process (ap_clk)
    begin
        if (ap_clk'event and ap_clk = '1') then
            if ((ap_const_logic_1 = AXI_video_strm_V_last_V_1_load_A)) then
                AXI_video_strm_V_last_V_1_payload_A <= axi_last_V_reg_612;
            end if;
        end if;
    end process;
    process (ap_clk)
    begin
        if (ap_clk'event and ap_clk = '1') then
            if ((ap_const_logic_1 = AXI_video_strm_V_last_V_1_load_B)) then
                AXI_video_strm_V_last_V_1_payload_B <= axi_last_V_reg_612;
            end if;
        end if;
    end process;
    process (ap_clk)
    begin
        if (ap_clk'event and ap_clk = '1') then
            if ((ap_const_logic_1 = AXI_video_strm_V_user_V_1_load_A)) then
                AXI_video_strm_V_user_V_1_payload_A <= tmp_user_V_fu_112;
            end if;
        end if;
    end process;
    process (ap_clk)
    begin
        if (ap_clk'event and ap_clk = '1') then
            if ((ap_const_logic_1 = AXI_video_strm_V_user_V_1_load_B)) then
                AXI_video_strm_V_user_V_1_payload_B <= tmp_user_V_fu_112;
            end if;
        end if;
    end process;
    process (ap_clk)
    begin
        if (ap_clk'event and ap_clk = '1') then
            if (((ap_const_logic_1 = ap_CS_fsm_state1) and not(((ap_const_logic_0 = ap_start) or (ap_done_reg = ap_const_logic_1) or (ap_const_logic_0 = HwReg_height_cast9_loc_empty_n) or (ap_const_logic_0 = tmp_4_loc_empty_n))))) then
                    Height_cast_i_i_reg_514(8 downto 0) <= Height_cast_i_i_fu_259_p1(8 downto 0);
                tmp_4_loc_read_reg_508 <= tmp_4_loc_dout;
            end if;
        end if;
    end process;
    process (ap_clk)
    begin
        if (ap_clk'event and ap_clk = '1') then
            if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_block_pp0_stage0_flag00011001 = ap_const_boolean_0))) then
                ap_reg_pp0_iter1_exitcond3_i_i_reg_603 <= exitcond3_i_i_reg_603;
                exitcond3_i_i_reg_603 <= exitcond3_i_i_fu_422_p2;
            end if;
        end if;
    end process;
    process (ap_clk)
    begin
        if (ap_clk'event and ap_clk = '1') then
            if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_block_pp0_stage0_flag00011001 = ap_const_boolean_0) and (ap_const_lv1_0 = exitcond3_i_i_fu_422_p2))) then
                axi_last_V_reg_612 <= axi_last_V_fu_433_p2;
            end if;
        end if;
    end process;
    process (ap_clk)
    begin
        if (ap_clk'event and ap_clk = '1') then
            if (((ap_const_logic_1 = ap_CS_fsm_state2) and (ap_block_state2_on_subcall_done = ap_const_boolean_0))) then
                    cols_cast_i_i_reg_529(9 downto 0) <= cols_cast_i_i_fu_275_p1(9 downto 0);
                tmp_4_reg_534 <= tmp_4_fu_293_p2;
                tmp_i_i_61_reg_524 <= grp_reg_unsigned_short_s_fu_269_ap_return;
                tmp_i_i_reg_519 <= grp_reg_unsigned_short_s_fu_263_ap_return;
            end if;
        end if;
    end process;
    process (ap_clk)
    begin
        if (ap_clk'event and ap_clk = '1') then
            if (((ap_const_logic_1 = ap_CS_fsm_state5) and not(((ap_const_logic_0 = AXI_video_strm_V_data_V_1_ack_in) or (ap_const_logic_0 = AXI_video_strm_V_keep_V_1_ack_in) or (ap_const_logic_0 = AXI_video_strm_V_strb_V_1_ack_in) or (ap_const_logic_0 = AXI_video_strm_V_user_V_1_ack_in) or (ap_const_logic_0 = AXI_video_strm_V_last_V_1_ack_in) or (ap_const_logic_0 = AXI_video_strm_V_id_V_1_ack_in) or (ap_const_logic_0 = AXI_video_strm_V_dest_V_1_ack_in))))) then
                i_1_reg_598 <= i_1_fu_412_p2;
            end if;
        end if;
    end process;
    process (ap_clk)
    begin
        if (ap_clk'event and ap_clk = '1') then
            if ((ap_const_logic_1 = ap_CS_fsm_state3)) then
                i_reg_547 <= i_fu_319_p2;
            end if;
        end if;
    end process;
    process (ap_clk)
    begin
        if (ap_clk'event and ap_clk = '1') then
            if ((ap_const_logic_1 = ap_CS_fsm_state4)) then
                map_2_V_4_reg_209 <= map_2_V_5_fu_395_p3;
                map_V_1_i_i_reg_197 <= map_2_V_3_fu_387_p3;
                map_V_2_i_i_reg_185 <= map_2_V_1_fu_371_p3;
            end if;
        end if;
    end process;
    process (ap_clk)
    begin
        if (ap_clk'event and ap_clk = '1') then
            if (((ap_const_logic_1 = ap_CS_fsm_state3) and (ap_const_lv1_1 = exitcond1_i_i_fu_313_p2))) then
                tmp_7_i_i_reg_559 <= tmp_7_i_i_fu_325_p2;
                tmp_7_reg_564 <= tmp_7_fu_330_p1;
                tmp_8_reg_569 <= tmp_8_fu_334_p1;
                tmp_9_reg_574 <= tmp_9_fu_338_p1;
            end if;
        end if;
    end process;
    Height_cast_i_i_reg_514(9) <= '0';
    cols_cast_i_i_reg_529(10) <= '0';

    ap_NS_fsm_assign_proc : process (ap_start, ap_done_reg, ap_CS_fsm, ap_CS_fsm_state1, AXI_video_strm_V_data_V_1_ack_in, AXI_video_strm_V_keep_V_1_ack_in, AXI_video_strm_V_strb_V_1_ack_in, AXI_video_strm_V_user_V_1_ack_in, AXI_video_strm_V_last_V_1_ack_in, AXI_video_strm_V_id_V_1_ack_in, AXI_video_strm_V_dest_V_1_ack_in, HwReg_height_cast9_loc_empty_n, tmp_4_loc_empty_n, ap_enable_reg_pp0_iter1, ap_enable_reg_pp0_iter2, ap_CS_fsm_state2, ap_block_state2_on_subcall_done, ap_CS_fsm_state3, exitcond1_i_i_fu_313_p2, exitcond2_i_i_fu_407_p2, ap_CS_fsm_state5, exitcond3_i_i_fu_422_p2, ap_enable_reg_pp0_iter0, ap_block_pp0_stage0_flag00011011)
    begin
        case ap_CS_fsm is
            when ap_ST_fsm_state1 => 
                if (((ap_const_logic_1 = ap_CS_fsm_state1) and not(((ap_const_logic_0 = ap_start) or (ap_done_reg = ap_const_logic_1) or (ap_const_logic_0 = HwReg_height_cast9_loc_empty_n) or (ap_const_logic_0 = tmp_4_loc_empty_n))))) then
                    ap_NS_fsm <= ap_ST_fsm_state2;
                else
                    ap_NS_fsm <= ap_ST_fsm_state1;
                end if;
            when ap_ST_fsm_state2 => 
                if (((ap_const_logic_1 = ap_CS_fsm_state2) and (ap_block_state2_on_subcall_done = ap_const_boolean_0))) then
                    ap_NS_fsm <= ap_ST_fsm_state3;
                else
                    ap_NS_fsm <= ap_ST_fsm_state2;
                end if;
            when ap_ST_fsm_state3 => 
                if (((ap_const_logic_1 = ap_CS_fsm_state3) and (ap_const_lv1_1 = exitcond1_i_i_fu_313_p2))) then
                    ap_NS_fsm <= ap_ST_fsm_state5;
                else
                    ap_NS_fsm <= ap_ST_fsm_state4;
                end if;
            when ap_ST_fsm_state4 => 
                ap_NS_fsm <= ap_ST_fsm_state3;
            when ap_ST_fsm_state5 => 
                if (((ap_const_logic_1 = ap_CS_fsm_state5) and not(((ap_const_logic_0 = AXI_video_strm_V_data_V_1_ack_in) or (ap_const_logic_0 = AXI_video_strm_V_keep_V_1_ack_in) or (ap_const_logic_0 = AXI_video_strm_V_strb_V_1_ack_in) or (ap_const_logic_0 = AXI_video_strm_V_user_V_1_ack_in) or (ap_const_logic_0 = AXI_video_strm_V_last_V_1_ack_in) or (ap_const_logic_0 = AXI_video_strm_V_id_V_1_ack_in) or (ap_const_logic_0 = AXI_video_strm_V_dest_V_1_ack_in))) and (ap_const_lv1_1 = exitcond2_i_i_fu_407_p2))) then
                    ap_NS_fsm <= ap_ST_fsm_state1;
                elsif (((ap_const_logic_1 = ap_CS_fsm_state5) and not(((ap_const_logic_0 = AXI_video_strm_V_data_V_1_ack_in) or (ap_const_logic_0 = AXI_video_strm_V_keep_V_1_ack_in) or (ap_const_logic_0 = AXI_video_strm_V_strb_V_1_ack_in) or (ap_const_logic_0 = AXI_video_strm_V_user_V_1_ack_in) or (ap_const_logic_0 = AXI_video_strm_V_last_V_1_ack_in) or (ap_const_logic_0 = AXI_video_strm_V_id_V_1_ack_in) or (ap_const_logic_0 = AXI_video_strm_V_dest_V_1_ack_in))) and (ap_const_lv1_0 = exitcond2_i_i_fu_407_p2))) then
                    ap_NS_fsm <= ap_ST_fsm_pp0_stage0;
                else
                    ap_NS_fsm <= ap_ST_fsm_state5;
                end if;
            when ap_ST_fsm_pp0_stage0 => 
                if ((not(((ap_const_logic_1 = ap_enable_reg_pp0_iter2) and (ap_block_pp0_stage0_flag00011011 = ap_const_boolean_0) and (ap_enable_reg_pp0_iter1 = ap_const_logic_0))) and not(((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_block_pp0_stage0_flag00011011 = ap_const_boolean_0) and (ap_const_lv1_1 = exitcond3_i_i_fu_422_p2) and (ap_enable_reg_pp0_iter1 = ap_const_logic_0))))) then
                    ap_NS_fsm <= ap_ST_fsm_pp0_stage0;
                elsif ((((ap_const_logic_1 = ap_enable_reg_pp0_iter2) and (ap_block_pp0_stage0_flag00011011 = ap_const_boolean_0) and (ap_enable_reg_pp0_iter1 = ap_const_logic_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_block_pp0_stage0_flag00011011 = ap_const_boolean_0) and (ap_const_lv1_1 = exitcond3_i_i_fu_422_p2) and (ap_enable_reg_pp0_iter1 = ap_const_logic_0)))) then
                    ap_NS_fsm <= ap_ST_fsm_state9;
                else
                    ap_NS_fsm <= ap_ST_fsm_pp0_stage0;
                end if;
            when ap_ST_fsm_state9 => 
                ap_NS_fsm <= ap_ST_fsm_state5;
            when others =>  
                ap_NS_fsm <= "XXXXXXX";
        end case;
    end process;
    AXI_video_strm_V_data_V_1_ack_in <= AXI_video_strm_V_data_V_1_state(1);
    AXI_video_strm_V_data_V_1_ack_out <= m_axis_video_TREADY;

    AXI_video_strm_V_data_V_1_data_out_assign_proc : process(AXI_video_strm_V_data_V_1_payload_A, AXI_video_strm_V_data_V_1_payload_B, AXI_video_strm_V_data_V_1_sel)
    begin
        if ((ap_const_logic_1 = AXI_video_strm_V_data_V_1_sel)) then 
            AXI_video_strm_V_data_V_1_data_out <= AXI_video_strm_V_data_V_1_payload_B;
        else 
            AXI_video_strm_V_data_V_1_data_out <= AXI_video_strm_V_data_V_1_payload_A;
        end if; 
    end process;

    AXI_video_strm_V_data_V_1_load_A <= (AXI_video_strm_V_data_V_1_state_cmp_full and not(AXI_video_strm_V_data_V_1_sel_wr));
    AXI_video_strm_V_data_V_1_load_B <= (AXI_video_strm_V_data_V_1_sel_wr and AXI_video_strm_V_data_V_1_state_cmp_full);
    AXI_video_strm_V_data_V_1_sel <= AXI_video_strm_V_data_V_1_sel_rd;
    AXI_video_strm_V_data_V_1_state_cmp_full <= '0' when (AXI_video_strm_V_data_V_1_state = ap_const_lv2_1) else '1';

    AXI_video_strm_V_data_V_1_vld_in_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter1, exitcond3_i_i_reg_603, ap_block_pp0_stage0_flag00011001)
    begin
        if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_lv1_0 = exitcond3_i_i_reg_603) and (ap_block_pp0_stage0_flag00011001 = ap_const_boolean_0))) then 
            AXI_video_strm_V_data_V_1_vld_in <= ap_const_logic_1;
        else 
            AXI_video_strm_V_data_V_1_vld_in <= ap_const_logic_0;
        end if; 
    end process;

    AXI_video_strm_V_data_V_1_vld_out <= AXI_video_strm_V_data_V_1_state(0);
    AXI_video_strm_V_dest_V_1_ack_in <= AXI_video_strm_V_dest_V_1_state(1);
    AXI_video_strm_V_dest_V_1_ack_out <= m_axis_video_TREADY;
    AXI_video_strm_V_dest_V_1_data_out <= ap_const_lv1_0;
    AXI_video_strm_V_dest_V_1_sel <= AXI_video_strm_V_dest_V_1_sel_rd;

    AXI_video_strm_V_dest_V_1_vld_in_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter1, exitcond3_i_i_reg_603, ap_block_pp0_stage0_flag00011001)
    begin
        if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_lv1_0 = exitcond3_i_i_reg_603) and (ap_block_pp0_stage0_flag00011001 = ap_const_boolean_0))) then 
            AXI_video_strm_V_dest_V_1_vld_in <= ap_const_logic_1;
        else 
            AXI_video_strm_V_dest_V_1_vld_in <= ap_const_logic_0;
        end if; 
    end process;

    AXI_video_strm_V_dest_V_1_vld_out <= AXI_video_strm_V_dest_V_1_state(0);
    AXI_video_strm_V_id_V_1_ack_in <= AXI_video_strm_V_id_V_1_state(1);
    AXI_video_strm_V_id_V_1_ack_out <= m_axis_video_TREADY;
    AXI_video_strm_V_id_V_1_data_out <= ap_const_lv1_0;
    AXI_video_strm_V_id_V_1_sel <= AXI_video_strm_V_id_V_1_sel_rd;

    AXI_video_strm_V_id_V_1_vld_in_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter1, exitcond3_i_i_reg_603, ap_block_pp0_stage0_flag00011001)
    begin
        if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_lv1_0 = exitcond3_i_i_reg_603) and (ap_block_pp0_stage0_flag00011001 = ap_const_boolean_0))) then 
            AXI_video_strm_V_id_V_1_vld_in <= ap_const_logic_1;
        else 
            AXI_video_strm_V_id_V_1_vld_in <= ap_const_logic_0;
        end if; 
    end process;

    AXI_video_strm_V_id_V_1_vld_out <= AXI_video_strm_V_id_V_1_state(0);
    AXI_video_strm_V_keep_V_1_ack_in <= AXI_video_strm_V_keep_V_1_state(1);
    AXI_video_strm_V_keep_V_1_ack_out <= m_axis_video_TREADY;
    AXI_video_strm_V_keep_V_1_data_out <= ap_const_lv3_7;
    AXI_video_strm_V_keep_V_1_sel <= AXI_video_strm_V_keep_V_1_sel_rd;

    AXI_video_strm_V_keep_V_1_vld_in_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter1, exitcond3_i_i_reg_603, ap_block_pp0_stage0_flag00011001)
    begin
        if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_lv1_0 = exitcond3_i_i_reg_603) and (ap_block_pp0_stage0_flag00011001 = ap_const_boolean_0))) then 
            AXI_video_strm_V_keep_V_1_vld_in <= ap_const_logic_1;
        else 
            AXI_video_strm_V_keep_V_1_vld_in <= ap_const_logic_0;
        end if; 
    end process;

    AXI_video_strm_V_keep_V_1_vld_out <= AXI_video_strm_V_keep_V_1_state(0);
    AXI_video_strm_V_last_V_1_ack_in <= AXI_video_strm_V_last_V_1_state(1);
    AXI_video_strm_V_last_V_1_ack_out <= m_axis_video_TREADY;

    AXI_video_strm_V_last_V_1_data_out_assign_proc : process(AXI_video_strm_V_last_V_1_payload_A, AXI_video_strm_V_last_V_1_payload_B, AXI_video_strm_V_last_V_1_sel)
    begin
        if ((ap_const_logic_1 = AXI_video_strm_V_last_V_1_sel)) then 
            AXI_video_strm_V_last_V_1_data_out <= AXI_video_strm_V_last_V_1_payload_B;
        else 
            AXI_video_strm_V_last_V_1_data_out <= AXI_video_strm_V_last_V_1_payload_A;
        end if; 
    end process;

    AXI_video_strm_V_last_V_1_load_A <= (AXI_video_strm_V_last_V_1_state_cmp_full and not(AXI_video_strm_V_last_V_1_sel_wr));
    AXI_video_strm_V_last_V_1_load_B <= (AXI_video_strm_V_last_V_1_sel_wr and AXI_video_strm_V_last_V_1_state_cmp_full);
    AXI_video_strm_V_last_V_1_sel <= AXI_video_strm_V_last_V_1_sel_rd;
    AXI_video_strm_V_last_V_1_state_cmp_full <= '0' when (AXI_video_strm_V_last_V_1_state = ap_const_lv2_1) else '1';

    AXI_video_strm_V_last_V_1_vld_in_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter1, exitcond3_i_i_reg_603, ap_block_pp0_stage0_flag00011001)
    begin
        if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_lv1_0 = exitcond3_i_i_reg_603) and (ap_block_pp0_stage0_flag00011001 = ap_const_boolean_0))) then 
            AXI_video_strm_V_last_V_1_vld_in <= ap_const_logic_1;
        else 
            AXI_video_strm_V_last_V_1_vld_in <= ap_const_logic_0;
        end if; 
    end process;

    AXI_video_strm_V_last_V_1_vld_out <= AXI_video_strm_V_last_V_1_state(0);
    AXI_video_strm_V_strb_V_1_ack_in <= AXI_video_strm_V_strb_V_1_state(1);
    AXI_video_strm_V_strb_V_1_ack_out <= m_axis_video_TREADY;
    AXI_video_strm_V_strb_V_1_data_out <= ap_const_lv3_0;
    AXI_video_strm_V_strb_V_1_sel <= AXI_video_strm_V_strb_V_1_sel_rd;

    AXI_video_strm_V_strb_V_1_vld_in_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter1, exitcond3_i_i_reg_603, ap_block_pp0_stage0_flag00011001)
    begin
        if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_lv1_0 = exitcond3_i_i_reg_603) and (ap_block_pp0_stage0_flag00011001 = ap_const_boolean_0))) then 
            AXI_video_strm_V_strb_V_1_vld_in <= ap_const_logic_1;
        else 
            AXI_video_strm_V_strb_V_1_vld_in <= ap_const_logic_0;
        end if; 
    end process;

    AXI_video_strm_V_strb_V_1_vld_out <= AXI_video_strm_V_strb_V_1_state(0);
    AXI_video_strm_V_user_V_1_ack_in <= AXI_video_strm_V_user_V_1_state(1);
    AXI_video_strm_V_user_V_1_ack_out <= m_axis_video_TREADY;

    AXI_video_strm_V_user_V_1_data_out_assign_proc : process(AXI_video_strm_V_user_V_1_payload_A, AXI_video_strm_V_user_V_1_payload_B, AXI_video_strm_V_user_V_1_sel)
    begin
        if ((ap_const_logic_1 = AXI_video_strm_V_user_V_1_sel)) then 
            AXI_video_strm_V_user_V_1_data_out <= AXI_video_strm_V_user_V_1_payload_B;
        else 
            AXI_video_strm_V_user_V_1_data_out <= AXI_video_strm_V_user_V_1_payload_A;
        end if; 
    end process;

    AXI_video_strm_V_user_V_1_load_A <= (AXI_video_strm_V_user_V_1_state_cmp_full and not(AXI_video_strm_V_user_V_1_sel_wr));
    AXI_video_strm_V_user_V_1_load_B <= (AXI_video_strm_V_user_V_1_sel_wr and AXI_video_strm_V_user_V_1_state_cmp_full);
    AXI_video_strm_V_user_V_1_sel <= AXI_video_strm_V_user_V_1_sel_rd;
    AXI_video_strm_V_user_V_1_state_cmp_full <= '0' when (AXI_video_strm_V_user_V_1_state = ap_const_lv2_1) else '1';

    AXI_video_strm_V_user_V_1_vld_in_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter1, exitcond3_i_i_reg_603, ap_block_pp0_stage0_flag00011001)
    begin
        if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_lv1_0 = exitcond3_i_i_reg_603) and (ap_block_pp0_stage0_flag00011001 = ap_const_boolean_0))) then 
            AXI_video_strm_V_user_V_1_vld_in <= ap_const_logic_1;
        else 
            AXI_video_strm_V_user_V_1_vld_in <= ap_const_logic_0;
        end if; 
    end process;

    AXI_video_strm_V_user_V_1_vld_out <= AXI_video_strm_V_user_V_1_state(0);
    Height_cast_i_i_fu_259_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(HwReg_height_cast9_loc_dout),10));

    HwReg_height_cast9_loc_blk_n_assign_proc : process(ap_start, ap_done_reg, ap_CS_fsm_state1, HwReg_height_cast9_loc_empty_n)
    begin
        if (((ap_const_logic_1 = ap_CS_fsm_state1) and not(((ap_const_logic_0 = ap_start) or (ap_done_reg = ap_const_logic_1))))) then 
            HwReg_height_cast9_loc_blk_n <= HwReg_height_cast9_loc_empty_n;
        else 
            HwReg_height_cast9_loc_blk_n <= ap_const_logic_1;
        end if; 
    end process;


    HwReg_height_cast9_loc_read_assign_proc : process(ap_start, ap_done_reg, ap_CS_fsm_state1, HwReg_height_cast9_loc_empty_n, tmp_4_loc_empty_n)
    begin
        if (((ap_const_logic_1 = ap_CS_fsm_state1) and not(((ap_const_logic_0 = ap_start) or (ap_done_reg = ap_const_logic_1) or (ap_const_logic_0 = HwReg_height_cast9_loc_empty_n) or (ap_const_logic_0 = tmp_4_loc_empty_n))))) then 
            HwReg_height_cast9_loc_read <= ap_const_logic_1;
        else 
            HwReg_height_cast9_loc_read <= ap_const_logic_0;
        end if; 
    end process;

    StrmMPix_V_val_0_V0_status <= (StrmMPix_V_val_0_V_empty_n and StrmMPix_V_val_1_V_empty_n and StrmMPix_V_val_2_V_empty_n);

    StrmMPix_V_val_0_V0_update_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter1, exitcond3_i_i_reg_603, ap_block_pp0_stage0_flag00011001)
    begin
        if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_lv1_0 = exitcond3_i_i_reg_603) and (ap_block_pp0_stage0_flag00011001 = ap_const_boolean_0))) then 
            StrmMPix_V_val_0_V0_update <= ap_const_logic_1;
        else 
            StrmMPix_V_val_0_V0_update <= ap_const_logic_0;
        end if; 
    end process;


    StrmMPix_V_val_0_V_blk_n_assign_proc : process(StrmMPix_V_val_0_V_empty_n, ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter1, ap_block_pp0_stage0_flag00000000, exitcond3_i_i_reg_603)
    begin
        if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage0_flag00000000 = ap_const_boolean_0) and (ap_const_lv1_0 = exitcond3_i_i_reg_603))) then 
            StrmMPix_V_val_0_V_blk_n <= StrmMPix_V_val_0_V_empty_n;
        else 
            StrmMPix_V_val_0_V_blk_n <= ap_const_logic_1;
        end if; 
    end process;

    StrmMPix_V_val_0_V_read <= StrmMPix_V_val_0_V0_update;

    StrmMPix_V_val_1_V_blk_n_assign_proc : process(StrmMPix_V_val_1_V_empty_n, ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter1, ap_block_pp0_stage0_flag00000000, exitcond3_i_i_reg_603)
    begin
        if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage0_flag00000000 = ap_const_boolean_0) and (ap_const_lv1_0 = exitcond3_i_i_reg_603))) then 
            StrmMPix_V_val_1_V_blk_n <= StrmMPix_V_val_1_V_empty_n;
        else 
            StrmMPix_V_val_1_V_blk_n <= ap_const_logic_1;
        end if; 
    end process;

    StrmMPix_V_val_1_V_read <= StrmMPix_V_val_0_V0_update;

    StrmMPix_V_val_2_V_blk_n_assign_proc : process(StrmMPix_V_val_2_V_empty_n, ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter1, ap_block_pp0_stage0_flag00000000, exitcond3_i_i_reg_603)
    begin
        if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage0_flag00000000 = ap_const_boolean_0) and (ap_const_lv1_0 = exitcond3_i_i_reg_603))) then 
            StrmMPix_V_val_2_V_blk_n <= StrmMPix_V_val_2_V_empty_n;
        else 
            StrmMPix_V_val_2_V_blk_n <= ap_const_logic_1;
        end if; 
    end process;

    StrmMPix_V_val_2_V_read <= StrmMPix_V_val_0_V0_update;
    ap_CS_fsm_pp0_stage0 <= ap_CS_fsm(5);
    ap_CS_fsm_state1 <= ap_CS_fsm(0);
    ap_CS_fsm_state2 <= ap_CS_fsm(1);
    ap_CS_fsm_state3 <= ap_CS_fsm(2);
    ap_CS_fsm_state4 <= ap_CS_fsm(3);
    ap_CS_fsm_state5 <= ap_CS_fsm(4);
    ap_CS_fsm_state9 <= ap_CS_fsm(6);
        ap_block_pp0_stage0_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1));

    ap_block_pp0_stage0_flag00001001_assign_proc : process(ap_enable_reg_pp0_iter1, exitcond3_i_i_reg_603, StrmMPix_V_val_0_V0_status)
    begin
                ap_block_pp0_stage0_flag00001001 <= ((ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_lv1_0 = exitcond3_i_i_reg_603) and (ap_const_logic_0 = StrmMPix_V_val_0_V0_status));
    end process;


    ap_block_pp0_stage0_flag00011001_assign_proc : process(ap_enable_reg_pp0_iter1, exitcond3_i_i_reg_603, ap_enable_reg_pp0_iter2, StrmMPix_V_val_0_V0_status, ap_block_state7_io, ap_block_state8_io)
    begin
                ap_block_pp0_stage0_flag00011001 <= (((ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (((ap_const_lv1_0 = exitcond3_i_i_reg_603) and (ap_const_logic_0 = StrmMPix_V_val_0_V0_status)) or (ap_const_boolean_1 = ap_block_state7_io))) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter2) and (ap_const_boolean_1 = ap_block_state8_io)));
    end process;


    ap_block_pp0_stage0_flag00011011_assign_proc : process(ap_enable_reg_pp0_iter1, exitcond3_i_i_reg_603, ap_enable_reg_pp0_iter2, StrmMPix_V_val_0_V0_status, ap_block_state7_io, ap_block_state8_io)
    begin
                ap_block_pp0_stage0_flag00011011 <= (((ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (((ap_const_lv1_0 = exitcond3_i_i_reg_603) and (ap_const_logic_0 = StrmMPix_V_val_0_V0_status)) or (ap_const_boolean_1 = ap_block_state7_io))) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter2) and (ap_const_boolean_1 = ap_block_state8_io)));
    end process;


    ap_block_state1_assign_proc : process(ap_start, ap_done_reg, HwReg_height_cast9_loc_empty_n, tmp_4_loc_empty_n)
    begin
                ap_block_state1 <= ((ap_const_logic_0 = ap_start) or (ap_done_reg = ap_const_logic_1) or (ap_const_logic_0 = HwReg_height_cast9_loc_empty_n) or (ap_const_logic_0 = tmp_4_loc_empty_n));
    end process;


    ap_block_state1_ignore_call18_assign_proc : process(ap_start, ap_done_reg, HwReg_height_cast9_loc_empty_n, tmp_4_loc_empty_n)
    begin
                ap_block_state1_ignore_call18 <= ((ap_const_logic_0 = ap_start) or (ap_done_reg = ap_const_logic_1) or (ap_const_logic_0 = HwReg_height_cast9_loc_empty_n) or (ap_const_logic_0 = tmp_4_loc_empty_n));
    end process;


    ap_block_state1_ignore_call19_assign_proc : process(ap_start, ap_done_reg, HwReg_height_cast9_loc_empty_n, tmp_4_loc_empty_n)
    begin
                ap_block_state1_ignore_call19 <= ((ap_const_logic_0 = ap_start) or (ap_done_reg = ap_const_logic_1) or (ap_const_logic_0 = HwReg_height_cast9_loc_empty_n) or (ap_const_logic_0 = tmp_4_loc_empty_n));
    end process;


    ap_block_state2_on_subcall_done_assign_proc : process(grp_reg_unsigned_short_s_fu_263_ap_done, grp_reg_unsigned_short_s_fu_269_ap_done)
    begin
                ap_block_state2_on_subcall_done <= ((ap_const_logic_0 = grp_reg_unsigned_short_s_fu_263_ap_done) or (ap_const_logic_0 = grp_reg_unsigned_short_s_fu_269_ap_done));
    end process;


    ap_block_state5_assign_proc : process(AXI_video_strm_V_data_V_1_ack_in, AXI_video_strm_V_keep_V_1_ack_in, AXI_video_strm_V_strb_V_1_ack_in, AXI_video_strm_V_user_V_1_ack_in, AXI_video_strm_V_last_V_1_ack_in, AXI_video_strm_V_id_V_1_ack_in, AXI_video_strm_V_dest_V_1_ack_in)
    begin
                ap_block_state5 <= ((ap_const_logic_0 = AXI_video_strm_V_data_V_1_ack_in) or (ap_const_logic_0 = AXI_video_strm_V_keep_V_1_ack_in) or (ap_const_logic_0 = AXI_video_strm_V_strb_V_1_ack_in) or (ap_const_logic_0 = AXI_video_strm_V_user_V_1_ack_in) or (ap_const_logic_0 = AXI_video_strm_V_last_V_1_ack_in) or (ap_const_logic_0 = AXI_video_strm_V_id_V_1_ack_in) or (ap_const_logic_0 = AXI_video_strm_V_dest_V_1_ack_in));
    end process;

        ap_block_state6_pp0_stage0_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1));

    ap_block_state7_io_assign_proc : process(AXI_video_strm_V_data_V_1_ack_in, exitcond3_i_i_reg_603)
    begin
                ap_block_state7_io <= ((ap_const_lv1_0 = exitcond3_i_i_reg_603) and (ap_const_logic_0 = AXI_video_strm_V_data_V_1_ack_in));
    end process;


    ap_block_state7_pp0_stage0_iter1_assign_proc : process(exitcond3_i_i_reg_603, StrmMPix_V_val_0_V0_status)
    begin
                ap_block_state7_pp0_stage0_iter1 <= ((ap_const_lv1_0 = exitcond3_i_i_reg_603) and (ap_const_logic_0 = StrmMPix_V_val_0_V0_status));
    end process;


    ap_block_state8_io_assign_proc : process(AXI_video_strm_V_data_V_1_ack_in, ap_reg_pp0_iter1_exitcond3_i_i_reg_603)
    begin
                ap_block_state8_io <= ((ap_const_lv1_0 = ap_reg_pp0_iter1_exitcond3_i_i_reg_603) and (ap_const_logic_0 = AXI_video_strm_V_data_V_1_ack_in));
    end process;

        ap_block_state8_pp0_stage0_iter2 <= not((ap_const_boolean_1 = ap_const_boolean_1));

    ap_condition_pp0_exit_iter0_state6_assign_proc : process(exitcond3_i_i_fu_422_p2)
    begin
        if ((ap_const_lv1_1 = exitcond3_i_i_fu_422_p2)) then 
            ap_condition_pp0_exit_iter0_state6 <= ap_const_logic_1;
        else 
            ap_condition_pp0_exit_iter0_state6 <= ap_const_logic_0;
        end if; 
    end process;


    ap_done_assign_proc : process(ap_done_reg, AXI_video_strm_V_data_V_1_ack_in, AXI_video_strm_V_keep_V_1_ack_in, AXI_video_strm_V_strb_V_1_ack_in, AXI_video_strm_V_user_V_1_ack_in, AXI_video_strm_V_last_V_1_ack_in, AXI_video_strm_V_id_V_1_ack_in, AXI_video_strm_V_dest_V_1_ack_in, exitcond2_i_i_fu_407_p2, ap_CS_fsm_state5)
    begin
        if (((ap_const_logic_1 = ap_CS_fsm_state5) and not(((ap_const_logic_0 = AXI_video_strm_V_data_V_1_ack_in) or (ap_const_logic_0 = AXI_video_strm_V_keep_V_1_ack_in) or (ap_const_logic_0 = AXI_video_strm_V_strb_V_1_ack_in) or (ap_const_logic_0 = AXI_video_strm_V_user_V_1_ack_in) or (ap_const_logic_0 = AXI_video_strm_V_last_V_1_ack_in) or (ap_const_logic_0 = AXI_video_strm_V_id_V_1_ack_in) or (ap_const_logic_0 = AXI_video_strm_V_dest_V_1_ack_in))) and (ap_const_lv1_1 = exitcond2_i_i_fu_407_p2))) then 
            ap_done <= ap_const_logic_1;
        else 
            ap_done <= ap_done_reg;
        end if; 
    end process;

    ap_enable_pp0 <= (ap_idle_pp0 xor ap_const_logic_1);

    ap_idle_assign_proc : process(ap_start, ap_CS_fsm_state1)
    begin
        if (((ap_const_logic_0 = ap_start) and (ap_const_logic_1 = ap_CS_fsm_state1))) then 
            ap_idle <= ap_const_logic_1;
        else 
            ap_idle <= ap_const_logic_0;
        end if; 
    end process;


    ap_idle_pp0_assign_proc : process(ap_enable_reg_pp0_iter1, ap_enable_reg_pp0_iter2, ap_enable_reg_pp0_iter0)
    begin
        if (((ap_const_logic_0 = ap_enable_reg_pp0_iter0) and (ap_const_logic_0 = ap_enable_reg_pp0_iter1) and (ap_const_logic_0 = ap_enable_reg_pp0_iter2))) then 
            ap_idle_pp0 <= ap_const_logic_1;
        else 
            ap_idle_pp0 <= ap_const_logic_0;
        end if; 
    end process;


    ap_ready_assign_proc : process(AXI_video_strm_V_data_V_1_ack_in, AXI_video_strm_V_keep_V_1_ack_in, AXI_video_strm_V_strb_V_1_ack_in, AXI_video_strm_V_user_V_1_ack_in, AXI_video_strm_V_last_V_1_ack_in, AXI_video_strm_V_id_V_1_ack_in, AXI_video_strm_V_dest_V_1_ack_in, exitcond2_i_i_fu_407_p2, ap_CS_fsm_state5)
    begin
        if (((ap_const_logic_1 = ap_CS_fsm_state5) and not(((ap_const_logic_0 = AXI_video_strm_V_data_V_1_ack_in) or (ap_const_logic_0 = AXI_video_strm_V_keep_V_1_ack_in) or (ap_const_logic_0 = AXI_video_strm_V_strb_V_1_ack_in) or (ap_const_logic_0 = AXI_video_strm_V_user_V_1_ack_in) or (ap_const_logic_0 = AXI_video_strm_V_last_V_1_ack_in) or (ap_const_logic_0 = AXI_video_strm_V_id_V_1_ack_in) or (ap_const_logic_0 = AXI_video_strm_V_dest_V_1_ack_in))) and (ap_const_lv1_1 = exitcond2_i_i_fu_407_p2))) then 
            ap_ready <= ap_const_logic_1;
        else 
            ap_ready <= ap_const_logic_0;
        end if; 
    end process;

    axi_last_V_fu_433_p2 <= "1" when (j_cast_i_i_fu_418_p1 = tmp_7_i_i_reg_559) else "0";
    cols_cast_i_i_fu_275_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(grp_reg_unsigned_short_s_fu_269_ap_return),11));
    exitcond1_i_i_fu_313_p2 <= "1" when (i_i_i_reg_221 = ap_const_lv2_3) else "0";
    exitcond2_i_i_fu_407_p2 <= "1" when (i1_cast_i_i_fu_403_p1 = tmp_i_i_reg_519) else "0";
    exitcond3_i_i_fu_422_p2 <= "1" when (j_i_i_reg_244 = tmp_i_i_61_reg_524) else "0";
    grp_reg_unsigned_short_s_fu_263_ap_start <= ap_reg_grp_reg_unsigned_short_s_fu_263_ap_start;
    grp_reg_unsigned_short_s_fu_269_ap_start <= ap_reg_grp_reg_unsigned_short_s_fu_269_ap_start;
    grp_reg_unsigned_short_s_fu_269_in_r <= HwReg_width(10 - 1 downto 0);
    i1_cast_i_i_fu_403_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(i1_i_i_reg_233),10));
    i_1_fu_412_p2 <= std_logic_vector(unsigned(i1_i_i_reg_233) + unsigned(ap_const_lv9_1));
    i_cast6_i_i_cast_fu_299_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(i_i_i_reg_221),5));
    i_fu_319_p2 <= std_logic_vector(unsigned(i_i_i_reg_221) + unsigned(ap_const_lv2_1));
    j_cast_i_i_fu_418_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(j_i_i_reg_244),11));
    j_fu_427_p2 <= std_logic_vector(unsigned(j_i_i_reg_244) + unsigned(ap_const_lv10_1));
    m_axis_video_TDATA <= AXI_video_strm_V_data_V_1_data_out;

    m_axis_video_TDATA_blk_n_assign_proc : process(AXI_video_strm_V_data_V_1_state, ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter1, ap_block_pp0_stage0_flag00000000, exitcond3_i_i_reg_603, ap_enable_reg_pp0_iter2, ap_reg_pp0_iter1_exitcond3_i_i_reg_603)
    begin
        if ((((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage0_flag00000000 = ap_const_boolean_0) and (ap_const_lv1_0 = exitcond3_i_i_reg_603)) or ((ap_block_pp0_stage0_flag00000000 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2) and (ap_const_lv1_0 = ap_reg_pp0_iter1_exitcond3_i_i_reg_603)))) then 
            m_axis_video_TDATA_blk_n <= AXI_video_strm_V_data_V_1_state(1);
        else 
            m_axis_video_TDATA_blk_n <= ap_const_logic_1;
        end if; 
    end process;

    m_axis_video_TDEST <= AXI_video_strm_V_dest_V_1_data_out;
    m_axis_video_TID <= AXI_video_strm_V_id_V_1_data_out;
    m_axis_video_TKEEP <= AXI_video_strm_V_keep_V_1_data_out;
    m_axis_video_TLAST <= AXI_video_strm_V_last_V_1_data_out;
    m_axis_video_TSTRB <= AXI_video_strm_V_strb_V_1_data_out;
    m_axis_video_TUSER <= AXI_video_strm_V_user_V_1_data_out;
    m_axis_video_TVALID <= AXI_video_strm_V_dest_V_1_state(0);
    mapComp_address0 <= tmp_5_cast_fu_308_p1(4 - 1 downto 0);

    mapComp_ce0_assign_proc : process(ap_CS_fsm_state3)
    begin
        if ((ap_const_logic_1 = ap_CS_fsm_state3)) then 
            mapComp_ce0 <= ap_const_logic_1;
        else 
            mapComp_ce0 <= ap_const_logic_0;
        end if; 
    end process;

    map_0_V_cast_fu_347_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(mapComp_q0),5));
    map_2_V_1_fu_371_p3 <= 
        map_V_2_i_i_reg_185 when (sel_tmp2_fu_365_p2(0) = '1') else 
        map_2_V_fu_357_p3;
    map_2_V_2_fu_379_p3 <= 
        map_0_V_cast_fu_347_p1 when (sel_tmp_fu_351_p2(0) = '1') else 
        map_V_1_i_i_reg_197;
    map_2_V_3_fu_387_p3 <= 
        map_V_1_i_i_reg_197 when (sel_tmp2_fu_365_p2(0) = '1') else 
        map_2_V_2_fu_379_p3;
    map_2_V_5_fu_395_p3 <= 
        map_0_V_cast_fu_347_p1 when (sel_tmp2_fu_365_p2(0) = '1') else 
        map_2_V_4_reg_209;
    map_2_V_fu_357_p3 <= 
        map_V_2_i_i_reg_185 when (sel_tmp_fu_351_p2(0) = '1') else 
        map_0_V_cast_fu_347_p1;
    p_shl_cast_fu_289_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_3_fu_282_p3),5));
    sel_tmp2_fu_365_p2 <= "1" when (i_i_i_reg_221 = ap_const_lv2_0) else "0";
    sel_tmp_fu_351_p2 <= "1" when (i_i_i_reg_221 = ap_const_lv2_1) else "0";
    tmp_3_fu_282_p3 <= (tmp_4_loc_read_reg_508 & ap_const_lv2_0);
    tmp_4_fu_293_p2 <= std_logic_vector(unsigned(p_shl_cast_fu_289_p1) - unsigned(tmp_5_i_i_cast_fu_279_p1));

    tmp_4_loc_blk_n_assign_proc : process(ap_start, ap_done_reg, ap_CS_fsm_state1, tmp_4_loc_empty_n)
    begin
        if (((ap_const_logic_1 = ap_CS_fsm_state1) and not(((ap_const_logic_0 = ap_start) or (ap_done_reg = ap_const_logic_1))))) then 
            tmp_4_loc_blk_n <= tmp_4_loc_empty_n;
        else 
            tmp_4_loc_blk_n <= ap_const_logic_1;
        end if; 
    end process;


    tmp_4_loc_read_assign_proc : process(ap_start, ap_done_reg, ap_CS_fsm_state1, HwReg_height_cast9_loc_empty_n, tmp_4_loc_empty_n)
    begin
        if (((ap_const_logic_1 = ap_CS_fsm_state1) and not(((ap_const_logic_0 = ap_start) or (ap_done_reg = ap_const_logic_1) or (ap_const_logic_0 = HwReg_height_cast9_loc_empty_n) or (ap_const_logic_0 = tmp_4_loc_empty_n))))) then 
            tmp_4_loc_read <= ap_const_logic_1;
        else 
            tmp_4_loc_read <= ap_const_logic_0;
        end if; 
    end process;

        tmp_5_cast_fu_308_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(tmp_5_fu_303_p2),32));

    tmp_5_fu_303_p2 <= std_logic_vector(unsigned(tmp_4_reg_534) + unsigned(i_cast6_i_i_cast_fu_299_p1));
    tmp_5_i_i_cast_fu_279_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_4_loc_read_reg_508),5));
    tmp_7_fu_330_p1 <= map_2_V_4_reg_209(2 - 1 downto 0);
    tmp_7_i_i_fu_325_p2 <= std_logic_vector(signed(ap_const_lv11_7FF) + signed(cols_cast_i_i_reg_529));
    tmp_8_fu_334_p1 <= map_V_1_i_i_reg_197(2 - 1 downto 0);
    tmp_9_fu_338_p1 <= map_V_2_i_i_reg_185(2 - 1 downto 0);
    tmp_data_V_fu_487_p4 <= ((tmp_2_fu_476_p5 & tmp_1_fu_465_p5) & tmp_fu_454_p5);
end behav;
