// ==============================================================
// RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2017.2
// Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved.
// 
// ===========================================================

`timescale 1 ns / 1 ps 

module AXIvideo2Mat (
        ap_clk,
        ap_rst,
        ap_start,
        start_full_n,
        ap_ready,
        ap_done,
        ap_continue,
        ap_idle,
        start_out,
        start_write,
        video_in_TDATA,
        video_in_TVALID,
        video_in_TREADY,
        video_in_TKEEP,
        video_in_TSTRB,
        video_in_TUSER,
        video_in_TLAST,
        video_in_TID,
        video_in_TDEST,
        img_rows_V_dout,
        img_rows_V_empty_n,
        img_rows_V_read,
        img_cols_V_dout,
        img_cols_V_empty_n,
        img_cols_V_read,
        img_data_stream_0_V_din,
        img_data_stream_0_V_full_n,
        img_data_stream_0_V_write,
        img_data_stream_1_V_din,
        img_data_stream_1_V_full_n,
        img_data_stream_1_V_write,
        img_data_stream_2_V_din,
        img_data_stream_2_V_full_n,
        img_data_stream_2_V_write,
        img_rows_V_out_din,
        img_rows_V_out_full_n,
        img_rows_V_out_write,
        img_cols_V_out_din,
        img_cols_V_out_full_n,
        img_cols_V_out_write
);

parameter    ap_ST_fsm_state1 = 8'd1;
parameter    ap_ST_fsm_state2 = 8'd2;
parameter    ap_ST_fsm_state3 = 8'd4;
parameter    ap_ST_fsm_state4 = 8'd8;
parameter    ap_ST_fsm_pp1_stage0 = 8'd16;
parameter    ap_ST_fsm_state7 = 8'd32;
parameter    ap_ST_fsm_pp2_stage0 = 8'd64;
parameter    ap_ST_fsm_state10 = 8'd128;

input   ap_clk;
input   ap_rst;
input   ap_start;
input   start_full_n;
output   ap_ready;
output   ap_done;
input   ap_continue;
output   ap_idle;
output   start_out;
output   start_write;
input  [23:0] video_in_TDATA;
input   video_in_TVALID;
output   video_in_TREADY;
input  [2:0] video_in_TKEEP;
input  [2:0] video_in_TSTRB;
input  [0:0] video_in_TUSER;
input  [0:0] video_in_TLAST;
input  [0:0] video_in_TID;
input  [0:0] video_in_TDEST;
input  [9:0] img_rows_V_dout;
input   img_rows_V_empty_n;
output   img_rows_V_read;
input  [10:0] img_cols_V_dout;
input   img_cols_V_empty_n;
output   img_cols_V_read;
output  [7:0] img_data_stream_0_V_din;
input   img_data_stream_0_V_full_n;
output   img_data_stream_0_V_write;
output  [7:0] img_data_stream_1_V_din;
input   img_data_stream_1_V_full_n;
output   img_data_stream_1_V_write;
output  [7:0] img_data_stream_2_V_din;
input   img_data_stream_2_V_full_n;
output   img_data_stream_2_V_write;
output  [9:0] img_rows_V_out_din;
input   img_rows_V_out_full_n;
output   img_rows_V_out_write;
output  [10:0] img_cols_V_out_din;
input   img_cols_V_out_full_n;
output   img_cols_V_out_write;

reg ap_done;
reg ap_idle;
reg img_rows_V_read;
reg img_cols_V_read;
reg img_data_stream_0_V_write;
reg img_data_stream_1_V_write;
reg img_data_stream_2_V_write;
reg img_rows_V_out_write;
reg img_cols_V_out_write;

reg    real_start;
reg    real_start_status_reg;
reg    internal_ap_ready;
reg    ap_done_reg;
(* fsm_encoding = "none" *) reg   [7:0] ap_CS_fsm;
wire    ap_CS_fsm_state1;
reg    start_once_reg;
reg    start_control_reg;
reg   [23:0] AXI_video_strm_V_data_V_0_data_out;
wire    AXI_video_strm_V_data_V_0_vld_in;
wire    AXI_video_strm_V_data_V_0_vld_out;
wire    AXI_video_strm_V_data_V_0_ack_in;
reg    AXI_video_strm_V_data_V_0_ack_out;
reg   [23:0] AXI_video_strm_V_data_V_0_payload_A;
reg   [23:0] AXI_video_strm_V_data_V_0_payload_B;
reg    AXI_video_strm_V_data_V_0_sel_rd;
reg    AXI_video_strm_V_data_V_0_sel_wr;
wire    AXI_video_strm_V_data_V_0_sel;
wire    AXI_video_strm_V_data_V_0_load_A;
wire    AXI_video_strm_V_data_V_0_load_B;
reg   [1:0] AXI_video_strm_V_data_V_0_state;
wire    AXI_video_strm_V_data_V_0_state_cmp_full;
reg   [0:0] AXI_video_strm_V_user_V_0_data_out;
wire    AXI_video_strm_V_user_V_0_vld_in;
wire    AXI_video_strm_V_user_V_0_vld_out;
wire    AXI_video_strm_V_user_V_0_ack_in;
reg    AXI_video_strm_V_user_V_0_ack_out;
reg   [0:0] AXI_video_strm_V_user_V_0_payload_A;
reg   [0:0] AXI_video_strm_V_user_V_0_payload_B;
reg    AXI_video_strm_V_user_V_0_sel_rd;
reg    AXI_video_strm_V_user_V_0_sel_wr;
wire    AXI_video_strm_V_user_V_0_sel;
wire    AXI_video_strm_V_user_V_0_load_A;
wire    AXI_video_strm_V_user_V_0_load_B;
reg   [1:0] AXI_video_strm_V_user_V_0_state;
wire    AXI_video_strm_V_user_V_0_state_cmp_full;
reg   [0:0] AXI_video_strm_V_last_V_0_data_out;
wire    AXI_video_strm_V_last_V_0_vld_in;
wire    AXI_video_strm_V_last_V_0_vld_out;
wire    AXI_video_strm_V_last_V_0_ack_in;
reg    AXI_video_strm_V_last_V_0_ack_out;
reg   [0:0] AXI_video_strm_V_last_V_0_payload_A;
reg   [0:0] AXI_video_strm_V_last_V_0_payload_B;
reg    AXI_video_strm_V_last_V_0_sel_rd;
reg    AXI_video_strm_V_last_V_0_sel_wr;
wire    AXI_video_strm_V_last_V_0_sel;
wire    AXI_video_strm_V_last_V_0_load_A;
wire    AXI_video_strm_V_last_V_0_load_B;
reg   [1:0] AXI_video_strm_V_last_V_0_state;
wire    AXI_video_strm_V_last_V_0_state_cmp_full;
wire    AXI_video_strm_V_dest_V_0_vld_in;
reg    AXI_video_strm_V_dest_V_0_ack_out;
reg   [1:0] AXI_video_strm_V_dest_V_0_state;
reg    video_in_TDATA_blk_n;
wire    ap_CS_fsm_state2;
wire    ap_CS_fsm_pp1_stage0;
reg    ap_enable_reg_pp1_iter1;
wire    ap_block_pp1_stage0_flag00000000;
reg   [0:0] exitcond_i_reg_446;
reg   [0:0] brmerge_i_reg_455;
wire    ap_CS_fsm_pp2_stage0;
reg    ap_enable_reg_pp2_iter1;
wire    ap_block_pp2_stage0_flag00000000;
reg   [0:0] eol_2_i_reg_282;
reg    img_rows_V_blk_n;
reg    img_cols_V_blk_n;
reg    img_data_stream_0_V_blk_n;
reg    img_data_stream_1_V_blk_n;
reg    img_data_stream_2_V_blk_n;
reg    img_rows_V_out_blk_n;
reg    img_cols_V_out_blk_n;
reg   [9:0] t_V_6_reg_212;
reg   [0:0] eol_i_reg_223;
reg   [0:0] eol_reg_235;
reg   [23:0] axi_data_V_1_i_reg_246;
reg   [0:0] axi_last_V_3_i_reg_293;
reg   [23:0] axi_data_V_3_i_reg_305;
reg   [9:0] img_rows_V_read_reg_407;
reg    ap_block_state1;
reg   [10:0] img_cols_V_read_reg_412;
reg   [23:0] tmp_data_V_reg_417;
reg   [0:0] tmp_last_V_reg_425;
wire   [0:0] exitcond7_i_fu_340_p2;
wire    ap_CS_fsm_state4;
wire   [8:0] i_V_fu_345_p2;
reg   [8:0] i_V_reg_441;
wire   [0:0] exitcond_i_fu_355_p2;
wire    ap_block_state5_pp1_stage0_iter0;
reg    ap_predicate_op73_read_state6;
reg    ap_block_state6_pp1_stage0_iter1;
reg    ap_block_pp1_stage0_flag00011001;
wire   [9:0] j_V_fu_360_p2;
reg    ap_enable_reg_pp1_iter0;
wire   [0:0] brmerge_i_fu_369_p2;
wire    ap_block_state8_pp2_stage0_iter0;
reg    ap_block_state9_pp2_stage0_iter1;
reg    ap_block_pp2_stage0_flag00011001;
reg    ap_block_pp1_stage0_flag00011011;
reg    ap_enable_reg_pp2_iter0;
wire    ap_CS_fsm_state7;
reg    ap_block_pp2_stage0_flag00011011;
reg   [0:0] eol_2_i_phi_fu_285_p4;
reg   [0:0] axi_last_V1_i_reg_181;
wire    ap_CS_fsm_state10;
wire    ap_CS_fsm_state3;
reg   [23:0] axi_data_V1_i_reg_191;
reg   [8:0] t_V_reg_201;
reg   [0:0] eol_i_phi_fu_227_p4;
reg   [0:0] axi_last_V_2_i_phi_fu_262_p4;
reg   [23:0] p_Val2_s_phi_fu_274_p4;
wire   [0:0] ap_phi_precharge_reg_pp1_iter1_axi_last_V_2_i_reg_257;
wire   [23:0] ap_phi_precharge_reg_pp1_iter1_p_Val2_s_reg_270;
reg    ap_block_pp1_stage0_flag00001001;
reg   [0:0] sof_1_i_fu_110;
wire   [9:0] t_V_cast_cast_i_fu_336_p1;
wire   [10:0] t_V_6_cast_cast_i_fu_351_p1;
wire   [0:0] tmp_user_V_fu_327_p1;
reg   [7:0] ap_NS_fsm;
reg    ap_idle_pp1;
wire    ap_enable_pp1;
reg    ap_idle_pp2;
wire    ap_enable_pp2;
reg    ap_condition_535;

// power-on initialization
initial begin
#0 real_start_status_reg = 1'b0;
#0 ap_done_reg = 1'b0;
#0 ap_CS_fsm = 8'd1;
#0 start_once_reg = 1'b0;
#0 start_control_reg = 1'b0;
#0 AXI_video_strm_V_data_V_0_sel_rd = 1'b0;
#0 AXI_video_strm_V_data_V_0_sel_wr = 1'b0;
#0 AXI_video_strm_V_data_V_0_state = 2'd0;
#0 AXI_video_strm_V_user_V_0_sel_rd = 1'b0;
#0 AXI_video_strm_V_user_V_0_sel_wr = 1'b0;
#0 AXI_video_strm_V_user_V_0_state = 2'd0;
#0 AXI_video_strm_V_last_V_0_sel_rd = 1'b0;
#0 AXI_video_strm_V_last_V_0_sel_wr = 1'b0;
#0 AXI_video_strm_V_last_V_0_state = 2'd0;
#0 AXI_video_strm_V_dest_V_0_state = 2'd0;
#0 ap_enable_reg_pp1_iter1 = 1'b0;
#0 ap_enable_reg_pp2_iter1 = 1'b0;
#0 ap_enable_reg_pp1_iter0 = 1'b0;
#0 ap_enable_reg_pp2_iter0 = 1'b0;
end

always @ (posedge ap_clk) begin
    if (ap_rst == 1'b1) begin
        AXI_video_strm_V_data_V_0_sel_rd <= 1'b0;
    end else begin
        if (((1'b1 == AXI_video_strm_V_data_V_0_ack_out) & (1'b1 == AXI_video_strm_V_data_V_0_vld_out))) begin
            AXI_video_strm_V_data_V_0_sel_rd <= ~AXI_video_strm_V_data_V_0_sel_rd;
        end
    end
end

always @ (posedge ap_clk) begin
    if (ap_rst == 1'b1) begin
        AXI_video_strm_V_data_V_0_sel_wr <= 1'b0;
    end else begin
        if (((1'b1 == AXI_video_strm_V_data_V_0_vld_in) & (1'b1 == AXI_video_strm_V_data_V_0_ack_in))) begin
            AXI_video_strm_V_data_V_0_sel_wr <= ~AXI_video_strm_V_data_V_0_sel_wr;
        end
    end
end

always @ (posedge ap_clk) begin
    if (ap_rst == 1'b1) begin
        AXI_video_strm_V_data_V_0_state <= 2'd0;
    end else begin
        if ((((1'b0 == AXI_video_strm_V_data_V_0_vld_in) & (1'b1 == AXI_video_strm_V_data_V_0_ack_out) & (AXI_video_strm_V_data_V_0_state == 2'd3)) | ((1'b0 == AXI_video_strm_V_data_V_0_vld_in) & (AXI_video_strm_V_data_V_0_state == 2'd2)))) begin
            AXI_video_strm_V_data_V_0_state <= 2'd2;
        end else if ((((1'b1 == AXI_video_strm_V_data_V_0_vld_in) & (1'b0 == AXI_video_strm_V_data_V_0_ack_out) & (AXI_video_strm_V_data_V_0_state == 2'd3)) | ((1'b0 == AXI_video_strm_V_data_V_0_ack_out) & (AXI_video_strm_V_data_V_0_state == 2'd1)))) begin
            AXI_video_strm_V_data_V_0_state <= 2'd1;
        end else if ((((1'b1 == AXI_video_strm_V_data_V_0_vld_in) & (AXI_video_strm_V_data_V_0_state == 2'd2)) | ((1'b1 == AXI_video_strm_V_data_V_0_ack_out) & (AXI_video_strm_V_data_V_0_state == 2'd1)) | ((AXI_video_strm_V_data_V_0_state == 2'd3) & ~((1'b1 == AXI_video_strm_V_data_V_0_vld_in) & (1'b0 == AXI_video_strm_V_data_V_0_ack_out)) & ~((1'b0 == AXI_video_strm_V_data_V_0_vld_in) & (1'b1 == AXI_video_strm_V_data_V_0_ack_out))))) begin
            AXI_video_strm_V_data_V_0_state <= 2'd3;
        end else begin
            AXI_video_strm_V_data_V_0_state <= 2'd2;
        end
    end
end

always @ (posedge ap_clk) begin
    if (ap_rst == 1'b1) begin
        AXI_video_strm_V_dest_V_0_state <= 2'd0;
    end else begin
        if ((((1'b0 == AXI_video_strm_V_dest_V_0_vld_in) & (1'b1 == AXI_video_strm_V_dest_V_0_ack_out) & (2'd3 == AXI_video_strm_V_dest_V_0_state)) | ((1'b0 == AXI_video_strm_V_dest_V_0_vld_in) & (2'd2 == AXI_video_strm_V_dest_V_0_state)))) begin
            AXI_video_strm_V_dest_V_0_state <= 2'd2;
        end else if ((((1'b1 == AXI_video_strm_V_dest_V_0_vld_in) & (1'b0 == AXI_video_strm_V_dest_V_0_ack_out) & (2'd3 == AXI_video_strm_V_dest_V_0_state)) | ((1'b0 == AXI_video_strm_V_dest_V_0_ack_out) & (2'd1 == AXI_video_strm_V_dest_V_0_state)))) begin
            AXI_video_strm_V_dest_V_0_state <= 2'd1;
        end else if ((((1'b1 == AXI_video_strm_V_dest_V_0_vld_in) & (2'd2 == AXI_video_strm_V_dest_V_0_state)) | ((1'b1 == AXI_video_strm_V_dest_V_0_ack_out) & (2'd1 == AXI_video_strm_V_dest_V_0_state)) | ((2'd3 == AXI_video_strm_V_dest_V_0_state) & ~((1'b1 == AXI_video_strm_V_dest_V_0_vld_in) & (1'b0 == AXI_video_strm_V_dest_V_0_ack_out)) & ~((1'b0 == AXI_video_strm_V_dest_V_0_vld_in) & (1'b1 == AXI_video_strm_V_dest_V_0_ack_out))))) begin
            AXI_video_strm_V_dest_V_0_state <= 2'd3;
        end else begin
            AXI_video_strm_V_dest_V_0_state <= 2'd2;
        end
    end
end

always @ (posedge ap_clk) begin
    if (ap_rst == 1'b1) begin
        AXI_video_strm_V_last_V_0_sel_rd <= 1'b0;
    end else begin
        if (((1'b1 == AXI_video_strm_V_last_V_0_ack_out) & (1'b1 == AXI_video_strm_V_last_V_0_vld_out))) begin
            AXI_video_strm_V_last_V_0_sel_rd <= ~AXI_video_strm_V_last_V_0_sel_rd;
        end
    end
end

always @ (posedge ap_clk) begin
    if (ap_rst == 1'b1) begin
        AXI_video_strm_V_last_V_0_sel_wr <= 1'b0;
    end else begin
        if (((1'b1 == AXI_video_strm_V_last_V_0_vld_in) & (1'b1 == AXI_video_strm_V_last_V_0_ack_in))) begin
            AXI_video_strm_V_last_V_0_sel_wr <= ~AXI_video_strm_V_last_V_0_sel_wr;
        end
    end
end

always @ (posedge ap_clk) begin
    if (ap_rst == 1'b1) begin
        AXI_video_strm_V_last_V_0_state <= 2'd0;
    end else begin
        if ((((1'b0 == AXI_video_strm_V_last_V_0_vld_in) & (1'b1 == AXI_video_strm_V_last_V_0_ack_out) & (2'd3 == AXI_video_strm_V_last_V_0_state)) | ((1'b0 == AXI_video_strm_V_last_V_0_vld_in) & (2'd2 == AXI_video_strm_V_last_V_0_state)))) begin
            AXI_video_strm_V_last_V_0_state <= 2'd2;
        end else if ((((1'b1 == AXI_video_strm_V_last_V_0_vld_in) & (1'b0 == AXI_video_strm_V_last_V_0_ack_out) & (2'd3 == AXI_video_strm_V_last_V_0_state)) | ((1'b0 == AXI_video_strm_V_last_V_0_ack_out) & (2'd1 == AXI_video_strm_V_last_V_0_state)))) begin
            AXI_video_strm_V_last_V_0_state <= 2'd1;
        end else if ((((1'b1 == AXI_video_strm_V_last_V_0_vld_in) & (2'd2 == AXI_video_strm_V_last_V_0_state)) | ((1'b1 == AXI_video_strm_V_last_V_0_ack_out) & (2'd1 == AXI_video_strm_V_last_V_0_state)) | ((2'd3 == AXI_video_strm_V_last_V_0_state) & ~((1'b1 == AXI_video_strm_V_last_V_0_vld_in) & (1'b0 == AXI_video_strm_V_last_V_0_ack_out)) & ~((1'b0 == AXI_video_strm_V_last_V_0_vld_in) & (1'b1 == AXI_video_strm_V_last_V_0_ack_out))))) begin
            AXI_video_strm_V_last_V_0_state <= 2'd3;
        end else begin
            AXI_video_strm_V_last_V_0_state <= 2'd2;
        end
    end
end

always @ (posedge ap_clk) begin
    if (ap_rst == 1'b1) begin
        AXI_video_strm_V_user_V_0_sel_rd <= 1'b0;
    end else begin
        if (((1'b1 == AXI_video_strm_V_user_V_0_ack_out) & (1'b1 == AXI_video_strm_V_user_V_0_vld_out))) begin
            AXI_video_strm_V_user_V_0_sel_rd <= ~AXI_video_strm_V_user_V_0_sel_rd;
        end
    end
end

always @ (posedge ap_clk) begin
    if (ap_rst == 1'b1) begin
        AXI_video_strm_V_user_V_0_sel_wr <= 1'b0;
    end else begin
        if (((1'b1 == AXI_video_strm_V_user_V_0_vld_in) & (1'b1 == AXI_video_strm_V_user_V_0_ack_in))) begin
            AXI_video_strm_V_user_V_0_sel_wr <= ~AXI_video_strm_V_user_V_0_sel_wr;
        end
    end
end

always @ (posedge ap_clk) begin
    if (ap_rst == 1'b1) begin
        AXI_video_strm_V_user_V_0_state <= 2'd0;
    end else begin
        if ((((1'b0 == AXI_video_strm_V_user_V_0_vld_in) & (1'b1 == AXI_video_strm_V_user_V_0_ack_out) & (2'd3 == AXI_video_strm_V_user_V_0_state)) | ((1'b0 == AXI_video_strm_V_user_V_0_vld_in) & (2'd2 == AXI_video_strm_V_user_V_0_state)))) begin
            AXI_video_strm_V_user_V_0_state <= 2'd2;
        end else if ((((1'b1 == AXI_video_strm_V_user_V_0_vld_in) & (1'b0 == AXI_video_strm_V_user_V_0_ack_out) & (2'd3 == AXI_video_strm_V_user_V_0_state)) | ((1'b0 == AXI_video_strm_V_user_V_0_ack_out) & (2'd1 == AXI_video_strm_V_user_V_0_state)))) begin
            AXI_video_strm_V_user_V_0_state <= 2'd1;
        end else if ((((1'b1 == AXI_video_strm_V_user_V_0_vld_in) & (2'd2 == AXI_video_strm_V_user_V_0_state)) | ((1'b1 == AXI_video_strm_V_user_V_0_ack_out) & (2'd1 == AXI_video_strm_V_user_V_0_state)) | ((2'd3 == AXI_video_strm_V_user_V_0_state) & ~((1'b1 == AXI_video_strm_V_user_V_0_vld_in) & (1'b0 == AXI_video_strm_V_user_V_0_ack_out)) & ~((1'b0 == AXI_video_strm_V_user_V_0_vld_in) & (1'b1 == AXI_video_strm_V_user_V_0_ack_out))))) begin
            AXI_video_strm_V_user_V_0_state <= 2'd3;
        end else begin
            AXI_video_strm_V_user_V_0_state <= 2'd2;
        end
    end
end

always @ (posedge ap_clk) begin
    if (ap_rst == 1'b1) begin
        ap_CS_fsm <= ap_ST_fsm_state1;
    end else begin
        ap_CS_fsm <= ap_NS_fsm;
    end
end

always @ (posedge ap_clk) begin
    if (ap_rst == 1'b1) begin
        ap_done_reg <= 1'b0;
    end else begin
        if ((1'b1 == ap_continue)) begin
            ap_done_reg <= 1'b0;
        end else if (((1'b1 == ap_CS_fsm_state4) & (1'd1 == exitcond7_i_fu_340_p2))) begin
            ap_done_reg <= 1'b1;
        end
    end
end

always @ (posedge ap_clk) begin
    if (ap_rst == 1'b1) begin
        ap_enable_reg_pp1_iter0 <= 1'b0;
    end else begin
        if (((1'b1 == ap_CS_fsm_pp1_stage0) & (ap_block_pp1_stage0_flag00011011 == 1'b0) & (1'd1 == exitcond_i_fu_355_p2))) begin
            ap_enable_reg_pp1_iter0 <= 1'b0;
        end else if (((1'b1 == ap_CS_fsm_state4) & (1'd0 == exitcond7_i_fu_340_p2))) begin
            ap_enable_reg_pp1_iter0 <= 1'b1;
        end
    end
end

always @ (posedge ap_clk) begin
    if (ap_rst == 1'b1) begin
        ap_enable_reg_pp1_iter1 <= 1'b0;
    end else begin
        if ((ap_block_pp1_stage0_flag00011011 == 1'b0)) begin
            ap_enable_reg_pp1_iter1 <= ap_enable_reg_pp1_iter0;
        end else if (((1'b1 == ap_CS_fsm_state4) & (1'd0 == exitcond7_i_fu_340_p2))) begin
            ap_enable_reg_pp1_iter1 <= 1'b0;
        end
    end
end

always @ (posedge ap_clk) begin
    if (ap_rst == 1'b1) begin
        ap_enable_reg_pp2_iter0 <= 1'b0;
    end else begin
        if (((1'b1 == ap_CS_fsm_pp2_stage0) & (ap_block_pp2_stage0_flag00011011 == 1'b0) & (1'd1 == eol_2_i_phi_fu_285_p4))) begin
            ap_enable_reg_pp2_iter0 <= 1'b0;
        end else if ((1'b1 == ap_CS_fsm_state7)) begin
            ap_enable_reg_pp2_iter0 <= 1'b1;
        end
    end
end

always @ (posedge ap_clk) begin
    if (ap_rst == 1'b1) begin
        ap_enable_reg_pp2_iter1 <= 1'b0;
    end else begin
        if ((ap_block_pp2_stage0_flag00011011 == 1'b0)) begin
            ap_enable_reg_pp2_iter1 <= ap_enable_reg_pp2_iter0;
        end else if ((1'b1 == ap_CS_fsm_state7)) begin
            ap_enable_reg_pp2_iter1 <= 1'b0;
        end
    end
end

always @ (posedge ap_clk) begin
    if (ap_rst == 1'b1) begin
        real_start_status_reg <= 1'b0;
    end else begin
        if ((start_full_n == 1'b1)) begin
            real_start_status_reg <= 1'b0;
        end else if (((1'b0 == start_full_n) & (1'b1 == internal_ap_ready))) begin
            real_start_status_reg <= 1'b1;
        end
    end
end

always @ (posedge ap_clk) begin
    if (ap_rst == 1'b1) begin
        start_control_reg <= 1'b0;
    end else begin
        if (((1'b1 == real_start) & ((1'b1 == internal_ap_ready) | (1'b0 == start_once_reg)))) begin
            start_control_reg <= 1'b1;
        end else if ((1'b1 == start_control_reg)) begin
            start_control_reg <= 1'b0;
        end
    end
end

always @ (posedge ap_clk) begin
    if (ap_rst == 1'b1) begin
        start_once_reg <= 1'b0;
    end else begin
        if ((1'b1 == real_start)) begin
            start_once_reg <= 1'b1;
        end else if ((1'b0 == ap_start)) begin
            start_once_reg <= 1'b0;
        end
    end
end

always @ (posedge ap_clk) begin
    if ((1'b1 == ap_CS_fsm_state3)) begin
        axi_data_V1_i_reg_191 <= tmp_data_V_reg_417;
    end else if ((1'b1 == ap_CS_fsm_state10)) begin
        axi_data_V1_i_reg_191 <= axi_data_V_3_i_reg_305;
    end
end

always @ (posedge ap_clk) begin
    if (((1'b1 == ap_CS_fsm_pp1_stage0) & (1'b1 == ap_enable_reg_pp1_iter1) & (1'd0 == exitcond_i_reg_446) & (ap_block_pp1_stage0_flag00011001 == 1'b0))) begin
        axi_data_V_1_i_reg_246 <= p_Val2_s_phi_fu_274_p4;
    end else if (((1'b1 == ap_CS_fsm_state4) & (1'd0 == exitcond7_i_fu_340_p2))) begin
        axi_data_V_1_i_reg_246 <= axi_data_V1_i_reg_191;
    end
end

always @ (posedge ap_clk) begin
    if ((1'b1 == ap_CS_fsm_state7)) begin
        axi_data_V_3_i_reg_305 <= axi_data_V_1_i_reg_246;
    end else if (((1'b1 == ap_CS_fsm_pp2_stage0) & (1'b1 == ap_enable_reg_pp2_iter1) & (1'd0 == eol_2_i_reg_282) & (ap_block_pp2_stage0_flag00011001 == 1'b0))) begin
        axi_data_V_3_i_reg_305 <= AXI_video_strm_V_data_V_0_data_out;
    end
end

always @ (posedge ap_clk) begin
    if ((1'b1 == ap_CS_fsm_state3)) begin
        axi_last_V1_i_reg_181 <= tmp_last_V_reg_425;
    end else if ((1'b1 == ap_CS_fsm_state10)) begin
        axi_last_V1_i_reg_181 <= axi_last_V_3_i_reg_293;
    end
end

always @ (posedge ap_clk) begin
    if ((1'b1 == ap_CS_fsm_state7)) begin
        axi_last_V_3_i_reg_293 <= eol_reg_235;
    end else if (((1'b1 == ap_CS_fsm_pp2_stage0) & (1'b1 == ap_enable_reg_pp2_iter1) & (1'd0 == eol_2_i_reg_282) & (ap_block_pp2_stage0_flag00011001 == 1'b0))) begin
        axi_last_V_3_i_reg_293 <= AXI_video_strm_V_last_V_0_data_out;
    end
end

always @ (posedge ap_clk) begin
    if ((1'b1 == ap_CS_fsm_state7)) begin
        eol_2_i_reg_282 <= eol_i_reg_223;
    end else if (((1'b1 == ap_CS_fsm_pp2_stage0) & (1'b1 == ap_enable_reg_pp2_iter1) & (1'd0 == eol_2_i_reg_282) & (ap_block_pp2_stage0_flag00011001 == 1'b0))) begin
        eol_2_i_reg_282 <= AXI_video_strm_V_last_V_0_data_out;
    end
end

always @ (posedge ap_clk) begin
    if (((1'b1 == ap_CS_fsm_pp1_stage0) & (1'b1 == ap_enable_reg_pp1_iter1) & (1'd0 == exitcond_i_reg_446) & (ap_block_pp1_stage0_flag00011001 == 1'b0))) begin
        eol_i_reg_223 <= axi_last_V_2_i_phi_fu_262_p4;
    end else if (((1'b1 == ap_CS_fsm_state4) & (1'd0 == exitcond7_i_fu_340_p2))) begin
        eol_i_reg_223 <= 1'd0;
    end
end

always @ (posedge ap_clk) begin
    if (((1'b1 == ap_CS_fsm_pp1_stage0) & (1'b1 == ap_enable_reg_pp1_iter1) & (1'd0 == exitcond_i_reg_446) & (ap_block_pp1_stage0_flag00011001 == 1'b0))) begin
        eol_reg_235 <= axi_last_V_2_i_phi_fu_262_p4;
    end else if (((1'b1 == ap_CS_fsm_state4) & (1'd0 == exitcond7_i_fu_340_p2))) begin
        eol_reg_235 <= axi_last_V1_i_reg_181;
    end
end

always @ (posedge ap_clk) begin
    if (((1'b1 == ap_CS_fsm_pp1_stage0) & (ap_block_pp1_stage0_flag00011001 == 1'b0) & (1'b1 == ap_enable_reg_pp1_iter0) & (1'd0 == exitcond_i_fu_355_p2))) begin
        sof_1_i_fu_110 <= 1'd0;
    end else if ((1'b1 == ap_CS_fsm_state3)) begin
        sof_1_i_fu_110 <= 1'd1;
    end
end

always @ (posedge ap_clk) begin
    if (((1'b1 == ap_CS_fsm_pp1_stage0) & (ap_block_pp1_stage0_flag00011001 == 1'b0) & (1'b1 == ap_enable_reg_pp1_iter0) & (1'd0 == exitcond_i_fu_355_p2))) begin
        t_V_6_reg_212 <= j_V_fu_360_p2;
    end else if (((1'b1 == ap_CS_fsm_state4) & (1'd0 == exitcond7_i_fu_340_p2))) begin
        t_V_6_reg_212 <= 10'd0;
    end
end

always @ (posedge ap_clk) begin
    if ((1'b1 == ap_CS_fsm_state3)) begin
        t_V_reg_201 <= 9'd0;
    end else if ((1'b1 == ap_CS_fsm_state10)) begin
        t_V_reg_201 <= i_V_reg_441;
    end
end

always @ (posedge ap_clk) begin
    if ((1'b1 == AXI_video_strm_V_data_V_0_load_A)) begin
        AXI_video_strm_V_data_V_0_payload_A <= video_in_TDATA;
    end
end

always @ (posedge ap_clk) begin
    if ((1'b1 == AXI_video_strm_V_data_V_0_load_B)) begin
        AXI_video_strm_V_data_V_0_payload_B <= video_in_TDATA;
    end
end

always @ (posedge ap_clk) begin
    if ((1'b1 == AXI_video_strm_V_last_V_0_load_A)) begin
        AXI_video_strm_V_last_V_0_payload_A <= video_in_TLAST;
    end
end

always @ (posedge ap_clk) begin
    if ((1'b1 == AXI_video_strm_V_last_V_0_load_B)) begin
        AXI_video_strm_V_last_V_0_payload_B <= video_in_TLAST;
    end
end

always @ (posedge ap_clk) begin
    if ((1'b1 == AXI_video_strm_V_user_V_0_load_A)) begin
        AXI_video_strm_V_user_V_0_payload_A <= video_in_TUSER;
    end
end

always @ (posedge ap_clk) begin
    if ((1'b1 == AXI_video_strm_V_user_V_0_load_B)) begin
        AXI_video_strm_V_user_V_0_payload_B <= video_in_TUSER;
    end
end

always @ (posedge ap_clk) begin
    if (((1'b1 == ap_CS_fsm_pp1_stage0) & (ap_block_pp1_stage0_flag00011001 == 1'b0) & (1'd0 == exitcond_i_fu_355_p2))) begin
        brmerge_i_reg_455 <= brmerge_i_fu_369_p2;
    end
end

always @ (posedge ap_clk) begin
    if (((1'b1 == ap_CS_fsm_pp1_stage0) & (ap_block_pp1_stage0_flag00011001 == 1'b0))) begin
        exitcond_i_reg_446 <= exitcond_i_fu_355_p2;
    end
end

always @ (posedge ap_clk) begin
    if ((1'b1 == ap_CS_fsm_state4)) begin
        i_V_reg_441 <= i_V_fu_345_p2;
    end
end

always @ (posedge ap_clk) begin
    if (((1'b1 == ap_CS_fsm_state1) & ~((1'b0 == real_start) | (ap_done_reg == 1'b1) | (1'b0 == img_rows_V_empty_n) | (1'b0 == img_cols_V_empty_n) | (1'b0 == img_rows_V_out_full_n) | (1'b0 == img_cols_V_out_full_n)))) begin
        img_cols_V_read_reg_412 <= img_cols_V_dout;
        img_rows_V_read_reg_407 <= img_rows_V_dout;
    end
end

always @ (posedge ap_clk) begin
    if (((1'b1 == ap_CS_fsm_state2) & (AXI_video_strm_V_data_V_0_vld_out == 1'b1))) begin
        tmp_data_V_reg_417 <= AXI_video_strm_V_data_V_0_data_out;
        tmp_last_V_reg_425 <= AXI_video_strm_V_last_V_0_data_out;
    end
end

always @ (*) begin
    if ((((1'b1 == ap_CS_fsm_state2) & (AXI_video_strm_V_data_V_0_vld_out == 1'b1)) | ((1'b1 == ap_CS_fsm_pp2_stage0) & (1'b1 == ap_enable_reg_pp2_iter1) & (1'd0 == eol_2_i_reg_282) & (ap_block_pp2_stage0_flag00011001 == 1'b0)) | ((1'b1 == ap_CS_fsm_pp1_stage0) & (1'b1 == ap_enable_reg_pp1_iter1) & (1'b1 == ap_predicate_op73_read_state6) & (ap_block_pp1_stage0_flag00011001 == 1'b0)))) begin
        AXI_video_strm_V_data_V_0_ack_out = 1'b1;
    end else begin
        AXI_video_strm_V_data_V_0_ack_out = 1'b0;
    end
end

always @ (*) begin
    if ((1'b1 == AXI_video_strm_V_data_V_0_sel)) begin
        AXI_video_strm_V_data_V_0_data_out = AXI_video_strm_V_data_V_0_payload_B;
    end else begin
        AXI_video_strm_V_data_V_0_data_out = AXI_video_strm_V_data_V_0_payload_A;
    end
end

always @ (*) begin
    if ((((1'b1 == ap_CS_fsm_state2) & (AXI_video_strm_V_data_V_0_vld_out == 1'b1)) | ((1'b1 == ap_CS_fsm_pp2_stage0) & (1'b1 == ap_enable_reg_pp2_iter1) & (1'd0 == eol_2_i_reg_282) & (ap_block_pp2_stage0_flag00011001 == 1'b0)) | ((1'b1 == ap_CS_fsm_pp1_stage0) & (1'b1 == ap_enable_reg_pp1_iter1) & (1'b1 == ap_predicate_op73_read_state6) & (ap_block_pp1_stage0_flag00011001 == 1'b0)))) begin
        AXI_video_strm_V_dest_V_0_ack_out = 1'b1;
    end else begin
        AXI_video_strm_V_dest_V_0_ack_out = 1'b0;
    end
end

always @ (*) begin
    if ((((1'b1 == ap_CS_fsm_state2) & (AXI_video_strm_V_data_V_0_vld_out == 1'b1)) | ((1'b1 == ap_CS_fsm_pp2_stage0) & (1'b1 == ap_enable_reg_pp2_iter1) & (1'd0 == eol_2_i_reg_282) & (ap_block_pp2_stage0_flag00011001 == 1'b0)) | ((1'b1 == ap_CS_fsm_pp1_stage0) & (1'b1 == ap_enable_reg_pp1_iter1) & (1'b1 == ap_predicate_op73_read_state6) & (ap_block_pp1_stage0_flag00011001 == 1'b0)))) begin
        AXI_video_strm_V_last_V_0_ack_out = 1'b1;
    end else begin
        AXI_video_strm_V_last_V_0_ack_out = 1'b0;
    end
end

always @ (*) begin
    if ((1'b1 == AXI_video_strm_V_last_V_0_sel)) begin
        AXI_video_strm_V_last_V_0_data_out = AXI_video_strm_V_last_V_0_payload_B;
    end else begin
        AXI_video_strm_V_last_V_0_data_out = AXI_video_strm_V_last_V_0_payload_A;
    end
end

always @ (*) begin
    if ((((1'b1 == ap_CS_fsm_state2) & (AXI_video_strm_V_data_V_0_vld_out == 1'b1)) | ((1'b1 == ap_CS_fsm_pp2_stage0) & (1'b1 == ap_enable_reg_pp2_iter1) & (1'd0 == eol_2_i_reg_282) & (ap_block_pp2_stage0_flag00011001 == 1'b0)) | ((1'b1 == ap_CS_fsm_pp1_stage0) & (1'b1 == ap_enable_reg_pp1_iter1) & (1'b1 == ap_predicate_op73_read_state6) & (ap_block_pp1_stage0_flag00011001 == 1'b0)))) begin
        AXI_video_strm_V_user_V_0_ack_out = 1'b1;
    end else begin
        AXI_video_strm_V_user_V_0_ack_out = 1'b0;
    end
end

always @ (*) begin
    if ((1'b1 == AXI_video_strm_V_user_V_0_sel)) begin
        AXI_video_strm_V_user_V_0_data_out = AXI_video_strm_V_user_V_0_payload_B;
    end else begin
        AXI_video_strm_V_user_V_0_data_out = AXI_video_strm_V_user_V_0_payload_A;
    end
end

always @ (*) begin
    if (((1'b1 == ap_CS_fsm_state4) & (1'd1 == exitcond7_i_fu_340_p2))) begin
        ap_done = 1'b1;
    end else begin
        ap_done = ap_done_reg;
    end
end

always @ (*) begin
    if (((1'b0 == real_start) & (1'b1 == ap_CS_fsm_state1))) begin
        ap_idle = 1'b1;
    end else begin
        ap_idle = 1'b0;
    end
end

always @ (*) begin
    if (((1'b0 == ap_enable_reg_pp1_iter0) & (1'b0 == ap_enable_reg_pp1_iter1))) begin
        ap_idle_pp1 = 1'b1;
    end else begin
        ap_idle_pp1 = 1'b0;
    end
end

always @ (*) begin
    if (((1'b0 == ap_enable_reg_pp2_iter0) & (1'b0 == ap_enable_reg_pp2_iter1))) begin
        ap_idle_pp2 = 1'b1;
    end else begin
        ap_idle_pp2 = 1'b0;
    end
end

always @ (*) begin
    if ((ap_condition_535 == 1'b1)) begin
        if ((1'd1 == brmerge_i_reg_455)) begin
            axi_last_V_2_i_phi_fu_262_p4 = eol_reg_235;
        end else if ((1'd0 == brmerge_i_reg_455)) begin
            axi_last_V_2_i_phi_fu_262_p4 = AXI_video_strm_V_last_V_0_data_out;
        end else begin
            axi_last_V_2_i_phi_fu_262_p4 = ap_phi_precharge_reg_pp1_iter1_axi_last_V_2_i_reg_257;
        end
    end else begin
        axi_last_V_2_i_phi_fu_262_p4 = ap_phi_precharge_reg_pp1_iter1_axi_last_V_2_i_reg_257;
    end
end

always @ (*) begin
    if (((1'b1 == ap_CS_fsm_pp2_stage0) & (1'b1 == ap_enable_reg_pp2_iter1) & (ap_block_pp2_stage0_flag00000000 == 1'b0) & (1'd0 == eol_2_i_reg_282))) begin
        eol_2_i_phi_fu_285_p4 = AXI_video_strm_V_last_V_0_data_out;
    end else begin
        eol_2_i_phi_fu_285_p4 = eol_2_i_reg_282;
    end
end

always @ (*) begin
    if (((1'b1 == ap_CS_fsm_pp1_stage0) & (1'b1 == ap_enable_reg_pp1_iter1) & (ap_block_pp1_stage0_flag00000000 == 1'b0) & (1'd0 == exitcond_i_reg_446))) begin
        eol_i_phi_fu_227_p4 = axi_last_V_2_i_phi_fu_262_p4;
    end else begin
        eol_i_phi_fu_227_p4 = eol_i_reg_223;
    end
end

always @ (*) begin
    if (((1'b1 == ap_CS_fsm_state1) & ~((1'b0 == real_start) | (ap_done_reg == 1'b1)))) begin
        img_cols_V_blk_n = img_cols_V_empty_n;
    end else begin
        img_cols_V_blk_n = 1'b1;
    end
end

always @ (*) begin
    if (((1'b1 == ap_CS_fsm_state1) & ~((1'b0 == real_start) | (ap_done_reg == 1'b1)))) begin
        img_cols_V_out_blk_n = img_cols_V_out_full_n;
    end else begin
        img_cols_V_out_blk_n = 1'b1;
    end
end

always @ (*) begin
    if (((1'b1 == ap_CS_fsm_state1) & ~((1'b0 == real_start) | (ap_done_reg == 1'b1) | (1'b0 == img_rows_V_empty_n) | (1'b0 == img_cols_V_empty_n) | (1'b0 == img_rows_V_out_full_n) | (1'b0 == img_cols_V_out_full_n)))) begin
        img_cols_V_out_write = 1'b1;
    end else begin
        img_cols_V_out_write = 1'b0;
    end
end

always @ (*) begin
    if (((1'b1 == ap_CS_fsm_state1) & ~((1'b0 == real_start) | (ap_done_reg == 1'b1) | (1'b0 == img_rows_V_empty_n) | (1'b0 == img_cols_V_empty_n) | (1'b0 == img_rows_V_out_full_n) | (1'b0 == img_cols_V_out_full_n)))) begin
        img_cols_V_read = 1'b1;
    end else begin
        img_cols_V_read = 1'b0;
    end
end

always @ (*) begin
    if (((1'b1 == ap_CS_fsm_pp1_stage0) & (1'b1 == ap_enable_reg_pp1_iter1) & (ap_block_pp1_stage0_flag00000000 == 1'b0) & (1'd0 == exitcond_i_reg_446))) begin
        img_data_stream_0_V_blk_n = img_data_stream_0_V_full_n;
    end else begin
        img_data_stream_0_V_blk_n = 1'b1;
    end
end

always @ (*) begin
    if (((1'b1 == ap_CS_fsm_pp1_stage0) & (1'b1 == ap_enable_reg_pp1_iter1) & (1'd0 == exitcond_i_reg_446) & (ap_block_pp1_stage0_flag00011001 == 1'b0))) begin
        img_data_stream_0_V_write = 1'b1;
    end else begin
        img_data_stream_0_V_write = 1'b0;
    end
end

always @ (*) begin
    if (((1'b1 == ap_CS_fsm_pp1_stage0) & (1'b1 == ap_enable_reg_pp1_iter1) & (ap_block_pp1_stage0_flag00000000 == 1'b0) & (1'd0 == exitcond_i_reg_446))) begin
        img_data_stream_1_V_blk_n = img_data_stream_1_V_full_n;
    end else begin
        img_data_stream_1_V_blk_n = 1'b1;
    end
end

always @ (*) begin
    if (((1'b1 == ap_CS_fsm_pp1_stage0) & (1'b1 == ap_enable_reg_pp1_iter1) & (1'd0 == exitcond_i_reg_446) & (ap_block_pp1_stage0_flag00011001 == 1'b0))) begin
        img_data_stream_1_V_write = 1'b1;
    end else begin
        img_data_stream_1_V_write = 1'b0;
    end
end

always @ (*) begin
    if (((1'b1 == ap_CS_fsm_pp1_stage0) & (1'b1 == ap_enable_reg_pp1_iter1) & (ap_block_pp1_stage0_flag00000000 == 1'b0) & (1'd0 == exitcond_i_reg_446))) begin
        img_data_stream_2_V_blk_n = img_data_stream_2_V_full_n;
    end else begin
        img_data_stream_2_V_blk_n = 1'b1;
    end
end

always @ (*) begin
    if (((1'b1 == ap_CS_fsm_pp1_stage0) & (1'b1 == ap_enable_reg_pp1_iter1) & (1'd0 == exitcond_i_reg_446) & (ap_block_pp1_stage0_flag00011001 == 1'b0))) begin
        img_data_stream_2_V_write = 1'b1;
    end else begin
        img_data_stream_2_V_write = 1'b0;
    end
end

always @ (*) begin
    if (((1'b1 == ap_CS_fsm_state1) & ~((1'b0 == real_start) | (ap_done_reg == 1'b1)))) begin
        img_rows_V_blk_n = img_rows_V_empty_n;
    end else begin
        img_rows_V_blk_n = 1'b1;
    end
end

always @ (*) begin
    if (((1'b1 == ap_CS_fsm_state1) & ~((1'b0 == real_start) | (ap_done_reg == 1'b1)))) begin
        img_rows_V_out_blk_n = img_rows_V_out_full_n;
    end else begin
        img_rows_V_out_blk_n = 1'b1;
    end
end

always @ (*) begin
    if (((1'b1 == ap_CS_fsm_state1) & ~((1'b0 == real_start) | (ap_done_reg == 1'b1) | (1'b0 == img_rows_V_empty_n) | (1'b0 == img_cols_V_empty_n) | (1'b0 == img_rows_V_out_full_n) | (1'b0 == img_cols_V_out_full_n)))) begin
        img_rows_V_out_write = 1'b1;
    end else begin
        img_rows_V_out_write = 1'b0;
    end
end

always @ (*) begin
    if (((1'b1 == ap_CS_fsm_state1) & ~((1'b0 == real_start) | (ap_done_reg == 1'b1) | (1'b0 == img_rows_V_empty_n) | (1'b0 == img_cols_V_empty_n) | (1'b0 == img_rows_V_out_full_n) | (1'b0 == img_cols_V_out_full_n)))) begin
        img_rows_V_read = 1'b1;
    end else begin
        img_rows_V_read = 1'b0;
    end
end

always @ (*) begin
    if (((1'b1 == ap_CS_fsm_state4) & (1'd1 == exitcond7_i_fu_340_p2))) begin
        internal_ap_ready = 1'b1;
    end else begin
        internal_ap_ready = 1'b0;
    end
end

always @ (*) begin
    if ((ap_condition_535 == 1'b1)) begin
        if ((1'd1 == brmerge_i_reg_455)) begin
            p_Val2_s_phi_fu_274_p4 = axi_data_V_1_i_reg_246;
        end else if ((1'd0 == brmerge_i_reg_455)) begin
            p_Val2_s_phi_fu_274_p4 = AXI_video_strm_V_data_V_0_data_out;
        end else begin
            p_Val2_s_phi_fu_274_p4 = ap_phi_precharge_reg_pp1_iter1_p_Val2_s_reg_270;
        end
    end else begin
        p_Val2_s_phi_fu_274_p4 = ap_phi_precharge_reg_pp1_iter1_p_Val2_s_reg_270;
    end
end

always @ (*) begin
    if ((1'b1 == real_start_status_reg)) begin
        real_start = 1'b0;
    end else begin
        real_start = ap_start;
    end
end

always @ (*) begin
    if (((1'b1 == ap_CS_fsm_state2) | ((1'b1 == ap_CS_fsm_pp1_stage0) & (1'b1 == ap_enable_reg_pp1_iter1) & (ap_block_pp1_stage0_flag00000000 == 1'b0) & (1'd0 == exitcond_i_reg_446) & (1'd0 == brmerge_i_reg_455)) | ((1'b1 == ap_CS_fsm_pp2_stage0) & (1'b1 == ap_enable_reg_pp2_iter1) & (ap_block_pp2_stage0_flag00000000 == 1'b0) & (1'd0 == eol_2_i_reg_282)))) begin
        video_in_TDATA_blk_n = AXI_video_strm_V_data_V_0_state[1'd0];
    end else begin
        video_in_TDATA_blk_n = 1'b1;
    end
end

always @ (*) begin
    case (ap_CS_fsm)
        ap_ST_fsm_state1 : begin
            if (((1'b1 == ap_CS_fsm_state1) & ~((1'b0 == real_start) | (ap_done_reg == 1'b1) | (1'b0 == img_rows_V_empty_n) | (1'b0 == img_cols_V_empty_n) | (1'b0 == img_rows_V_out_full_n) | (1'b0 == img_cols_V_out_full_n)))) begin
                ap_NS_fsm = ap_ST_fsm_state2;
            end else begin
                ap_NS_fsm = ap_ST_fsm_state1;
            end
        end
        ap_ST_fsm_state2 : begin
            if (((1'b1 == ap_CS_fsm_state2) & (AXI_video_strm_V_data_V_0_vld_out == 1'b1) & (1'd0 == tmp_user_V_fu_327_p1))) begin
                ap_NS_fsm = ap_ST_fsm_state2;
            end else if (((1'b1 == ap_CS_fsm_state2) & (AXI_video_strm_V_data_V_0_vld_out == 1'b1) & (1'd1 == tmp_user_V_fu_327_p1))) begin
                ap_NS_fsm = ap_ST_fsm_state3;
            end else begin
                ap_NS_fsm = ap_ST_fsm_state2;
            end
        end
        ap_ST_fsm_state3 : begin
            ap_NS_fsm = ap_ST_fsm_state4;
        end
        ap_ST_fsm_state4 : begin
            if (((1'b1 == ap_CS_fsm_state4) & (1'd1 == exitcond7_i_fu_340_p2))) begin
                ap_NS_fsm = ap_ST_fsm_state1;
            end else begin
                ap_NS_fsm = ap_ST_fsm_pp1_stage0;
            end
        end
        ap_ST_fsm_pp1_stage0 : begin
            if (~((1'b1 == ap_CS_fsm_pp1_stage0) & (1'b1 == ap_enable_reg_pp1_iter1) & (ap_block_pp1_stage0_flag00011011 == 1'b0) & (ap_enable_reg_pp1_iter0 == 1'b0))) begin
                ap_NS_fsm = ap_ST_fsm_pp1_stage0;
            end else if (((1'b1 == ap_CS_fsm_pp1_stage0) & (1'b1 == ap_enable_reg_pp1_iter1) & (ap_block_pp1_stage0_flag00011011 == 1'b0) & (ap_enable_reg_pp1_iter0 == 1'b0))) begin
                ap_NS_fsm = ap_ST_fsm_state7;
            end else begin
                ap_NS_fsm = ap_ST_fsm_pp1_stage0;
            end
        end
        ap_ST_fsm_state7 : begin
            ap_NS_fsm = ap_ST_fsm_pp2_stage0;
        end
        ap_ST_fsm_pp2_stage0 : begin
            if (~((1'b1 == ap_CS_fsm_pp2_stage0) & (1'b1 == ap_enable_reg_pp2_iter1) & (ap_block_pp2_stage0_flag00011011 == 1'b0) & (ap_enable_reg_pp2_iter0 == 1'b0))) begin
                ap_NS_fsm = ap_ST_fsm_pp2_stage0;
            end else if (((1'b1 == ap_CS_fsm_pp2_stage0) & (1'b1 == ap_enable_reg_pp2_iter1) & (ap_block_pp2_stage0_flag00011011 == 1'b0) & (ap_enable_reg_pp2_iter0 == 1'b0))) begin
                ap_NS_fsm = ap_ST_fsm_state10;
            end else begin
                ap_NS_fsm = ap_ST_fsm_pp2_stage0;
            end
        end
        ap_ST_fsm_state10 : begin
            ap_NS_fsm = ap_ST_fsm_state4;
        end
        default : begin
            ap_NS_fsm = 'bx;
        end
    endcase
end

assign AXI_video_strm_V_data_V_0_ack_in = AXI_video_strm_V_data_V_0_state[1'd1];

assign AXI_video_strm_V_data_V_0_load_A = (AXI_video_strm_V_data_V_0_state_cmp_full & ~AXI_video_strm_V_data_V_0_sel_wr);

assign AXI_video_strm_V_data_V_0_load_B = (AXI_video_strm_V_data_V_0_sel_wr & AXI_video_strm_V_data_V_0_state_cmp_full);

assign AXI_video_strm_V_data_V_0_sel = AXI_video_strm_V_data_V_0_sel_rd;

assign AXI_video_strm_V_data_V_0_state_cmp_full = ((AXI_video_strm_V_data_V_0_state != 2'd1) ? 1'b1 : 1'b0);

assign AXI_video_strm_V_data_V_0_vld_in = video_in_TVALID;

assign AXI_video_strm_V_data_V_0_vld_out = AXI_video_strm_V_data_V_0_state[1'd0];

assign AXI_video_strm_V_dest_V_0_vld_in = video_in_TVALID;

assign AXI_video_strm_V_last_V_0_ack_in = AXI_video_strm_V_last_V_0_state[1'd1];

assign AXI_video_strm_V_last_V_0_load_A = (AXI_video_strm_V_last_V_0_state_cmp_full & ~AXI_video_strm_V_last_V_0_sel_wr);

assign AXI_video_strm_V_last_V_0_load_B = (AXI_video_strm_V_last_V_0_sel_wr & AXI_video_strm_V_last_V_0_state_cmp_full);

assign AXI_video_strm_V_last_V_0_sel = AXI_video_strm_V_last_V_0_sel_rd;

assign AXI_video_strm_V_last_V_0_state_cmp_full = ((AXI_video_strm_V_last_V_0_state != 2'd1) ? 1'b1 : 1'b0);

assign AXI_video_strm_V_last_V_0_vld_in = video_in_TVALID;

assign AXI_video_strm_V_last_V_0_vld_out = AXI_video_strm_V_last_V_0_state[1'd0];

assign AXI_video_strm_V_user_V_0_ack_in = AXI_video_strm_V_user_V_0_state[1'd1];

assign AXI_video_strm_V_user_V_0_load_A = (AXI_video_strm_V_user_V_0_state_cmp_full & ~AXI_video_strm_V_user_V_0_sel_wr);

assign AXI_video_strm_V_user_V_0_load_B = (AXI_video_strm_V_user_V_0_sel_wr & AXI_video_strm_V_user_V_0_state_cmp_full);

assign AXI_video_strm_V_user_V_0_sel = AXI_video_strm_V_user_V_0_sel_rd;

assign AXI_video_strm_V_user_V_0_state_cmp_full = ((AXI_video_strm_V_user_V_0_state != 2'd1) ? 1'b1 : 1'b0);

assign AXI_video_strm_V_user_V_0_vld_in = video_in_TVALID;

assign AXI_video_strm_V_user_V_0_vld_out = AXI_video_strm_V_user_V_0_state[1'd0];

assign ap_CS_fsm_pp1_stage0 = ap_CS_fsm[32'd4];

assign ap_CS_fsm_pp2_stage0 = ap_CS_fsm[32'd6];

assign ap_CS_fsm_state1 = ap_CS_fsm[32'd0];

assign ap_CS_fsm_state10 = ap_CS_fsm[32'd7];

assign ap_CS_fsm_state2 = ap_CS_fsm[32'd1];

assign ap_CS_fsm_state3 = ap_CS_fsm[32'd2];

assign ap_CS_fsm_state4 = ap_CS_fsm[32'd3];

assign ap_CS_fsm_state7 = ap_CS_fsm[32'd5];

assign ap_block_pp1_stage0_flag00000000 = ~(1'b1 == 1'b1);

always @ (*) begin
    ap_block_pp1_stage0_flag00001001 = ((1'b1 == ap_enable_reg_pp1_iter1) & (((1'b0 == AXI_video_strm_V_data_V_0_vld_out) & (1'b1 == ap_predicate_op73_read_state6)) | ((1'd0 == exitcond_i_reg_446) & (1'b0 == img_data_stream_0_V_full_n)) | ((1'd0 == exitcond_i_reg_446) & (1'b0 == img_data_stream_1_V_full_n)) | ((1'd0 == exitcond_i_reg_446) & (1'b0 == img_data_stream_2_V_full_n))));
end

always @ (*) begin
    ap_block_pp1_stage0_flag00011001 = ((1'b1 == ap_enable_reg_pp1_iter1) & (((1'b0 == AXI_video_strm_V_data_V_0_vld_out) & (1'b1 == ap_predicate_op73_read_state6)) | ((1'd0 == exitcond_i_reg_446) & (1'b0 == img_data_stream_0_V_full_n)) | ((1'd0 == exitcond_i_reg_446) & (1'b0 == img_data_stream_1_V_full_n)) | ((1'd0 == exitcond_i_reg_446) & (1'b0 == img_data_stream_2_V_full_n))));
end

always @ (*) begin
    ap_block_pp1_stage0_flag00011011 = ((1'b1 == ap_enable_reg_pp1_iter1) & (((1'b0 == AXI_video_strm_V_data_V_0_vld_out) & (1'b1 == ap_predicate_op73_read_state6)) | ((1'd0 == exitcond_i_reg_446) & (1'b0 == img_data_stream_0_V_full_n)) | ((1'd0 == exitcond_i_reg_446) & (1'b0 == img_data_stream_1_V_full_n)) | ((1'd0 == exitcond_i_reg_446) & (1'b0 == img_data_stream_2_V_full_n))));
end

assign ap_block_pp2_stage0_flag00000000 = ~(1'b1 == 1'b1);

always @ (*) begin
    ap_block_pp2_stage0_flag00011001 = ((1'b1 == ap_enable_reg_pp2_iter1) & (1'd0 == eol_2_i_reg_282) & (1'b0 == AXI_video_strm_V_data_V_0_vld_out));
end

always @ (*) begin
    ap_block_pp2_stage0_flag00011011 = ((1'b1 == ap_enable_reg_pp2_iter1) & (1'd0 == eol_2_i_reg_282) & (1'b0 == AXI_video_strm_V_data_V_0_vld_out));
end

always @ (*) begin
    ap_block_state1 = ((1'b0 == real_start) | (ap_done_reg == 1'b1) | (1'b0 == img_rows_V_empty_n) | (1'b0 == img_cols_V_empty_n) | (1'b0 == img_rows_V_out_full_n) | (1'b0 == img_cols_V_out_full_n));
end

assign ap_block_state5_pp1_stage0_iter0 = ~(1'b1 == 1'b1);

always @ (*) begin
    ap_block_state6_pp1_stage0_iter1 = (((1'b0 == AXI_video_strm_V_data_V_0_vld_out) & (1'b1 == ap_predicate_op73_read_state6)) | ((1'd0 == exitcond_i_reg_446) & (1'b0 == img_data_stream_0_V_full_n)) | ((1'd0 == exitcond_i_reg_446) & (1'b0 == img_data_stream_1_V_full_n)) | ((1'd0 == exitcond_i_reg_446) & (1'b0 == img_data_stream_2_V_full_n)));
end

assign ap_block_state8_pp2_stage0_iter0 = ~(1'b1 == 1'b1);

always @ (*) begin
    ap_block_state9_pp2_stage0_iter1 = ((1'd0 == eol_2_i_reg_282) & (1'b0 == AXI_video_strm_V_data_V_0_vld_out));
end

always @ (*) begin
    ap_condition_535 = ((1'b1 == ap_CS_fsm_pp1_stage0) & (1'b1 == ap_enable_reg_pp1_iter1) & (ap_block_pp1_stage0_flag00000000 == 1'b0) & (1'd0 == exitcond_i_reg_446));
end

assign ap_enable_pp1 = (ap_idle_pp1 ^ 1'b1);

assign ap_enable_pp2 = (ap_idle_pp2 ^ 1'b1);

assign ap_phi_precharge_reg_pp1_iter1_axi_last_V_2_i_reg_257 = 'bx;

assign ap_phi_precharge_reg_pp1_iter1_p_Val2_s_reg_270 = 'bx;

always @ (*) begin
    ap_predicate_op73_read_state6 = ((1'd0 == exitcond_i_reg_446) & (1'd0 == brmerge_i_reg_455));
end

assign ap_ready = internal_ap_ready;

assign brmerge_i_fu_369_p2 = (sof_1_i_fu_110 | eol_i_phi_fu_227_p4);

assign exitcond7_i_fu_340_p2 = ((t_V_cast_cast_i_fu_336_p1 == img_rows_V_read_reg_407) ? 1'b1 : 1'b0);

assign exitcond_i_fu_355_p2 = ((t_V_6_cast_cast_i_fu_351_p1 == img_cols_V_read_reg_412) ? 1'b1 : 1'b0);

assign i_V_fu_345_p2 = (t_V_reg_201 + 9'd1);

assign img_cols_V_out_din = img_cols_V_dout;

assign img_data_stream_0_V_din = p_Val2_s_phi_fu_274_p4[7:0];

assign img_data_stream_1_V_din = {{p_Val2_s_phi_fu_274_p4[15:8]}};

assign img_data_stream_2_V_din = {{p_Val2_s_phi_fu_274_p4[23:16]}};

assign img_rows_V_out_din = img_rows_V_dout;

assign j_V_fu_360_p2 = (t_V_6_reg_212 + 10'd1);

assign start_out = real_start;

assign start_write = (ap_start & start_control_reg);

assign t_V_6_cast_cast_i_fu_351_p1 = t_V_6_reg_212;

assign t_V_cast_cast_i_fu_336_p1 = t_V_reg_201;

assign tmp_user_V_fu_327_p1 = AXI_video_strm_V_user_V_0_data_out;

assign video_in_TREADY = AXI_video_strm_V_dest_V_0_state[1'd1];

endmodule //AXIvideo2Mat
