// ==============================================================
// RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2017.2
// Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved.
// 
// ===========================================================

`timescale 1 ns / 1 ps 

module design_1_v_frmbuf_rd_0_0_MultiPixStream2AXIvi (
        ap_clk,
        ap_rst,
        ap_start,
        ap_done,
        ap_continue,
        ap_idle,
        ap_ready,
        StrmMPix_V_val_0_V_dout,
        StrmMPix_V_val_0_V_empty_n,
        StrmMPix_V_val_0_V_read,
        StrmMPix_V_val_1_V_dout,
        StrmMPix_V_val_1_V_empty_n,
        StrmMPix_V_val_1_V_read,
        StrmMPix_V_val_2_V_dout,
        StrmMPix_V_val_2_V_empty_n,
        StrmMPix_V_val_2_V_read,
        m_axis_video_TDATA,
        m_axis_video_TVALID,
        m_axis_video_TREADY,
        m_axis_video_TKEEP,
        m_axis_video_TSTRB,
        m_axis_video_TUSER,
        m_axis_video_TLAST,
        m_axis_video_TID,
        m_axis_video_TDEST,
        HwReg_height_cast9_loc_dout,
        HwReg_height_cast9_loc_empty_n,
        HwReg_height_cast9_loc_read,
        HwReg_width,
        tmp_4_loc_dout,
        tmp_4_loc_empty_n,
        tmp_4_loc_read
);

parameter    ap_ST_fsm_state1 = 7'd1;
parameter    ap_ST_fsm_state2 = 7'd2;
parameter    ap_ST_fsm_state3 = 7'd4;
parameter    ap_ST_fsm_state4 = 7'd8;
parameter    ap_ST_fsm_state5 = 7'd16;
parameter    ap_ST_fsm_pp0_stage0 = 7'd32;
parameter    ap_ST_fsm_state9 = 7'd64;

input   ap_clk;
input   ap_rst;
input   ap_start;
output   ap_done;
input   ap_continue;
output   ap_idle;
output   ap_ready;
input  [7:0] StrmMPix_V_val_0_V_dout;
input   StrmMPix_V_val_0_V_empty_n;
output   StrmMPix_V_val_0_V_read;
input  [7:0] StrmMPix_V_val_1_V_dout;
input   StrmMPix_V_val_1_V_empty_n;
output   StrmMPix_V_val_1_V_read;
input  [7:0] StrmMPix_V_val_2_V_dout;
input   StrmMPix_V_val_2_V_empty_n;
output   StrmMPix_V_val_2_V_read;
output  [23:0] m_axis_video_TDATA;
output   m_axis_video_TVALID;
input   m_axis_video_TREADY;
output  [2:0] m_axis_video_TKEEP;
output  [2:0] m_axis_video_TSTRB;
output  [0:0] m_axis_video_TUSER;
output  [0:0] m_axis_video_TLAST;
output  [0:0] m_axis_video_TID;
output  [0:0] m_axis_video_TDEST;
input  [8:0] HwReg_height_cast9_loc_dout;
input   HwReg_height_cast9_loc_empty_n;
output   HwReg_height_cast9_loc_read;
input  [15:0] HwReg_width;
input  [1:0] tmp_4_loc_dout;
input   tmp_4_loc_empty_n;
output   tmp_4_loc_read;

reg ap_done;
reg ap_idle;
reg ap_ready;
reg HwReg_height_cast9_loc_read;
reg tmp_4_loc_read;

reg    ap_done_reg;
(* fsm_encoding = "none" *) reg   [6:0] ap_CS_fsm;
wire    ap_CS_fsm_state1;
reg   [23:0] AXI_video_strm_V_data_V_1_data_out;
reg    AXI_video_strm_V_data_V_1_vld_in;
wire    AXI_video_strm_V_data_V_1_vld_out;
wire    AXI_video_strm_V_data_V_1_ack_in;
wire    AXI_video_strm_V_data_V_1_ack_out;
reg   [23:0] AXI_video_strm_V_data_V_1_payload_A;
reg   [23:0] AXI_video_strm_V_data_V_1_payload_B;
reg    AXI_video_strm_V_data_V_1_sel_rd;
reg    AXI_video_strm_V_data_V_1_sel_wr;
wire    AXI_video_strm_V_data_V_1_sel;
wire    AXI_video_strm_V_data_V_1_load_A;
wire    AXI_video_strm_V_data_V_1_load_B;
reg   [1:0] AXI_video_strm_V_data_V_1_state;
wire    AXI_video_strm_V_data_V_1_state_cmp_full;
wire   [2:0] AXI_video_strm_V_keep_V_1_data_out;
reg    AXI_video_strm_V_keep_V_1_vld_in;
wire    AXI_video_strm_V_keep_V_1_vld_out;
wire    AXI_video_strm_V_keep_V_1_ack_in;
wire    AXI_video_strm_V_keep_V_1_ack_out;
reg    AXI_video_strm_V_keep_V_1_sel_rd;
wire    AXI_video_strm_V_keep_V_1_sel;
reg   [1:0] AXI_video_strm_V_keep_V_1_state;
wire   [2:0] AXI_video_strm_V_strb_V_1_data_out;
reg    AXI_video_strm_V_strb_V_1_vld_in;
wire    AXI_video_strm_V_strb_V_1_vld_out;
wire    AXI_video_strm_V_strb_V_1_ack_in;
wire    AXI_video_strm_V_strb_V_1_ack_out;
reg    AXI_video_strm_V_strb_V_1_sel_rd;
wire    AXI_video_strm_V_strb_V_1_sel;
reg   [1:0] AXI_video_strm_V_strb_V_1_state;
reg   [0:0] AXI_video_strm_V_user_V_1_data_out;
reg    AXI_video_strm_V_user_V_1_vld_in;
wire    AXI_video_strm_V_user_V_1_vld_out;
wire    AXI_video_strm_V_user_V_1_ack_in;
wire    AXI_video_strm_V_user_V_1_ack_out;
reg   [0:0] AXI_video_strm_V_user_V_1_payload_A;
reg   [0:0] AXI_video_strm_V_user_V_1_payload_B;
reg    AXI_video_strm_V_user_V_1_sel_rd;
reg    AXI_video_strm_V_user_V_1_sel_wr;
wire    AXI_video_strm_V_user_V_1_sel;
wire    AXI_video_strm_V_user_V_1_load_A;
wire    AXI_video_strm_V_user_V_1_load_B;
reg   [1:0] AXI_video_strm_V_user_V_1_state;
wire    AXI_video_strm_V_user_V_1_state_cmp_full;
reg   [0:0] AXI_video_strm_V_last_V_1_data_out;
reg    AXI_video_strm_V_last_V_1_vld_in;
wire    AXI_video_strm_V_last_V_1_vld_out;
wire    AXI_video_strm_V_last_V_1_ack_in;
wire    AXI_video_strm_V_last_V_1_ack_out;
reg   [0:0] AXI_video_strm_V_last_V_1_payload_A;
reg   [0:0] AXI_video_strm_V_last_V_1_payload_B;
reg    AXI_video_strm_V_last_V_1_sel_rd;
reg    AXI_video_strm_V_last_V_1_sel_wr;
wire    AXI_video_strm_V_last_V_1_sel;
wire    AXI_video_strm_V_last_V_1_load_A;
wire    AXI_video_strm_V_last_V_1_load_B;
reg   [1:0] AXI_video_strm_V_last_V_1_state;
wire    AXI_video_strm_V_last_V_1_state_cmp_full;
wire   [0:0] AXI_video_strm_V_id_V_1_data_out;
reg    AXI_video_strm_V_id_V_1_vld_in;
wire    AXI_video_strm_V_id_V_1_vld_out;
wire    AXI_video_strm_V_id_V_1_ack_in;
wire    AXI_video_strm_V_id_V_1_ack_out;
reg    AXI_video_strm_V_id_V_1_sel_rd;
wire    AXI_video_strm_V_id_V_1_sel;
reg   [1:0] AXI_video_strm_V_id_V_1_state;
wire   [0:0] AXI_video_strm_V_dest_V_1_data_out;
reg    AXI_video_strm_V_dest_V_1_vld_in;
wire    AXI_video_strm_V_dest_V_1_vld_out;
wire    AXI_video_strm_V_dest_V_1_ack_in;
wire    AXI_video_strm_V_dest_V_1_ack_out;
reg    AXI_video_strm_V_dest_V_1_sel_rd;
wire    AXI_video_strm_V_dest_V_1_sel;
reg   [1:0] AXI_video_strm_V_dest_V_1_state;
wire   [3:0] mapComp_address0;
reg    mapComp_ce0;
wire   [1:0] mapComp_q0;
reg    StrmMPix_V_val_0_V_blk_n;
wire    ap_CS_fsm_pp0_stage0;
reg    ap_enable_reg_pp0_iter1;
wire    ap_block_pp0_stage0_flag00000000;
reg   [0:0] exitcond3_i_i_reg_603;
reg    StrmMPix_V_val_1_V_blk_n;
reg    StrmMPix_V_val_2_V_blk_n;
reg    m_axis_video_TDATA_blk_n;
reg    ap_enable_reg_pp0_iter2;
reg   [0:0] ap_reg_pp0_iter1_exitcond3_i_i_reg_603;
reg    HwReg_height_cast9_loc_blk_n;
reg    tmp_4_loc_blk_n;
reg   [9:0] j_i_i_reg_244;
reg    ap_block_state1;
reg   [1:0] tmp_4_loc_read_reg_508;
wire   [9:0] Height_cast_i_i_fu_259_p1;
reg   [9:0] Height_cast_i_i_reg_514;
wire   [9:0] grp_reg_unsigned_short_s_fu_263_ap_return;
reg   [9:0] tmp_i_i_reg_519;
wire    ap_CS_fsm_state2;
wire    grp_reg_unsigned_short_s_fu_263_ap_done;
wire    grp_reg_unsigned_short_s_fu_269_ap_done;
reg    ap_block_state2_on_subcall_done;
wire   [9:0] grp_reg_unsigned_short_s_fu_269_ap_return;
reg   [9:0] tmp_i_i_61_reg_524;
wire   [10:0] cols_cast_i_i_fu_275_p1;
reg   [10:0] cols_cast_i_i_reg_529;
wire   [4:0] tmp_4_fu_293_p2;
reg   [4:0] tmp_4_reg_534;
wire    ap_CS_fsm_state3;
wire   [1:0] i_fu_319_p2;
reg   [1:0] i_reg_547;
wire   [10:0] tmp_7_i_i_fu_325_p2;
reg   [10:0] tmp_7_i_i_reg_559;
wire   [0:0] exitcond1_i_i_fu_313_p2;
wire   [1:0] tmp_7_fu_330_p1;
reg   [1:0] tmp_7_reg_564;
wire   [1:0] tmp_8_fu_334_p1;
reg   [1:0] tmp_8_reg_569;
wire   [1:0] tmp_9_fu_338_p1;
reg   [1:0] tmp_9_reg_574;
wire   [4:0] map_2_V_1_fu_371_p3;
wire    ap_CS_fsm_state4;
wire   [4:0] map_2_V_3_fu_387_p3;
wire   [4:0] map_2_V_5_fu_395_p3;
wire   [0:0] exitcond2_i_i_fu_407_p2;
wire    ap_CS_fsm_state5;
reg    ap_block_state5;
wire   [8:0] i_1_fu_412_p2;
reg   [8:0] i_1_reg_598;
wire   [0:0] exitcond3_i_i_fu_422_p2;
wire    ap_block_state6_pp0_stage0_iter0;
wire    StrmMPix_V_val_0_V0_status;
reg    ap_block_state7_pp0_stage0_iter1;
reg    ap_block_state7_io;
wire    ap_block_state8_pp0_stage0_iter2;
reg    ap_block_state8_io;
reg    ap_block_pp0_stage0_flag00011001;
wire   [9:0] j_fu_427_p2;
reg    ap_enable_reg_pp0_iter0;
wire   [0:0] axi_last_V_fu_433_p2;
reg   [0:0] axi_last_V_reg_612;
wire   [23:0] tmp_data_V_fu_487_p4;
reg    ap_block_pp0_stage0_flag00011011;
reg    ap_condition_pp0_exit_iter0_state6;
wire    grp_reg_unsigned_short_s_fu_263_ap_start;
wire    grp_reg_unsigned_short_s_fu_263_ap_idle;
wire    grp_reg_unsigned_short_s_fu_263_ap_ready;
wire    grp_reg_unsigned_short_s_fu_269_ap_start;
wire    grp_reg_unsigned_short_s_fu_269_ap_idle;
wire    grp_reg_unsigned_short_s_fu_269_ap_ready;
wire   [9:0] grp_reg_unsigned_short_s_fu_269_in_r;
reg   [4:0] map_V_2_i_i_reg_185;
reg   [4:0] map_V_1_i_i_reg_197;
reg   [4:0] map_2_V_4_reg_209;
reg   [1:0] i_i_i_reg_221;
reg   [8:0] i1_i_i_reg_233;
wire    ap_CS_fsm_state9;
reg    ap_reg_grp_reg_unsigned_short_s_fu_263_ap_start;
reg    ap_block_state1_ignore_call18;
reg    ap_reg_grp_reg_unsigned_short_s_fu_269_ap_start;
reg    ap_block_state1_ignore_call19;
wire  signed [31:0] tmp_5_cast_fu_308_p1;
reg    StrmMPix_V_val_0_V0_update;
reg   [0:0] tmp_user_V_fu_112;
reg    ap_block_pp0_stage0_flag00001001;
wire   [3:0] tmp_3_fu_282_p3;
wire   [4:0] p_shl_cast_fu_289_p1;
wire   [4:0] tmp_5_i_i_cast_fu_279_p1;
wire   [4:0] i_cast6_i_i_cast_fu_299_p1;
wire   [4:0] tmp_5_fu_303_p2;
wire   [0:0] sel_tmp_fu_351_p2;
wire   [4:0] map_0_V_cast_fu_347_p1;
wire   [0:0] sel_tmp2_fu_365_p2;
wire   [4:0] map_2_V_fu_357_p3;
wire   [4:0] map_2_V_2_fu_379_p3;
wire   [9:0] i1_cast_i_i_fu_403_p1;
wire   [10:0] j_cast_i_i_fu_418_p1;
wire   [7:0] tmp_2_fu_476_p5;
wire   [7:0] tmp_1_fu_465_p5;
wire   [7:0] tmp_fu_454_p5;
reg   [6:0] ap_NS_fsm;
reg    ap_idle_pp0;
wire    ap_enable_pp0;

// power-on initialization
initial begin
#0 ap_done_reg = 1'b0;
#0 ap_CS_fsm = 7'd1;
#0 AXI_video_strm_V_data_V_1_sel_rd = 1'b0;
#0 AXI_video_strm_V_data_V_1_sel_wr = 1'b0;
#0 AXI_video_strm_V_data_V_1_state = 2'd0;
#0 AXI_video_strm_V_keep_V_1_sel_rd = 1'b0;
#0 AXI_video_strm_V_keep_V_1_state = 2'd0;
#0 AXI_video_strm_V_strb_V_1_sel_rd = 1'b0;
#0 AXI_video_strm_V_strb_V_1_state = 2'd0;
#0 AXI_video_strm_V_user_V_1_sel_rd = 1'b0;
#0 AXI_video_strm_V_user_V_1_sel_wr = 1'b0;
#0 AXI_video_strm_V_user_V_1_state = 2'd0;
#0 AXI_video_strm_V_last_V_1_sel_rd = 1'b0;
#0 AXI_video_strm_V_last_V_1_sel_wr = 1'b0;
#0 AXI_video_strm_V_last_V_1_state = 2'd0;
#0 AXI_video_strm_V_id_V_1_sel_rd = 1'b0;
#0 AXI_video_strm_V_id_V_1_state = 2'd0;
#0 AXI_video_strm_V_dest_V_1_sel_rd = 1'b0;
#0 AXI_video_strm_V_dest_V_1_state = 2'd0;
#0 ap_enable_reg_pp0_iter1 = 1'b0;
#0 ap_enable_reg_pp0_iter2 = 1'b0;
#0 ap_enable_reg_pp0_iter0 = 1'b0;
#0 ap_reg_grp_reg_unsigned_short_s_fu_263_ap_start = 1'b0;
#0 ap_reg_grp_reg_unsigned_short_s_fu_269_ap_start = 1'b0;
end

design_1_v_frmbuf_rd_0_0_MultiPixStream2AXfYi #(
    .DataWidth( 2 ),
    .AddressRange( 12 ),
    .AddressWidth( 4 ))
mapComp_U(
    .clk(ap_clk),
    .reset(ap_rst),
    .address0(mapComp_address0),
    .ce0(mapComp_ce0),
    .q0(mapComp_q0)
);

design_1_v_frmbuf_rd_0_0_reg_unsigned_short_s grp_reg_unsigned_short_s_fu_263(
    .ap_clk(ap_clk),
    .ap_rst(ap_rst),
    .ap_start(grp_reg_unsigned_short_s_fu_263_ap_start),
    .ap_done(grp_reg_unsigned_short_s_fu_263_ap_done),
    .ap_idle(grp_reg_unsigned_short_s_fu_263_ap_idle),
    .ap_ready(grp_reg_unsigned_short_s_fu_263_ap_ready),
    .in_r(Height_cast_i_i_reg_514),
    .ap_return(grp_reg_unsigned_short_s_fu_263_ap_return)
);

design_1_v_frmbuf_rd_0_0_reg_unsigned_short_s grp_reg_unsigned_short_s_fu_269(
    .ap_clk(ap_clk),
    .ap_rst(ap_rst),
    .ap_start(grp_reg_unsigned_short_s_fu_269_ap_start),
    .ap_done(grp_reg_unsigned_short_s_fu_269_ap_done),
    .ap_idle(grp_reg_unsigned_short_s_fu_269_ap_idle),
    .ap_ready(grp_reg_unsigned_short_s_fu_269_ap_ready),
    .in_r(grp_reg_unsigned_short_s_fu_269_in_r),
    .ap_return(grp_reg_unsigned_short_s_fu_269_ap_return)
);

design_1_v_frmbuf_rd_0_0_v_frmbuf_rd_mux_3g8j #(
    .ID( 1 ),
    .NUM_STAGE( 1 ),
    .din1_WIDTH( 8 ),
    .din2_WIDTH( 8 ),
    .din3_WIDTH( 8 ),
    .din4_WIDTH( 2 ),
    .dout_WIDTH( 8 ))
v_frmbuf_rd_mux_3g8j_U31(
    .din1(StrmMPix_V_val_0_V_dout),
    .din2(StrmMPix_V_val_1_V_dout),
    .din3(StrmMPix_V_val_2_V_dout),
    .din4(tmp_7_reg_564),
    .dout(tmp_fu_454_p5)
);

design_1_v_frmbuf_rd_0_0_v_frmbuf_rd_mux_3g8j #(
    .ID( 1 ),
    .NUM_STAGE( 1 ),
    .din1_WIDTH( 8 ),
    .din2_WIDTH( 8 ),
    .din3_WIDTH( 8 ),
    .din4_WIDTH( 2 ),
    .dout_WIDTH( 8 ))
v_frmbuf_rd_mux_3g8j_U32(
    .din1(StrmMPix_V_val_0_V_dout),
    .din2(StrmMPix_V_val_1_V_dout),
    .din3(StrmMPix_V_val_2_V_dout),
    .din4(tmp_8_reg_569),
    .dout(tmp_1_fu_465_p5)
);

design_1_v_frmbuf_rd_0_0_v_frmbuf_rd_mux_3g8j #(
    .ID( 1 ),
    .NUM_STAGE( 1 ),
    .din1_WIDTH( 8 ),
    .din2_WIDTH( 8 ),
    .din3_WIDTH( 8 ),
    .din4_WIDTH( 2 ),
    .dout_WIDTH( 8 ))
v_frmbuf_rd_mux_3g8j_U33(
    .din1(StrmMPix_V_val_0_V_dout),
    .din2(StrmMPix_V_val_1_V_dout),
    .din3(StrmMPix_V_val_2_V_dout),
    .din4(tmp_9_reg_574),
    .dout(tmp_2_fu_476_p5)
);

always @ (posedge ap_clk) begin
    if (ap_rst == 1'b1) begin
        AXI_video_strm_V_data_V_1_sel_rd <= 1'b0;
    end else begin
        if (((1'b1 == AXI_video_strm_V_data_V_1_ack_out) & (1'b1 == AXI_video_strm_V_data_V_1_vld_out))) begin
            AXI_video_strm_V_data_V_1_sel_rd <= ~AXI_video_strm_V_data_V_1_sel_rd;
        end
    end
end

always @ (posedge ap_clk) begin
    if (ap_rst == 1'b1) begin
        AXI_video_strm_V_data_V_1_sel_wr <= 1'b0;
    end else begin
        if (((1'b1 == AXI_video_strm_V_data_V_1_vld_in) & (1'b1 == AXI_video_strm_V_data_V_1_ack_in))) begin
            AXI_video_strm_V_data_V_1_sel_wr <= ~AXI_video_strm_V_data_V_1_sel_wr;
        end
    end
end

always @ (posedge ap_clk) begin
    if (ap_rst == 1'b1) begin
        AXI_video_strm_V_data_V_1_state <= 2'd0;
    end else begin
        if ((((1'b0 == AXI_video_strm_V_data_V_1_vld_in) & (1'b1 == AXI_video_strm_V_data_V_1_ack_out) & (AXI_video_strm_V_data_V_1_state == 2'd3)) | ((1'b0 == AXI_video_strm_V_data_V_1_vld_in) & (AXI_video_strm_V_data_V_1_state == 2'd2)))) begin
            AXI_video_strm_V_data_V_1_state <= 2'd2;
        end else if ((((1'b1 == AXI_video_strm_V_data_V_1_vld_in) & (1'b0 == AXI_video_strm_V_data_V_1_ack_out) & (AXI_video_strm_V_data_V_1_state == 2'd3)) | ((1'b0 == AXI_video_strm_V_data_V_1_ack_out) & (AXI_video_strm_V_data_V_1_state == 2'd1)))) begin
            AXI_video_strm_V_data_V_1_state <= 2'd1;
        end else if ((((1'b1 == AXI_video_strm_V_data_V_1_vld_in) & (AXI_video_strm_V_data_V_1_state == 2'd2)) | ((1'b1 == AXI_video_strm_V_data_V_1_ack_out) & (AXI_video_strm_V_data_V_1_state == 2'd1)) | ((AXI_video_strm_V_data_V_1_state == 2'd3) & ~((1'b1 == AXI_video_strm_V_data_V_1_vld_in) & (1'b0 == AXI_video_strm_V_data_V_1_ack_out)) & ~((1'b0 == AXI_video_strm_V_data_V_1_vld_in) & (1'b1 == AXI_video_strm_V_data_V_1_ack_out))))) begin
            AXI_video_strm_V_data_V_1_state <= 2'd3;
        end else begin
            AXI_video_strm_V_data_V_1_state <= 2'd2;
        end
    end
end

always @ (posedge ap_clk) begin
    if (ap_rst == 1'b1) begin
        AXI_video_strm_V_dest_V_1_sel_rd <= 1'b0;
    end else begin
        if (((1'b1 == AXI_video_strm_V_dest_V_1_ack_out) & (1'b1 == AXI_video_strm_V_dest_V_1_vld_out))) begin
            AXI_video_strm_V_dest_V_1_sel_rd <= ~AXI_video_strm_V_dest_V_1_sel_rd;
        end
    end
end

always @ (posedge ap_clk) begin
    if (ap_rst == 1'b1) begin
        AXI_video_strm_V_dest_V_1_state <= 2'd0;
    end else begin
        if ((((1'b0 == AXI_video_strm_V_dest_V_1_vld_in) & (1'b1 == AXI_video_strm_V_dest_V_1_ack_out) & (2'd3 == AXI_video_strm_V_dest_V_1_state)) | ((1'b0 == AXI_video_strm_V_dest_V_1_vld_in) & (2'd2 == AXI_video_strm_V_dest_V_1_state)))) begin
            AXI_video_strm_V_dest_V_1_state <= 2'd2;
        end else if ((((1'b1 == AXI_video_strm_V_dest_V_1_vld_in) & (1'b0 == AXI_video_strm_V_dest_V_1_ack_out) & (2'd3 == AXI_video_strm_V_dest_V_1_state)) | ((1'b0 == AXI_video_strm_V_dest_V_1_ack_out) & (2'd1 == AXI_video_strm_V_dest_V_1_state)))) begin
            AXI_video_strm_V_dest_V_1_state <= 2'd1;
        end else if ((((1'b1 == AXI_video_strm_V_dest_V_1_vld_in) & (2'd2 == AXI_video_strm_V_dest_V_1_state)) | ((1'b1 == AXI_video_strm_V_dest_V_1_ack_out) & (2'd1 == AXI_video_strm_V_dest_V_1_state)) | ((2'd3 == AXI_video_strm_V_dest_V_1_state) & ~((1'b1 == AXI_video_strm_V_dest_V_1_vld_in) & (1'b0 == AXI_video_strm_V_dest_V_1_ack_out)) & ~((1'b0 == AXI_video_strm_V_dest_V_1_vld_in) & (1'b1 == AXI_video_strm_V_dest_V_1_ack_out))))) begin
            AXI_video_strm_V_dest_V_1_state <= 2'd3;
        end else begin
            AXI_video_strm_V_dest_V_1_state <= 2'd2;
        end
    end
end

always @ (posedge ap_clk) begin
    if (ap_rst == 1'b1) begin
        AXI_video_strm_V_id_V_1_sel_rd <= 1'b0;
    end else begin
        if (((1'b1 == AXI_video_strm_V_id_V_1_ack_out) & (1'b1 == AXI_video_strm_V_id_V_1_vld_out))) begin
            AXI_video_strm_V_id_V_1_sel_rd <= ~AXI_video_strm_V_id_V_1_sel_rd;
        end
    end
end

always @ (posedge ap_clk) begin
    if (ap_rst == 1'b1) begin
        AXI_video_strm_V_id_V_1_state <= 2'd0;
    end else begin
        if ((((1'b0 == AXI_video_strm_V_id_V_1_vld_in) & (1'b1 == AXI_video_strm_V_id_V_1_ack_out) & (2'd3 == AXI_video_strm_V_id_V_1_state)) | ((1'b0 == AXI_video_strm_V_id_V_1_vld_in) & (2'd2 == AXI_video_strm_V_id_V_1_state)))) begin
            AXI_video_strm_V_id_V_1_state <= 2'd2;
        end else if ((((1'b1 == AXI_video_strm_V_id_V_1_vld_in) & (1'b0 == AXI_video_strm_V_id_V_1_ack_out) & (2'd3 == AXI_video_strm_V_id_V_1_state)) | ((1'b0 == AXI_video_strm_V_id_V_1_ack_out) & (2'd1 == AXI_video_strm_V_id_V_1_state)))) begin
            AXI_video_strm_V_id_V_1_state <= 2'd1;
        end else if ((((1'b1 == AXI_video_strm_V_id_V_1_vld_in) & (2'd2 == AXI_video_strm_V_id_V_1_state)) | ((1'b1 == AXI_video_strm_V_id_V_1_ack_out) & (2'd1 == AXI_video_strm_V_id_V_1_state)) | ((2'd3 == AXI_video_strm_V_id_V_1_state) & ~((1'b1 == AXI_video_strm_V_id_V_1_vld_in) & (1'b0 == AXI_video_strm_V_id_V_1_ack_out)) & ~((1'b0 == AXI_video_strm_V_id_V_1_vld_in) & (1'b1 == AXI_video_strm_V_id_V_1_ack_out))))) begin
            AXI_video_strm_V_id_V_1_state <= 2'd3;
        end else begin
            AXI_video_strm_V_id_V_1_state <= 2'd2;
        end
    end
end

always @ (posedge ap_clk) begin
    if (ap_rst == 1'b1) begin
        AXI_video_strm_V_keep_V_1_sel_rd <= 1'b0;
    end else begin
        if (((1'b1 == AXI_video_strm_V_keep_V_1_ack_out) & (1'b1 == AXI_video_strm_V_keep_V_1_vld_out))) begin
            AXI_video_strm_V_keep_V_1_sel_rd <= ~AXI_video_strm_V_keep_V_1_sel_rd;
        end
    end
end

always @ (posedge ap_clk) begin
    if (ap_rst == 1'b1) begin
        AXI_video_strm_V_keep_V_1_state <= 2'd0;
    end else begin
        if ((((1'b0 == AXI_video_strm_V_keep_V_1_vld_in) & (1'b1 == AXI_video_strm_V_keep_V_1_ack_out) & (2'd3 == AXI_video_strm_V_keep_V_1_state)) | ((1'b0 == AXI_video_strm_V_keep_V_1_vld_in) & (2'd2 == AXI_video_strm_V_keep_V_1_state)))) begin
            AXI_video_strm_V_keep_V_1_state <= 2'd2;
        end else if ((((1'b1 == AXI_video_strm_V_keep_V_1_vld_in) & (1'b0 == AXI_video_strm_V_keep_V_1_ack_out) & (2'd3 == AXI_video_strm_V_keep_V_1_state)) | ((1'b0 == AXI_video_strm_V_keep_V_1_ack_out) & (2'd1 == AXI_video_strm_V_keep_V_1_state)))) begin
            AXI_video_strm_V_keep_V_1_state <= 2'd1;
        end else if ((((1'b1 == AXI_video_strm_V_keep_V_1_vld_in) & (2'd2 == AXI_video_strm_V_keep_V_1_state)) | ((1'b1 == AXI_video_strm_V_keep_V_1_ack_out) & (2'd1 == AXI_video_strm_V_keep_V_1_state)) | ((2'd3 == AXI_video_strm_V_keep_V_1_state) & ~((1'b1 == AXI_video_strm_V_keep_V_1_vld_in) & (1'b0 == AXI_video_strm_V_keep_V_1_ack_out)) & ~((1'b0 == AXI_video_strm_V_keep_V_1_vld_in) & (1'b1 == AXI_video_strm_V_keep_V_1_ack_out))))) begin
            AXI_video_strm_V_keep_V_1_state <= 2'd3;
        end else begin
            AXI_video_strm_V_keep_V_1_state <= 2'd2;
        end
    end
end

always @ (posedge ap_clk) begin
    if (ap_rst == 1'b1) begin
        AXI_video_strm_V_last_V_1_sel_rd <= 1'b0;
    end else begin
        if (((1'b1 == AXI_video_strm_V_last_V_1_ack_out) & (1'b1 == AXI_video_strm_V_last_V_1_vld_out))) begin
            AXI_video_strm_V_last_V_1_sel_rd <= ~AXI_video_strm_V_last_V_1_sel_rd;
        end
    end
end

always @ (posedge ap_clk) begin
    if (ap_rst == 1'b1) begin
        AXI_video_strm_V_last_V_1_sel_wr <= 1'b0;
    end else begin
        if (((1'b1 == AXI_video_strm_V_last_V_1_vld_in) & (1'b1 == AXI_video_strm_V_last_V_1_ack_in))) begin
            AXI_video_strm_V_last_V_1_sel_wr <= ~AXI_video_strm_V_last_V_1_sel_wr;
        end
    end
end

always @ (posedge ap_clk) begin
    if (ap_rst == 1'b1) begin
        AXI_video_strm_V_last_V_1_state <= 2'd0;
    end else begin
        if ((((1'b0 == AXI_video_strm_V_last_V_1_vld_in) & (1'b1 == AXI_video_strm_V_last_V_1_ack_out) & (2'd3 == AXI_video_strm_V_last_V_1_state)) | ((1'b0 == AXI_video_strm_V_last_V_1_vld_in) & (2'd2 == AXI_video_strm_V_last_V_1_state)))) begin
            AXI_video_strm_V_last_V_1_state <= 2'd2;
        end else if ((((1'b1 == AXI_video_strm_V_last_V_1_vld_in) & (1'b0 == AXI_video_strm_V_last_V_1_ack_out) & (2'd3 == AXI_video_strm_V_last_V_1_state)) | ((1'b0 == AXI_video_strm_V_last_V_1_ack_out) & (2'd1 == AXI_video_strm_V_last_V_1_state)))) begin
            AXI_video_strm_V_last_V_1_state <= 2'd1;
        end else if ((((1'b1 == AXI_video_strm_V_last_V_1_vld_in) & (2'd2 == AXI_video_strm_V_last_V_1_state)) | ((1'b1 == AXI_video_strm_V_last_V_1_ack_out) & (2'd1 == AXI_video_strm_V_last_V_1_state)) | ((2'd3 == AXI_video_strm_V_last_V_1_state) & ~((1'b1 == AXI_video_strm_V_last_V_1_vld_in) & (1'b0 == AXI_video_strm_V_last_V_1_ack_out)) & ~((1'b0 == AXI_video_strm_V_last_V_1_vld_in) & (1'b1 == AXI_video_strm_V_last_V_1_ack_out))))) begin
            AXI_video_strm_V_last_V_1_state <= 2'd3;
        end else begin
            AXI_video_strm_V_last_V_1_state <= 2'd2;
        end
    end
end

always @ (posedge ap_clk) begin
    if (ap_rst == 1'b1) begin
        AXI_video_strm_V_strb_V_1_sel_rd <= 1'b0;
    end else begin
        if (((1'b1 == AXI_video_strm_V_strb_V_1_ack_out) & (1'b1 == AXI_video_strm_V_strb_V_1_vld_out))) begin
            AXI_video_strm_V_strb_V_1_sel_rd <= ~AXI_video_strm_V_strb_V_1_sel_rd;
        end
    end
end

always @ (posedge ap_clk) begin
    if (ap_rst == 1'b1) begin
        AXI_video_strm_V_strb_V_1_state <= 2'd0;
    end else begin
        if ((((1'b0 == AXI_video_strm_V_strb_V_1_vld_in) & (1'b1 == AXI_video_strm_V_strb_V_1_ack_out) & (2'd3 == AXI_video_strm_V_strb_V_1_state)) | ((1'b0 == AXI_video_strm_V_strb_V_1_vld_in) & (2'd2 == AXI_video_strm_V_strb_V_1_state)))) begin
            AXI_video_strm_V_strb_V_1_state <= 2'd2;
        end else if ((((1'b1 == AXI_video_strm_V_strb_V_1_vld_in) & (1'b0 == AXI_video_strm_V_strb_V_1_ack_out) & (2'd3 == AXI_video_strm_V_strb_V_1_state)) | ((1'b0 == AXI_video_strm_V_strb_V_1_ack_out) & (2'd1 == AXI_video_strm_V_strb_V_1_state)))) begin
            AXI_video_strm_V_strb_V_1_state <= 2'd1;
        end else if ((((1'b1 == AXI_video_strm_V_strb_V_1_vld_in) & (2'd2 == AXI_video_strm_V_strb_V_1_state)) | ((1'b1 == AXI_video_strm_V_strb_V_1_ack_out) & (2'd1 == AXI_video_strm_V_strb_V_1_state)) | ((2'd3 == AXI_video_strm_V_strb_V_1_state) & ~((1'b1 == AXI_video_strm_V_strb_V_1_vld_in) & (1'b0 == AXI_video_strm_V_strb_V_1_ack_out)) & ~((1'b0 == AXI_video_strm_V_strb_V_1_vld_in) & (1'b1 == AXI_video_strm_V_strb_V_1_ack_out))))) begin
            AXI_video_strm_V_strb_V_1_state <= 2'd3;
        end else begin
            AXI_video_strm_V_strb_V_1_state <= 2'd2;
        end
    end
end

always @ (posedge ap_clk) begin
    if (ap_rst == 1'b1) begin
        AXI_video_strm_V_user_V_1_sel_rd <= 1'b0;
    end else begin
        if (((1'b1 == AXI_video_strm_V_user_V_1_ack_out) & (1'b1 == AXI_video_strm_V_user_V_1_vld_out))) begin
            AXI_video_strm_V_user_V_1_sel_rd <= ~AXI_video_strm_V_user_V_1_sel_rd;
        end
    end
end

always @ (posedge ap_clk) begin
    if (ap_rst == 1'b1) begin
        AXI_video_strm_V_user_V_1_sel_wr <= 1'b0;
    end else begin
        if (((1'b1 == AXI_video_strm_V_user_V_1_vld_in) & (1'b1 == AXI_video_strm_V_user_V_1_ack_in))) begin
            AXI_video_strm_V_user_V_1_sel_wr <= ~AXI_video_strm_V_user_V_1_sel_wr;
        end
    end
end

always @ (posedge ap_clk) begin
    if (ap_rst == 1'b1) begin
        AXI_video_strm_V_user_V_1_state <= 2'd0;
    end else begin
        if ((((1'b0 == AXI_video_strm_V_user_V_1_vld_in) & (1'b1 == AXI_video_strm_V_user_V_1_ack_out) & (2'd3 == AXI_video_strm_V_user_V_1_state)) | ((1'b0 == AXI_video_strm_V_user_V_1_vld_in) & (2'd2 == AXI_video_strm_V_user_V_1_state)))) begin
            AXI_video_strm_V_user_V_1_state <= 2'd2;
        end else if ((((1'b1 == AXI_video_strm_V_user_V_1_vld_in) & (1'b0 == AXI_video_strm_V_user_V_1_ack_out) & (2'd3 == AXI_video_strm_V_user_V_1_state)) | ((1'b0 == AXI_video_strm_V_user_V_1_ack_out) & (2'd1 == AXI_video_strm_V_user_V_1_state)))) begin
            AXI_video_strm_V_user_V_1_state <= 2'd1;
        end else if ((((1'b1 == AXI_video_strm_V_user_V_1_vld_in) & (2'd2 == AXI_video_strm_V_user_V_1_state)) | ((1'b1 == AXI_video_strm_V_user_V_1_ack_out) & (2'd1 == AXI_video_strm_V_user_V_1_state)) | ((2'd3 == AXI_video_strm_V_user_V_1_state) & ~((1'b1 == AXI_video_strm_V_user_V_1_vld_in) & (1'b0 == AXI_video_strm_V_user_V_1_ack_out)) & ~((1'b0 == AXI_video_strm_V_user_V_1_vld_in) & (1'b1 == AXI_video_strm_V_user_V_1_ack_out))))) begin
            AXI_video_strm_V_user_V_1_state <= 2'd3;
        end else begin
            AXI_video_strm_V_user_V_1_state <= 2'd2;
        end
    end
end

always @ (posedge ap_clk) begin
    if (ap_rst == 1'b1) begin
        ap_CS_fsm <= ap_ST_fsm_state1;
    end else begin
        ap_CS_fsm <= ap_NS_fsm;
    end
end

always @ (posedge ap_clk) begin
    if (ap_rst == 1'b1) begin
        ap_done_reg <= 1'b0;
    end else begin
        if ((1'b1 == ap_continue)) begin
            ap_done_reg <= 1'b0;
        end else if (((1'b1 == ap_CS_fsm_state5) & ~((1'b0 == AXI_video_strm_V_data_V_1_ack_in) | (1'b0 == AXI_video_strm_V_keep_V_1_ack_in) | (1'b0 == AXI_video_strm_V_strb_V_1_ack_in) | (1'b0 == AXI_video_strm_V_user_V_1_ack_in) | (1'b0 == AXI_video_strm_V_last_V_1_ack_in) | (1'b0 == AXI_video_strm_V_id_V_1_ack_in) | (1'b0 == AXI_video_strm_V_dest_V_1_ack_in)) & (1'd1 == exitcond2_i_i_fu_407_p2))) begin
            ap_done_reg <= 1'b1;
        end
    end
end

always @ (posedge ap_clk) begin
    if (ap_rst == 1'b1) begin
        ap_enable_reg_pp0_iter0 <= 1'b0;
    end else begin
        if (((1'b1 == ap_CS_fsm_pp0_stage0) & (ap_block_pp0_stage0_flag00011011 == 1'b0) & (1'b1 == ap_condition_pp0_exit_iter0_state6))) begin
            ap_enable_reg_pp0_iter0 <= 1'b0;
        end else if (((1'b1 == ap_CS_fsm_state5) & ~((1'b0 == AXI_video_strm_V_data_V_1_ack_in) | (1'b0 == AXI_video_strm_V_keep_V_1_ack_in) | (1'b0 == AXI_video_strm_V_strb_V_1_ack_in) | (1'b0 == AXI_video_strm_V_user_V_1_ack_in) | (1'b0 == AXI_video_strm_V_last_V_1_ack_in) | (1'b0 == AXI_video_strm_V_id_V_1_ack_in) | (1'b0 == AXI_video_strm_V_dest_V_1_ack_in)) & (1'd0 == exitcond2_i_i_fu_407_p2))) begin
            ap_enable_reg_pp0_iter0 <= 1'b1;
        end
    end
end

always @ (posedge ap_clk) begin
    if (ap_rst == 1'b1) begin
        ap_enable_reg_pp0_iter1 <= 1'b0;
    end else begin
        if ((ap_block_pp0_stage0_flag00011011 == 1'b0)) begin
            if ((1'b1 == ap_condition_pp0_exit_iter0_state6)) begin
                ap_enable_reg_pp0_iter1 <= (ap_condition_pp0_exit_iter0_state6 ^ 1'b1);
            end else if ((1'b1 == 1'b1)) begin
                ap_enable_reg_pp0_iter1 <= ap_enable_reg_pp0_iter0;
            end
        end
    end
end

always @ (posedge ap_clk) begin
    if (ap_rst == 1'b1) begin
        ap_enable_reg_pp0_iter2 <= 1'b0;
    end else begin
        if ((ap_block_pp0_stage0_flag00011011 == 1'b0)) begin
            ap_enable_reg_pp0_iter2 <= ap_enable_reg_pp0_iter1;
        end else if (((1'b1 == ap_CS_fsm_state5) & ~((1'b0 == AXI_video_strm_V_data_V_1_ack_in) | (1'b0 == AXI_video_strm_V_keep_V_1_ack_in) | (1'b0 == AXI_video_strm_V_strb_V_1_ack_in) | (1'b0 == AXI_video_strm_V_user_V_1_ack_in) | (1'b0 == AXI_video_strm_V_last_V_1_ack_in) | (1'b0 == AXI_video_strm_V_id_V_1_ack_in) | (1'b0 == AXI_video_strm_V_dest_V_1_ack_in)) & (1'd0 == exitcond2_i_i_fu_407_p2))) begin
            ap_enable_reg_pp0_iter2 <= 1'b0;
        end
    end
end

always @ (posedge ap_clk) begin
    if (ap_rst == 1'b1) begin
        ap_reg_grp_reg_unsigned_short_s_fu_263_ap_start <= 1'b0;
    end else begin
        if (((1'b1 == ap_CS_fsm_state1) & ~((1'b0 == ap_start) | (ap_done_reg == 1'b1) | (1'b0 == HwReg_height_cast9_loc_empty_n) | (1'b0 == tmp_4_loc_empty_n)))) begin
            ap_reg_grp_reg_unsigned_short_s_fu_263_ap_start <= 1'b1;
        end else if ((1'b1 == grp_reg_unsigned_short_s_fu_263_ap_ready)) begin
            ap_reg_grp_reg_unsigned_short_s_fu_263_ap_start <= 1'b0;
        end
    end
end

always @ (posedge ap_clk) begin
    if (ap_rst == 1'b1) begin
        ap_reg_grp_reg_unsigned_short_s_fu_269_ap_start <= 1'b0;
    end else begin
        if (((1'b1 == ap_CS_fsm_state1) & ~((1'b0 == ap_start) | (ap_done_reg == 1'b1) | (1'b0 == HwReg_height_cast9_loc_empty_n) | (1'b0 == tmp_4_loc_empty_n)))) begin
            ap_reg_grp_reg_unsigned_short_s_fu_269_ap_start <= 1'b1;
        end else if ((1'b1 == grp_reg_unsigned_short_s_fu_269_ap_ready)) begin
            ap_reg_grp_reg_unsigned_short_s_fu_269_ap_start <= 1'b0;
        end
    end
end

always @ (posedge ap_clk) begin
    if ((1'b1 == ap_CS_fsm_state9)) begin
        i1_i_i_reg_233 <= i_1_reg_598;
    end else if (((1'b1 == ap_CS_fsm_state3) & (1'd1 == exitcond1_i_i_fu_313_p2))) begin
        i1_i_i_reg_233 <= 9'd0;
    end
end

always @ (posedge ap_clk) begin
    if ((1'b1 == ap_CS_fsm_state4)) begin
        i_i_i_reg_221 <= i_reg_547;
    end else if (((1'b1 == ap_CS_fsm_state2) & (ap_block_state2_on_subcall_done == 1'b0))) begin
        i_i_i_reg_221 <= 2'd0;
    end
end

always @ (posedge ap_clk) begin
    if (((1'b1 == ap_CS_fsm_state5) & ~((1'b0 == AXI_video_strm_V_data_V_1_ack_in) | (1'b0 == AXI_video_strm_V_keep_V_1_ack_in) | (1'b0 == AXI_video_strm_V_strb_V_1_ack_in) | (1'b0 == AXI_video_strm_V_user_V_1_ack_in) | (1'b0 == AXI_video_strm_V_last_V_1_ack_in) | (1'b0 == AXI_video_strm_V_id_V_1_ack_in) | (1'b0 == AXI_video_strm_V_dest_V_1_ack_in)) & (1'd0 == exitcond2_i_i_fu_407_p2))) begin
        j_i_i_reg_244 <= 10'd0;
    end else if (((1'b1 == ap_CS_fsm_pp0_stage0) & (ap_block_pp0_stage0_flag00011001 == 1'b0) & (1'b1 == ap_enable_reg_pp0_iter0) & (1'd0 == exitcond3_i_i_fu_422_p2))) begin
        j_i_i_reg_244 <= j_fu_427_p2;
    end
end

always @ (posedge ap_clk) begin
    if (((1'b1 == ap_CS_fsm_pp0_stage0) & (1'b1 == ap_enable_reg_pp0_iter1) & (1'd0 == exitcond3_i_i_reg_603) & (ap_block_pp0_stage0_flag00011001 == 1'b0))) begin
        tmp_user_V_fu_112 <= 1'd0;
    end else if (((1'b1 == ap_CS_fsm_state3) & (1'd1 == exitcond1_i_i_fu_313_p2))) begin
        tmp_user_V_fu_112 <= 1'd1;
    end
end

always @ (posedge ap_clk) begin
    if ((1'b1 == AXI_video_strm_V_data_V_1_load_A)) begin
        AXI_video_strm_V_data_V_1_payload_A <= tmp_data_V_fu_487_p4;
    end
end

always @ (posedge ap_clk) begin
    if ((1'b1 == AXI_video_strm_V_data_V_1_load_B)) begin
        AXI_video_strm_V_data_V_1_payload_B <= tmp_data_V_fu_487_p4;
    end
end

always @ (posedge ap_clk) begin
    if ((1'b1 == AXI_video_strm_V_last_V_1_load_A)) begin
        AXI_video_strm_V_last_V_1_payload_A <= axi_last_V_reg_612;
    end
end

always @ (posedge ap_clk) begin
    if ((1'b1 == AXI_video_strm_V_last_V_1_load_B)) begin
        AXI_video_strm_V_last_V_1_payload_B <= axi_last_V_reg_612;
    end
end

always @ (posedge ap_clk) begin
    if ((1'b1 == AXI_video_strm_V_user_V_1_load_A)) begin
        AXI_video_strm_V_user_V_1_payload_A <= tmp_user_V_fu_112;
    end
end

always @ (posedge ap_clk) begin
    if ((1'b1 == AXI_video_strm_V_user_V_1_load_B)) begin
        AXI_video_strm_V_user_V_1_payload_B <= tmp_user_V_fu_112;
    end
end

always @ (posedge ap_clk) begin
    if (((1'b1 == ap_CS_fsm_state1) & ~((1'b0 == ap_start) | (ap_done_reg == 1'b1) | (1'b0 == HwReg_height_cast9_loc_empty_n) | (1'b0 == tmp_4_loc_empty_n)))) begin
        Height_cast_i_i_reg_514[8 : 0] <= Height_cast_i_i_fu_259_p1[8 : 0];
        tmp_4_loc_read_reg_508 <= tmp_4_loc_dout;
    end
end

always @ (posedge ap_clk) begin
    if (((1'b1 == ap_CS_fsm_pp0_stage0) & (ap_block_pp0_stage0_flag00011001 == 1'b0))) begin
        ap_reg_pp0_iter1_exitcond3_i_i_reg_603 <= exitcond3_i_i_reg_603;
        exitcond3_i_i_reg_603 <= exitcond3_i_i_fu_422_p2;
    end
end

always @ (posedge ap_clk) begin
    if (((1'b1 == ap_CS_fsm_pp0_stage0) & (ap_block_pp0_stage0_flag00011001 == 1'b0) & (1'd0 == exitcond3_i_i_fu_422_p2))) begin
        axi_last_V_reg_612 <= axi_last_V_fu_433_p2;
    end
end

always @ (posedge ap_clk) begin
    if (((1'b1 == ap_CS_fsm_state2) & (ap_block_state2_on_subcall_done == 1'b0))) begin
        cols_cast_i_i_reg_529[9 : 0] <= cols_cast_i_i_fu_275_p1[9 : 0];
        tmp_4_reg_534 <= tmp_4_fu_293_p2;
        tmp_i_i_61_reg_524 <= grp_reg_unsigned_short_s_fu_269_ap_return;
        tmp_i_i_reg_519 <= grp_reg_unsigned_short_s_fu_263_ap_return;
    end
end

always @ (posedge ap_clk) begin
    if (((1'b1 == ap_CS_fsm_state5) & ~((1'b0 == AXI_video_strm_V_data_V_1_ack_in) | (1'b0 == AXI_video_strm_V_keep_V_1_ack_in) | (1'b0 == AXI_video_strm_V_strb_V_1_ack_in) | (1'b0 == AXI_video_strm_V_user_V_1_ack_in) | (1'b0 == AXI_video_strm_V_last_V_1_ack_in) | (1'b0 == AXI_video_strm_V_id_V_1_ack_in) | (1'b0 == AXI_video_strm_V_dest_V_1_ack_in)))) begin
        i_1_reg_598 <= i_1_fu_412_p2;
    end
end

always @ (posedge ap_clk) begin
    if ((1'b1 == ap_CS_fsm_state3)) begin
        i_reg_547 <= i_fu_319_p2;
    end
end

always @ (posedge ap_clk) begin
    if ((1'b1 == ap_CS_fsm_state4)) begin
        map_2_V_4_reg_209 <= map_2_V_5_fu_395_p3;
        map_V_1_i_i_reg_197 <= map_2_V_3_fu_387_p3;
        map_V_2_i_i_reg_185 <= map_2_V_1_fu_371_p3;
    end
end

always @ (posedge ap_clk) begin
    if (((1'b1 == ap_CS_fsm_state3) & (1'd1 == exitcond1_i_i_fu_313_p2))) begin
        tmp_7_i_i_reg_559 <= tmp_7_i_i_fu_325_p2;
        tmp_7_reg_564 <= tmp_7_fu_330_p1;
        tmp_8_reg_569 <= tmp_8_fu_334_p1;
        tmp_9_reg_574 <= tmp_9_fu_338_p1;
    end
end

always @ (*) begin
    if ((1'b1 == AXI_video_strm_V_data_V_1_sel)) begin
        AXI_video_strm_V_data_V_1_data_out = AXI_video_strm_V_data_V_1_payload_B;
    end else begin
        AXI_video_strm_V_data_V_1_data_out = AXI_video_strm_V_data_V_1_payload_A;
    end
end

always @ (*) begin
    if (((1'b1 == ap_CS_fsm_pp0_stage0) & (1'b1 == ap_enable_reg_pp0_iter1) & (1'd0 == exitcond3_i_i_reg_603) & (ap_block_pp0_stage0_flag00011001 == 1'b0))) begin
        AXI_video_strm_V_data_V_1_vld_in = 1'b1;
    end else begin
        AXI_video_strm_V_data_V_1_vld_in = 1'b0;
    end
end

always @ (*) begin
    if (((1'b1 == ap_CS_fsm_pp0_stage0) & (1'b1 == ap_enable_reg_pp0_iter1) & (1'd0 == exitcond3_i_i_reg_603) & (ap_block_pp0_stage0_flag00011001 == 1'b0))) begin
        AXI_video_strm_V_dest_V_1_vld_in = 1'b1;
    end else begin
        AXI_video_strm_V_dest_V_1_vld_in = 1'b0;
    end
end

always @ (*) begin
    if (((1'b1 == ap_CS_fsm_pp0_stage0) & (1'b1 == ap_enable_reg_pp0_iter1) & (1'd0 == exitcond3_i_i_reg_603) & (ap_block_pp0_stage0_flag00011001 == 1'b0))) begin
        AXI_video_strm_V_id_V_1_vld_in = 1'b1;
    end else begin
        AXI_video_strm_V_id_V_1_vld_in = 1'b0;
    end
end

always @ (*) begin
    if (((1'b1 == ap_CS_fsm_pp0_stage0) & (1'b1 == ap_enable_reg_pp0_iter1) & (1'd0 == exitcond3_i_i_reg_603) & (ap_block_pp0_stage0_flag00011001 == 1'b0))) begin
        AXI_video_strm_V_keep_V_1_vld_in = 1'b1;
    end else begin
        AXI_video_strm_V_keep_V_1_vld_in = 1'b0;
    end
end

always @ (*) begin
    if ((1'b1 == AXI_video_strm_V_last_V_1_sel)) begin
        AXI_video_strm_V_last_V_1_data_out = AXI_video_strm_V_last_V_1_payload_B;
    end else begin
        AXI_video_strm_V_last_V_1_data_out = AXI_video_strm_V_last_V_1_payload_A;
    end
end

always @ (*) begin
    if (((1'b1 == ap_CS_fsm_pp0_stage0) & (1'b1 == ap_enable_reg_pp0_iter1) & (1'd0 == exitcond3_i_i_reg_603) & (ap_block_pp0_stage0_flag00011001 == 1'b0))) begin
        AXI_video_strm_V_last_V_1_vld_in = 1'b1;
    end else begin
        AXI_video_strm_V_last_V_1_vld_in = 1'b0;
    end
end

always @ (*) begin
    if (((1'b1 == ap_CS_fsm_pp0_stage0) & (1'b1 == ap_enable_reg_pp0_iter1) & (1'd0 == exitcond3_i_i_reg_603) & (ap_block_pp0_stage0_flag00011001 == 1'b0))) begin
        AXI_video_strm_V_strb_V_1_vld_in = 1'b1;
    end else begin
        AXI_video_strm_V_strb_V_1_vld_in = 1'b0;
    end
end

always @ (*) begin
    if ((1'b1 == AXI_video_strm_V_user_V_1_sel)) begin
        AXI_video_strm_V_user_V_1_data_out = AXI_video_strm_V_user_V_1_payload_B;
    end else begin
        AXI_video_strm_V_user_V_1_data_out = AXI_video_strm_V_user_V_1_payload_A;
    end
end

always @ (*) begin
    if (((1'b1 == ap_CS_fsm_pp0_stage0) & (1'b1 == ap_enable_reg_pp0_iter1) & (1'd0 == exitcond3_i_i_reg_603) & (ap_block_pp0_stage0_flag00011001 == 1'b0))) begin
        AXI_video_strm_V_user_V_1_vld_in = 1'b1;
    end else begin
        AXI_video_strm_V_user_V_1_vld_in = 1'b0;
    end
end

always @ (*) begin
    if (((1'b1 == ap_CS_fsm_state1) & ~((1'b0 == ap_start) | (ap_done_reg == 1'b1)))) begin
        HwReg_height_cast9_loc_blk_n = HwReg_height_cast9_loc_empty_n;
    end else begin
        HwReg_height_cast9_loc_blk_n = 1'b1;
    end
end

always @ (*) begin
    if (((1'b1 == ap_CS_fsm_state1) & ~((1'b0 == ap_start) | (ap_done_reg == 1'b1) | (1'b0 == HwReg_height_cast9_loc_empty_n) | (1'b0 == tmp_4_loc_empty_n)))) begin
        HwReg_height_cast9_loc_read = 1'b1;
    end else begin
        HwReg_height_cast9_loc_read = 1'b0;
    end
end

always @ (*) begin
    if (((1'b1 == ap_CS_fsm_pp0_stage0) & (1'b1 == ap_enable_reg_pp0_iter1) & (1'd0 == exitcond3_i_i_reg_603) & (ap_block_pp0_stage0_flag00011001 == 1'b0))) begin
        StrmMPix_V_val_0_V0_update = 1'b1;
    end else begin
        StrmMPix_V_val_0_V0_update = 1'b0;
    end
end

always @ (*) begin
    if (((1'b1 == ap_CS_fsm_pp0_stage0) & (1'b1 == ap_enable_reg_pp0_iter1) & (ap_block_pp0_stage0_flag00000000 == 1'b0) & (1'd0 == exitcond3_i_i_reg_603))) begin
        StrmMPix_V_val_0_V_blk_n = StrmMPix_V_val_0_V_empty_n;
    end else begin
        StrmMPix_V_val_0_V_blk_n = 1'b1;
    end
end

always @ (*) begin
    if (((1'b1 == ap_CS_fsm_pp0_stage0) & (1'b1 == ap_enable_reg_pp0_iter1) & (ap_block_pp0_stage0_flag00000000 == 1'b0) & (1'd0 == exitcond3_i_i_reg_603))) begin
        StrmMPix_V_val_1_V_blk_n = StrmMPix_V_val_1_V_empty_n;
    end else begin
        StrmMPix_V_val_1_V_blk_n = 1'b1;
    end
end

always @ (*) begin
    if (((1'b1 == ap_CS_fsm_pp0_stage0) & (1'b1 == ap_enable_reg_pp0_iter1) & (ap_block_pp0_stage0_flag00000000 == 1'b0) & (1'd0 == exitcond3_i_i_reg_603))) begin
        StrmMPix_V_val_2_V_blk_n = StrmMPix_V_val_2_V_empty_n;
    end else begin
        StrmMPix_V_val_2_V_blk_n = 1'b1;
    end
end

always @ (*) begin
    if ((1'd1 == exitcond3_i_i_fu_422_p2)) begin
        ap_condition_pp0_exit_iter0_state6 = 1'b1;
    end else begin
        ap_condition_pp0_exit_iter0_state6 = 1'b0;
    end
end

always @ (*) begin
    if (((1'b1 == ap_CS_fsm_state5) & ~((1'b0 == AXI_video_strm_V_data_V_1_ack_in) | (1'b0 == AXI_video_strm_V_keep_V_1_ack_in) | (1'b0 == AXI_video_strm_V_strb_V_1_ack_in) | (1'b0 == AXI_video_strm_V_user_V_1_ack_in) | (1'b0 == AXI_video_strm_V_last_V_1_ack_in) | (1'b0 == AXI_video_strm_V_id_V_1_ack_in) | (1'b0 == AXI_video_strm_V_dest_V_1_ack_in)) & (1'd1 == exitcond2_i_i_fu_407_p2))) begin
        ap_done = 1'b1;
    end else begin
        ap_done = ap_done_reg;
    end
end

always @ (*) begin
    if (((1'b0 == ap_start) & (1'b1 == ap_CS_fsm_state1))) begin
        ap_idle = 1'b1;
    end else begin
        ap_idle = 1'b0;
    end
end

always @ (*) begin
    if (((1'b0 == ap_enable_reg_pp0_iter0) & (1'b0 == ap_enable_reg_pp0_iter1) & (1'b0 == ap_enable_reg_pp0_iter2))) begin
        ap_idle_pp0 = 1'b1;
    end else begin
        ap_idle_pp0 = 1'b0;
    end
end

always @ (*) begin
    if (((1'b1 == ap_CS_fsm_state5) & ~((1'b0 == AXI_video_strm_V_data_V_1_ack_in) | (1'b0 == AXI_video_strm_V_keep_V_1_ack_in) | (1'b0 == AXI_video_strm_V_strb_V_1_ack_in) | (1'b0 == AXI_video_strm_V_user_V_1_ack_in) | (1'b0 == AXI_video_strm_V_last_V_1_ack_in) | (1'b0 == AXI_video_strm_V_id_V_1_ack_in) | (1'b0 == AXI_video_strm_V_dest_V_1_ack_in)) & (1'd1 == exitcond2_i_i_fu_407_p2))) begin
        ap_ready = 1'b1;
    end else begin
        ap_ready = 1'b0;
    end
end

always @ (*) begin
    if ((((1'b1 == ap_CS_fsm_pp0_stage0) & (1'b1 == ap_enable_reg_pp0_iter1) & (ap_block_pp0_stage0_flag00000000 == 1'b0) & (1'd0 == exitcond3_i_i_reg_603)) | ((ap_block_pp0_stage0_flag00000000 == 1'b0) & (1'b1 == ap_enable_reg_pp0_iter2) & (1'd0 == ap_reg_pp0_iter1_exitcond3_i_i_reg_603)))) begin
        m_axis_video_TDATA_blk_n = AXI_video_strm_V_data_V_1_state[1'd1];
    end else begin
        m_axis_video_TDATA_blk_n = 1'b1;
    end
end

always @ (*) begin
    if ((1'b1 == ap_CS_fsm_state3)) begin
        mapComp_ce0 = 1'b1;
    end else begin
        mapComp_ce0 = 1'b0;
    end
end

always @ (*) begin
    if (((1'b1 == ap_CS_fsm_state1) & ~((1'b0 == ap_start) | (ap_done_reg == 1'b1)))) begin
        tmp_4_loc_blk_n = tmp_4_loc_empty_n;
    end else begin
        tmp_4_loc_blk_n = 1'b1;
    end
end

always @ (*) begin
    if (((1'b1 == ap_CS_fsm_state1) & ~((1'b0 == ap_start) | (ap_done_reg == 1'b1) | (1'b0 == HwReg_height_cast9_loc_empty_n) | (1'b0 == tmp_4_loc_empty_n)))) begin
        tmp_4_loc_read = 1'b1;
    end else begin
        tmp_4_loc_read = 1'b0;
    end
end

always @ (*) begin
    case (ap_CS_fsm)
        ap_ST_fsm_state1 : begin
            if (((1'b1 == ap_CS_fsm_state1) & ~((1'b0 == ap_start) | (ap_done_reg == 1'b1) | (1'b0 == HwReg_height_cast9_loc_empty_n) | (1'b0 == tmp_4_loc_empty_n)))) begin
                ap_NS_fsm = ap_ST_fsm_state2;
            end else begin
                ap_NS_fsm = ap_ST_fsm_state1;
            end
        end
        ap_ST_fsm_state2 : begin
            if (((1'b1 == ap_CS_fsm_state2) & (ap_block_state2_on_subcall_done == 1'b0))) begin
                ap_NS_fsm = ap_ST_fsm_state3;
            end else begin
                ap_NS_fsm = ap_ST_fsm_state2;
            end
        end
        ap_ST_fsm_state3 : begin
            if (((1'b1 == ap_CS_fsm_state3) & (1'd1 == exitcond1_i_i_fu_313_p2))) begin
                ap_NS_fsm = ap_ST_fsm_state5;
            end else begin
                ap_NS_fsm = ap_ST_fsm_state4;
            end
        end
        ap_ST_fsm_state4 : begin
            ap_NS_fsm = ap_ST_fsm_state3;
        end
        ap_ST_fsm_state5 : begin
            if (((1'b1 == ap_CS_fsm_state5) & ~((1'b0 == AXI_video_strm_V_data_V_1_ack_in) | (1'b0 == AXI_video_strm_V_keep_V_1_ack_in) | (1'b0 == AXI_video_strm_V_strb_V_1_ack_in) | (1'b0 == AXI_video_strm_V_user_V_1_ack_in) | (1'b0 == AXI_video_strm_V_last_V_1_ack_in) | (1'b0 == AXI_video_strm_V_id_V_1_ack_in) | (1'b0 == AXI_video_strm_V_dest_V_1_ack_in)) & (1'd1 == exitcond2_i_i_fu_407_p2))) begin
                ap_NS_fsm = ap_ST_fsm_state1;
            end else if (((1'b1 == ap_CS_fsm_state5) & ~((1'b0 == AXI_video_strm_V_data_V_1_ack_in) | (1'b0 == AXI_video_strm_V_keep_V_1_ack_in) | (1'b0 == AXI_video_strm_V_strb_V_1_ack_in) | (1'b0 == AXI_video_strm_V_user_V_1_ack_in) | (1'b0 == AXI_video_strm_V_last_V_1_ack_in) | (1'b0 == AXI_video_strm_V_id_V_1_ack_in) | (1'b0 == AXI_video_strm_V_dest_V_1_ack_in)) & (1'd0 == exitcond2_i_i_fu_407_p2))) begin
                ap_NS_fsm = ap_ST_fsm_pp0_stage0;
            end else begin
                ap_NS_fsm = ap_ST_fsm_state5;
            end
        end
        ap_ST_fsm_pp0_stage0 : begin
            if ((~((1'b1 == ap_enable_reg_pp0_iter2) & (ap_block_pp0_stage0_flag00011011 == 1'b0) & (ap_enable_reg_pp0_iter1 == 1'b0)) & ~((1'b1 == ap_enable_reg_pp0_iter0) & (ap_block_pp0_stage0_flag00011011 == 1'b0) & (1'd1 == exitcond3_i_i_fu_422_p2) & (ap_enable_reg_pp0_iter1 == 1'b0)))) begin
                ap_NS_fsm = ap_ST_fsm_pp0_stage0;
            end else if ((((1'b1 == ap_enable_reg_pp0_iter2) & (ap_block_pp0_stage0_flag00011011 == 1'b0) & (ap_enable_reg_pp0_iter1 == 1'b0)) | ((1'b1 == ap_enable_reg_pp0_iter0) & (ap_block_pp0_stage0_flag00011011 == 1'b0) & (1'd1 == exitcond3_i_i_fu_422_p2) & (ap_enable_reg_pp0_iter1 == 1'b0)))) begin
                ap_NS_fsm = ap_ST_fsm_state9;
            end else begin
                ap_NS_fsm = ap_ST_fsm_pp0_stage0;
            end
        end
        ap_ST_fsm_state9 : begin
            ap_NS_fsm = ap_ST_fsm_state5;
        end
        default : begin
            ap_NS_fsm = 'bx;
        end
    endcase
end

assign AXI_video_strm_V_data_V_1_ack_in = AXI_video_strm_V_data_V_1_state[1'd1];

assign AXI_video_strm_V_data_V_1_ack_out = m_axis_video_TREADY;

assign AXI_video_strm_V_data_V_1_load_A = (AXI_video_strm_V_data_V_1_state_cmp_full & ~AXI_video_strm_V_data_V_1_sel_wr);

assign AXI_video_strm_V_data_V_1_load_B = (AXI_video_strm_V_data_V_1_sel_wr & AXI_video_strm_V_data_V_1_state_cmp_full);

assign AXI_video_strm_V_data_V_1_sel = AXI_video_strm_V_data_V_1_sel_rd;

assign AXI_video_strm_V_data_V_1_state_cmp_full = ((AXI_video_strm_V_data_V_1_state != 2'd1) ? 1'b1 : 1'b0);

assign AXI_video_strm_V_data_V_1_vld_out = AXI_video_strm_V_data_V_1_state[1'd0];

assign AXI_video_strm_V_dest_V_1_ack_in = AXI_video_strm_V_dest_V_1_state[1'd1];

assign AXI_video_strm_V_dest_V_1_ack_out = m_axis_video_TREADY;

assign AXI_video_strm_V_dest_V_1_data_out = 1'd0;

assign AXI_video_strm_V_dest_V_1_sel = AXI_video_strm_V_dest_V_1_sel_rd;

assign AXI_video_strm_V_dest_V_1_vld_out = AXI_video_strm_V_dest_V_1_state[1'd0];

assign AXI_video_strm_V_id_V_1_ack_in = AXI_video_strm_V_id_V_1_state[1'd1];

assign AXI_video_strm_V_id_V_1_ack_out = m_axis_video_TREADY;

assign AXI_video_strm_V_id_V_1_data_out = 1'd0;

assign AXI_video_strm_V_id_V_1_sel = AXI_video_strm_V_id_V_1_sel_rd;

assign AXI_video_strm_V_id_V_1_vld_out = AXI_video_strm_V_id_V_1_state[1'd0];

assign AXI_video_strm_V_keep_V_1_ack_in = AXI_video_strm_V_keep_V_1_state[1'd1];

assign AXI_video_strm_V_keep_V_1_ack_out = m_axis_video_TREADY;

assign AXI_video_strm_V_keep_V_1_data_out = 3'd7;

assign AXI_video_strm_V_keep_V_1_sel = AXI_video_strm_V_keep_V_1_sel_rd;

assign AXI_video_strm_V_keep_V_1_vld_out = AXI_video_strm_V_keep_V_1_state[1'd0];

assign AXI_video_strm_V_last_V_1_ack_in = AXI_video_strm_V_last_V_1_state[1'd1];

assign AXI_video_strm_V_last_V_1_ack_out = m_axis_video_TREADY;

assign AXI_video_strm_V_last_V_1_load_A = (AXI_video_strm_V_last_V_1_state_cmp_full & ~AXI_video_strm_V_last_V_1_sel_wr);

assign AXI_video_strm_V_last_V_1_load_B = (AXI_video_strm_V_last_V_1_sel_wr & AXI_video_strm_V_last_V_1_state_cmp_full);

assign AXI_video_strm_V_last_V_1_sel = AXI_video_strm_V_last_V_1_sel_rd;

assign AXI_video_strm_V_last_V_1_state_cmp_full = ((AXI_video_strm_V_last_V_1_state != 2'd1) ? 1'b1 : 1'b0);

assign AXI_video_strm_V_last_V_1_vld_out = AXI_video_strm_V_last_V_1_state[1'd0];

assign AXI_video_strm_V_strb_V_1_ack_in = AXI_video_strm_V_strb_V_1_state[1'd1];

assign AXI_video_strm_V_strb_V_1_ack_out = m_axis_video_TREADY;

assign AXI_video_strm_V_strb_V_1_data_out = 3'd0;

assign AXI_video_strm_V_strb_V_1_sel = AXI_video_strm_V_strb_V_1_sel_rd;

assign AXI_video_strm_V_strb_V_1_vld_out = AXI_video_strm_V_strb_V_1_state[1'd0];

assign AXI_video_strm_V_user_V_1_ack_in = AXI_video_strm_V_user_V_1_state[1'd1];

assign AXI_video_strm_V_user_V_1_ack_out = m_axis_video_TREADY;

assign AXI_video_strm_V_user_V_1_load_A = (AXI_video_strm_V_user_V_1_state_cmp_full & ~AXI_video_strm_V_user_V_1_sel_wr);

assign AXI_video_strm_V_user_V_1_load_B = (AXI_video_strm_V_user_V_1_sel_wr & AXI_video_strm_V_user_V_1_state_cmp_full);

assign AXI_video_strm_V_user_V_1_sel = AXI_video_strm_V_user_V_1_sel_rd;

assign AXI_video_strm_V_user_V_1_state_cmp_full = ((AXI_video_strm_V_user_V_1_state != 2'd1) ? 1'b1 : 1'b0);

assign AXI_video_strm_V_user_V_1_vld_out = AXI_video_strm_V_user_V_1_state[1'd0];

assign Height_cast_i_i_fu_259_p1 = HwReg_height_cast9_loc_dout;

assign StrmMPix_V_val_0_V0_status = (StrmMPix_V_val_0_V_empty_n & StrmMPix_V_val_1_V_empty_n & StrmMPix_V_val_2_V_empty_n);

assign StrmMPix_V_val_0_V_read = StrmMPix_V_val_0_V0_update;

assign StrmMPix_V_val_1_V_read = StrmMPix_V_val_0_V0_update;

assign StrmMPix_V_val_2_V_read = StrmMPix_V_val_0_V0_update;

assign ap_CS_fsm_pp0_stage0 = ap_CS_fsm[32'd5];

assign ap_CS_fsm_state1 = ap_CS_fsm[32'd0];

assign ap_CS_fsm_state2 = ap_CS_fsm[32'd1];

assign ap_CS_fsm_state3 = ap_CS_fsm[32'd2];

assign ap_CS_fsm_state4 = ap_CS_fsm[32'd3];

assign ap_CS_fsm_state5 = ap_CS_fsm[32'd4];

assign ap_CS_fsm_state9 = ap_CS_fsm[32'd6];

assign ap_block_pp0_stage0_flag00000000 = ~(1'b1 == 1'b1);

always @ (*) begin
    ap_block_pp0_stage0_flag00001001 = ((1'b1 == ap_enable_reg_pp0_iter1) & (1'd0 == exitcond3_i_i_reg_603) & (1'b0 == StrmMPix_V_val_0_V0_status));
end

always @ (*) begin
    ap_block_pp0_stage0_flag00011001 = (((1'b1 == ap_enable_reg_pp0_iter1) & (((1'd0 == exitcond3_i_i_reg_603) & (1'b0 == StrmMPix_V_val_0_V0_status)) | (1'b1 == ap_block_state7_io))) | ((1'b1 == ap_enable_reg_pp0_iter2) & (1'b1 == ap_block_state8_io)));
end

always @ (*) begin
    ap_block_pp0_stage0_flag00011011 = (((1'b1 == ap_enable_reg_pp0_iter1) & (((1'd0 == exitcond3_i_i_reg_603) & (1'b0 == StrmMPix_V_val_0_V0_status)) | (1'b1 == ap_block_state7_io))) | ((1'b1 == ap_enable_reg_pp0_iter2) & (1'b1 == ap_block_state8_io)));
end

always @ (*) begin
    ap_block_state1 = ((1'b0 == ap_start) | (ap_done_reg == 1'b1) | (1'b0 == HwReg_height_cast9_loc_empty_n) | (1'b0 == tmp_4_loc_empty_n));
end

always @ (*) begin
    ap_block_state1_ignore_call18 = ((1'b0 == ap_start) | (ap_done_reg == 1'b1) | (1'b0 == HwReg_height_cast9_loc_empty_n) | (1'b0 == tmp_4_loc_empty_n));
end

always @ (*) begin
    ap_block_state1_ignore_call19 = ((1'b0 == ap_start) | (ap_done_reg == 1'b1) | (1'b0 == HwReg_height_cast9_loc_empty_n) | (1'b0 == tmp_4_loc_empty_n));
end

always @ (*) begin
    ap_block_state2_on_subcall_done = ((1'b0 == grp_reg_unsigned_short_s_fu_263_ap_done) | (1'b0 == grp_reg_unsigned_short_s_fu_269_ap_done));
end

always @ (*) begin
    ap_block_state5 = ((1'b0 == AXI_video_strm_V_data_V_1_ack_in) | (1'b0 == AXI_video_strm_V_keep_V_1_ack_in) | (1'b0 == AXI_video_strm_V_strb_V_1_ack_in) | (1'b0 == AXI_video_strm_V_user_V_1_ack_in) | (1'b0 == AXI_video_strm_V_last_V_1_ack_in) | (1'b0 == AXI_video_strm_V_id_V_1_ack_in) | (1'b0 == AXI_video_strm_V_dest_V_1_ack_in));
end

assign ap_block_state6_pp0_stage0_iter0 = ~(1'b1 == 1'b1);

always @ (*) begin
    ap_block_state7_io = ((1'd0 == exitcond3_i_i_reg_603) & (1'b0 == AXI_video_strm_V_data_V_1_ack_in));
end

always @ (*) begin
    ap_block_state7_pp0_stage0_iter1 = ((1'd0 == exitcond3_i_i_reg_603) & (1'b0 == StrmMPix_V_val_0_V0_status));
end

always @ (*) begin
    ap_block_state8_io = ((1'd0 == ap_reg_pp0_iter1_exitcond3_i_i_reg_603) & (1'b0 == AXI_video_strm_V_data_V_1_ack_in));
end

assign ap_block_state8_pp0_stage0_iter2 = ~(1'b1 == 1'b1);

assign ap_enable_pp0 = (ap_idle_pp0 ^ 1'b1);

assign axi_last_V_fu_433_p2 = ((j_cast_i_i_fu_418_p1 == tmp_7_i_i_reg_559) ? 1'b1 : 1'b0);

assign cols_cast_i_i_fu_275_p1 = grp_reg_unsigned_short_s_fu_269_ap_return;

assign exitcond1_i_i_fu_313_p2 = ((i_i_i_reg_221 == 2'd3) ? 1'b1 : 1'b0);

assign exitcond2_i_i_fu_407_p2 = ((i1_cast_i_i_fu_403_p1 == tmp_i_i_reg_519) ? 1'b1 : 1'b0);

assign exitcond3_i_i_fu_422_p2 = ((j_i_i_reg_244 == tmp_i_i_61_reg_524) ? 1'b1 : 1'b0);

assign grp_reg_unsigned_short_s_fu_263_ap_start = ap_reg_grp_reg_unsigned_short_s_fu_263_ap_start;

assign grp_reg_unsigned_short_s_fu_269_ap_start = ap_reg_grp_reg_unsigned_short_s_fu_269_ap_start;

assign grp_reg_unsigned_short_s_fu_269_in_r = HwReg_width[9:0];

assign i1_cast_i_i_fu_403_p1 = i1_i_i_reg_233;

assign i_1_fu_412_p2 = (i1_i_i_reg_233 + 9'd1);

assign i_cast6_i_i_cast_fu_299_p1 = i_i_i_reg_221;

assign i_fu_319_p2 = (i_i_i_reg_221 + 2'd1);

assign j_cast_i_i_fu_418_p1 = j_i_i_reg_244;

assign j_fu_427_p2 = (j_i_i_reg_244 + 10'd1);

assign m_axis_video_TDATA = AXI_video_strm_V_data_V_1_data_out;

assign m_axis_video_TDEST = AXI_video_strm_V_dest_V_1_data_out;

assign m_axis_video_TID = AXI_video_strm_V_id_V_1_data_out;

assign m_axis_video_TKEEP = AXI_video_strm_V_keep_V_1_data_out;

assign m_axis_video_TLAST = AXI_video_strm_V_last_V_1_data_out;

assign m_axis_video_TSTRB = AXI_video_strm_V_strb_V_1_data_out;

assign m_axis_video_TUSER = AXI_video_strm_V_user_V_1_data_out;

assign m_axis_video_TVALID = AXI_video_strm_V_dest_V_1_state[1'd0];

assign mapComp_address0 = tmp_5_cast_fu_308_p1;

assign map_0_V_cast_fu_347_p1 = mapComp_q0;

assign map_2_V_1_fu_371_p3 = ((sel_tmp2_fu_365_p2[0:0] === 1'b1) ? map_V_2_i_i_reg_185 : map_2_V_fu_357_p3);

assign map_2_V_2_fu_379_p3 = ((sel_tmp_fu_351_p2[0:0] === 1'b1) ? map_0_V_cast_fu_347_p1 : map_V_1_i_i_reg_197);

assign map_2_V_3_fu_387_p3 = ((sel_tmp2_fu_365_p2[0:0] === 1'b1) ? map_V_1_i_i_reg_197 : map_2_V_2_fu_379_p3);

assign map_2_V_5_fu_395_p3 = ((sel_tmp2_fu_365_p2[0:0] === 1'b1) ? map_0_V_cast_fu_347_p1 : map_2_V_4_reg_209);

assign map_2_V_fu_357_p3 = ((sel_tmp_fu_351_p2[0:0] === 1'b1) ? map_V_2_i_i_reg_185 : map_0_V_cast_fu_347_p1);

assign p_shl_cast_fu_289_p1 = tmp_3_fu_282_p3;

assign sel_tmp2_fu_365_p2 = ((i_i_i_reg_221 == 2'd0) ? 1'b1 : 1'b0);

assign sel_tmp_fu_351_p2 = ((i_i_i_reg_221 == 2'd1) ? 1'b1 : 1'b0);

assign tmp_3_fu_282_p3 = {{tmp_4_loc_read_reg_508}, {2'd0}};

assign tmp_4_fu_293_p2 = (p_shl_cast_fu_289_p1 - tmp_5_i_i_cast_fu_279_p1);

assign tmp_5_cast_fu_308_p1 = $signed(tmp_5_fu_303_p2);

assign tmp_5_fu_303_p2 = (tmp_4_reg_534 + i_cast6_i_i_cast_fu_299_p1);

assign tmp_5_i_i_cast_fu_279_p1 = tmp_4_loc_read_reg_508;

assign tmp_7_fu_330_p1 = map_2_V_4_reg_209[1:0];

assign tmp_7_i_i_fu_325_p2 = ($signed(11'd2047) + $signed(cols_cast_i_i_reg_529));

assign tmp_8_fu_334_p1 = map_V_1_i_i_reg_197[1:0];

assign tmp_9_fu_338_p1 = map_V_2_i_i_reg_185[1:0];

assign tmp_data_V_fu_487_p4 = {{{tmp_2_fu_476_p5}, {tmp_1_fu_465_p5}}, {tmp_fu_454_p5}};

always @ (posedge ap_clk) begin
    Height_cast_i_i_reg_514[9] <= 1'b0;
    cols_cast_i_i_reg_529[10] <= 1'b0;
end

endmodule //design_1_v_frmbuf_rd_0_0_MultiPixStream2AXIvi
