// ==============================================================
// RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2017.2
// Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved.
// 
// ===========================================================

`timescale 1 ns / 1 ps 

module design_1_v_frmbuf_wr_0_0_MultiPixStream2Bytes (
        ap_clk,
        ap_rst,
        ap_start,
        ap_done,
        ap_continue,
        ap_idle,
        ap_ready,
        StrmMPix_V_val_0_V_dout,
        StrmMPix_V_val_0_V_empty_n,
        StrmMPix_V_val_0_V_read,
        StrmMPix_V_val_1_V_dout,
        StrmMPix_V_val_1_V_empty_n,
        StrmMPix_V_val_1_V_read,
        StrmMPix_V_val_2_V_dout,
        StrmMPix_V_val_2_V_empty_n,
        StrmMPix_V_val_2_V_read,
        bytes_plane0_V_V_din,
        bytes_plane0_V_V_full_n,
        bytes_plane0_V_V_write,
        HwReg_height_cast8_loc_dout,
        HwReg_height_cast8_loc_empty_n,
        HwReg_height_cast8_loc_read,
        HwReg_width_cast9_loc_dout,
        HwReg_width_cast9_loc_empty_n,
        HwReg_width_cast9_loc_read,
        tmp_3_loc_dout,
        tmp_3_loc_empty_n,
        tmp_3_loc_read,
        HwReg_video_format,
        HwReg_height_cast8_loc_out_din,
        HwReg_height_cast8_loc_out_full_n,
        HwReg_height_cast8_loc_out_write,
        tmp_3_loc_out_din,
        tmp_3_loc_out_full_n,
        tmp_3_loc_out_write
);

parameter    ap_ST_fsm_state1 = 12'd1;
parameter    ap_ST_fsm_state2 = 12'd2;
parameter    ap_ST_fsm_state3 = 12'd4;
parameter    ap_ST_fsm_pp0_stage0 = 12'd8;
parameter    ap_ST_fsm_pp0_stage1 = 12'd16;
parameter    ap_ST_fsm_pp0_stage2 = 12'd32;
parameter    ap_ST_fsm_pp0_stage3 = 12'd64;
parameter    ap_ST_fsm_pp0_stage4 = 12'd128;
parameter    ap_ST_fsm_pp0_stage5 = 12'd256;
parameter    ap_ST_fsm_pp0_stage6 = 12'd512;
parameter    ap_ST_fsm_pp0_stage7 = 12'd1024;
parameter    ap_ST_fsm_state13 = 12'd2048;

input   ap_clk;
input   ap_rst;
input   ap_start;
output   ap_done;
input   ap_continue;
output   ap_idle;
output   ap_ready;
input  [7:0] StrmMPix_V_val_0_V_dout;
input   StrmMPix_V_val_0_V_empty_n;
output   StrmMPix_V_val_0_V_read;
input  [7:0] StrmMPix_V_val_1_V_dout;
input   StrmMPix_V_val_1_V_empty_n;
output   StrmMPix_V_val_1_V_read;
input  [7:0] StrmMPix_V_val_2_V_dout;
input   StrmMPix_V_val_2_V_empty_n;
output   StrmMPix_V_val_2_V_read;
output  [63:0] bytes_plane0_V_V_din;
input   bytes_plane0_V_V_full_n;
output   bytes_plane0_V_V_write;
input  [8:0] HwReg_height_cast8_loc_dout;
input   HwReg_height_cast8_loc_empty_n;
output   HwReg_height_cast8_loc_read;
input  [9:0] HwReg_width_cast9_loc_dout;
input   HwReg_width_cast9_loc_empty_n;
output   HwReg_width_cast9_loc_read;
input  [11:0] tmp_3_loc_dout;
input   tmp_3_loc_empty_n;
output   tmp_3_loc_read;
input  [15:0] HwReg_video_format;
output  [8:0] HwReg_height_cast8_loc_out_din;
input   HwReg_height_cast8_loc_out_full_n;
output   HwReg_height_cast8_loc_out_write;
output  [11:0] tmp_3_loc_out_din;
input   tmp_3_loc_out_full_n;
output   tmp_3_loc_out_write;

reg ap_done;
reg ap_idle;
reg ap_ready;
reg[63:0] bytes_plane0_V_V_din;
reg bytes_plane0_V_V_write;
reg HwReg_height_cast8_loc_read;
reg HwReg_width_cast9_loc_read;
reg tmp_3_loc_read;
reg HwReg_height_cast8_loc_out_write;
reg tmp_3_loc_out_write;

reg    ap_done_reg;
(* fsm_encoding = "none" *) reg   [11:0] ap_CS_fsm;
wire    ap_CS_fsm_state1;
reg    StrmMPix_V_val_0_V_blk_n;
wire    ap_CS_fsm_pp0_stage1;
reg    ap_enable_reg_pp0_iter0;
wire    ap_block_pp0_stage1_flag00000000;
reg   [0:0] tmp_13_i_i_reg_1248;
reg   [0:0] or_cond_i_i_reg_1268;
wire    ap_CS_fsm_pp0_stage2;
wire    ap_block_pp0_stage2_flag00000000;
reg   [0:0] or_cond_1_i_i_reg_1314;
wire    ap_CS_fsm_pp0_stage3;
wire    ap_block_pp0_stage3_flag00000000;
reg   [0:0] or_cond_2_i_i_reg_1333;
wire    ap_CS_fsm_pp0_stage4;
wire    ap_block_pp0_stage4_flag00000000;
reg   [0:0] or_cond_3_i_i_reg_1352;
wire    ap_CS_fsm_pp0_stage5;
wire    ap_block_pp0_stage5_flag00000000;
reg   [0:0] or_cond_4_i_i_reg_1371;
wire    ap_CS_fsm_pp0_stage6;
wire    ap_block_pp0_stage6_flag00000000;
reg   [0:0] or_cond_5_i_i_reg_1390;
wire    ap_CS_fsm_pp0_stage7;
wire    ap_block_pp0_stage7_flag00000000;
reg   [0:0] or_cond_6_i_i_reg_1394;
wire    ap_CS_fsm_pp0_stage0;
reg    ap_enable_reg_pp0_iter1;
wire    ap_block_pp0_stage0_flag00000000;
reg   [0:0] or_cond_7_i_i_reg_1398;
reg    StrmMPix_V_val_1_V_blk_n;
reg    StrmMPix_V_val_2_V_blk_n;
reg    bytes_plane0_V_V_blk_n;
reg   [0:0] or_cond1_i_i_reg_1272;
reg   [0:0] or_cond1_1_i_i_reg_1276;
reg   [0:0] or_cond1_2_i_i_reg_1280;
reg    HwReg_height_cast8_loc_blk_n;
reg    HwReg_width_cast9_loc_blk_n;
reg    tmp_3_loc_blk_n;
reg    HwReg_height_cast8_loc_out_blk_n;
reg    tmp_3_loc_out_blk_n;
reg   [7:0] x_i_i_reg_254;
reg   [7:0] pix_val_V_2_2_i_i_reg_265;
reg   [7:0] pix_val_V_1_2_i_i_reg_275;
reg   [7:0] pix_val_V_0_2_i_i_reg_285;
reg   [7:0] pix_val_V_2_3_i_i_reg_295;
reg   [7:0] pix_val_V_1_3_i_i_reg_306;
reg   [7:0] pix_val_V_0_3_i_i_reg_317;
reg   [7:0] pix_val_V_2_4_i_i_reg_328;
reg   [7:0] pix_val_V_2_5_i_i_reg_361;
reg   [7:0] pix_val_V_1_5_i_i_reg_372;
reg   [7:0] pix_val_V_0_5_i_i_reg_383;
reg   [7:0] pix_val_V_2_6_i_i_reg_394;
reg   [7:0] pix_val_V_1_6_i_i_reg_405;
reg   [7:0] pix_val_V_0_6_i_i_reg_416;
reg   [7:0] pix_val_V_2_7_i_i_reg_427;
reg   [7:0] pix_val_V_1_7_i_i_reg_438;
reg   [8:0] HwReg_height_cast8_l_reg_1103;
reg    ap_block_state1;
wire   [0:0] icmp_fu_555_p2;
wire   [0:0] icmp1_fu_577_p2;
wire   [0:0] tmp_i_i_fu_583_p2;
wire   [0:0] icmp2_fu_605_p2;
wire   [0:0] icmp3_fu_627_p2;
wire   [0:0] icmp4_fu_649_p2;
wire   [9:0] tmp_6_i_i_fu_675_p2;
reg   [9:0] tmp_6_i_i_reg_1156;
wire   [2:0] remPix_fu_681_p1;
reg   [2:0] remPix_reg_1161;
wire   [8:0] loopWidth_cast_i_i_c_fu_699_p4;
reg   [8:0] loopWidth_cast_i_i_c_reg_1169;
wire    ap_CS_fsm_state2;
wire   [0:0] tmp_7_i_i_fu_712_p2;
reg   [0:0] tmp_7_i_i_reg_1174;
wire   [16:0] tmp_11_cast_i_i_fu_777_p1;
reg   [16:0] tmp_11_cast_i_i_reg_1179;
wire   [8:0] tmp_12_i_i_fu_780_p2;
reg   [8:0] tmp_12_i_i_reg_1184;
wire   [0:0] tmp_24_i_i_fu_786_p2;
reg   [0:0] tmp_24_i_i_reg_1189;
wire   [0:0] icmp5_fu_802_p2;
reg   [0:0] icmp5_reg_1194;
wire   [0:0] tmp_24_2_i_i_fu_808_p2;
reg   [0:0] tmp_24_2_i_i_reg_1199;
wire   [0:0] icmp6_fu_824_p2;
reg   [0:0] icmp6_reg_1204;
wire   [0:0] tmp_24_4_i_i_fu_830_p2;
reg   [0:0] tmp_24_4_i_i_reg_1209;
wire   [0:0] tmp_24_5_i_i_fu_836_p2;
reg   [0:0] tmp_24_5_i_i_reg_1214;
wire   [0:0] tmp_24_6_i_i_fu_842_p2;
reg   [0:0] tmp_24_6_i_i_reg_1219;
wire   [0:0] tmp_25_i_i_fu_848_p2;
reg   [0:0] tmp_25_i_i_reg_1224;
wire   [0:0] icmp7_fu_864_p2;
reg   [0:0] icmp7_reg_1229;
wire   [0:0] tmp_25_2_i_i_fu_870_p2;
reg   [0:0] tmp_25_2_i_i_reg_1234;
wire   [0:0] exitcond1_i_i_fu_880_p2;
wire    ap_CS_fsm_state3;
wire   [15:0] y_fu_885_p2;
reg   [15:0] y_reg_1243;
wire   [0:0] tmp_13_i_i_fu_895_p2;
wire    ap_block_state4_pp0_stage0_iter0;
wire    StrmMPix_V_val_0_V0_status;
reg    ap_predicate_op205_read_state12;
reg    ap_block_state12_pp0_stage0_iter1;
reg    ap_block_pp0_stage0_flag00011001;
wire   [7:0] x_fu_900_p2;
reg   [7:0] x_reg_1252;
wire   [0:0] tmp_14_i_i_fu_906_p2;
reg   [0:0] tmp_14_i_i_reg_1257;
wire   [0:0] or_cond_i_i_fu_911_p2;
wire   [0:0] or_cond1_i_i_fu_916_p2;
wire   [0:0] or_cond1_1_i_i_fu_921_p2;
wire   [0:0] or_cond1_2_i_i_fu_926_p2;
reg    ap_predicate_op129_read_state5;
reg    ap_block_state5_pp0_stage1_iter0;
reg    ap_block_pp0_stage1_flag00011001;
wire   [0:0] or_cond_1_i_i_fu_940_p2;
reg    ap_predicate_op139_read_state6;
reg    ap_block_state6_pp0_stage2_iter0;
reg    ap_block_pp0_stage2_flag00011001;
wire   [0:0] or_cond_2_i_i_fu_944_p2;
reg    ap_predicate_op149_read_state7;
reg    ap_block_state7_pp0_stage3_iter0;
reg    ap_block_pp0_stage3_flag00011001;
wire   [0:0] or_cond_3_i_i_fu_948_p2;
reg    ap_predicate_op159_read_state8;
reg    ap_predicate_op166_write_state8;
reg    ap_block_state8_pp0_stage4_iter0;
reg    ap_block_pp0_stage4_flag00011001;
wire   [0:0] or_cond_4_i_i_fu_952_p2;
reg    ap_predicate_op172_read_state9;
reg    ap_block_state9_pp0_stage5_iter0;
reg    ap_block_pp0_stage5_flag00011001;
wire   [0:0] or_cond_5_i_i_fu_977_p2;
wire   [0:0] or_cond_6_i_i_fu_981_p2;
wire   [0:0] or_cond_7_i_i_fu_985_p2;
reg    ap_predicate_op184_read_state10;
reg    ap_block_state10_pp0_stage6_iter0;
reg    ap_block_pp0_stage6_flag00011001;
reg    ap_predicate_op193_read_state11;
reg    ap_predicate_op199_write_state11;
reg    ap_block_state11_pp0_stage7_iter0;
reg    ap_block_pp0_stage7_flag00011001;
reg    ap_block_pp0_stage1_flag00011011;
reg    ap_condition_pp0_exit_iter0_state5;
reg    ap_block_pp0_stage7_flag00011011;
reg   [15:0] y_i_i_reg_243;
wire    ap_CS_fsm_state13;
reg   [7:0] x_i_i_phi_fu_258_p4;
reg   [7:0] ap_phi_precharge_reg_pp0_iter0_pix_val_V_2_2_i_i_reg_265;
reg   [7:0] ap_phi_precharge_reg_pp0_iter0_pix_val_V_1_2_i_i_reg_275;
reg   [7:0] ap_phi_precharge_reg_pp0_iter0_pix_val_V_0_2_i_i_reg_285;
reg   [7:0] ap_phi_precharge_reg_pp0_iter0_pix_val_V_2_3_i_i_reg_295;
reg   [7:0] ap_phi_precharge_reg_pp0_iter0_pix_val_V_1_3_i_i_reg_306;
reg   [7:0] ap_phi_precharge_reg_pp0_iter0_pix_val_V_0_3_i_i_reg_317;
reg   [7:0] ap_phi_precharge_reg_pp0_iter0_pix_val_V_2_4_i_i_reg_328;
reg   [7:0] ap_phi_precharge_reg_pp0_iter0_pix_val_V_1_4_i_i_reg_339;
reg   [7:0] ap_phi_precharge_reg_pp0_iter0_pix_val_V_0_4_i_i_reg_350;
reg   [7:0] ap_phi_precharge_reg_pp0_iter0_pix_val_V_2_5_i_i_reg_361;
reg   [7:0] ap_phi_precharge_reg_pp0_iter0_pix_val_V_1_5_i_i_reg_372;
reg   [7:0] ap_phi_precharge_reg_pp0_iter0_pix_val_V_0_5_i_i_reg_383;
reg   [7:0] ap_phi_precharge_reg_pp0_iter0_pix_val_V_2_6_i_i_reg_394;
reg   [7:0] ap_phi_precharge_reg_pp0_iter0_pix_val_V_1_6_i_i_reg_405;
reg   [7:0] ap_phi_precharge_reg_pp0_iter0_pix_val_V_0_6_i_i_reg_416;
reg   [7:0] ap_phi_precharge_reg_pp0_iter0_pix_val_V_2_7_i_i_reg_427;
reg   [7:0] ap_phi_precharge_reg_pp0_iter0_pix_val_V_1_7_i_i_reg_438;
reg   [7:0] ap_phi_precharge_reg_pp0_iter0_pix_val_V_0_7_i_i_reg_449;
wire   [7:0] ap_phi_precharge_reg_pp0_iter0_pix_val_V_2_8_i_i_reg_460;
reg   [7:0] ap_phi_precharge_reg_pp0_iter1_pix_val_V_2_8_i_i_reg_460;
wire   [7:0] ap_phi_precharge_reg_pp0_iter0_pix_val_V_1_8_i_i_reg_470;
reg   [7:0] ap_phi_precharge_reg_pp0_iter1_pix_val_V_1_8_i_i_reg_470;
wire   [7:0] ap_phi_precharge_reg_pp0_iter0_pix_val_V_0_8_i_i_reg_480;
reg   [7:0] ap_phi_precharge_reg_pp0_iter1_pix_val_V_0_8_i_i_reg_480;
wire   [7:0] ap_phi_precharge_reg_pp0_iter0_pix_val_V_2_9_i_i_reg_490;
reg   [7:0] ap_phi_precharge_reg_pp0_iter1_pix_val_V_2_9_i_i_reg_490;
reg   [7:0] pix_val_V_2_9_i_i_phi_fu_493_p4;
wire   [7:0] ap_phi_precharge_reg_pp0_iter0_pix_val_V_1_9_i_i_reg_500;
reg   [7:0] ap_phi_precharge_reg_pp0_iter1_pix_val_V_1_9_i_i_reg_500;
reg   [7:0] pix_val_V_1_9_i_i_phi_fu_503_p4;
wire   [7:0] ap_phi_precharge_reg_pp0_iter0_pix_val_V_0_9_i_i_reg_510;
reg   [7:0] ap_phi_precharge_reg_pp0_iter1_pix_val_V_0_9_i_i_reg_510;
reg   [7:0] pix_val_V_0_9_i_i_phi_fu_513_p4;
reg    StrmMPix_V_val_0_V0_update;
wire   [63:0] tmp_V_fu_956_p9;
reg    ap_block_pp0_stage4_flag00001001;
wire   [63:0] tmp_V_1_fu_989_p9;
reg    ap_block_pp0_stage7_flag00001001;
wire   [63:0] tmp_V_2_fu_1062_p9;
reg    ap_block_pp0_stage0_flag00001001;
reg   [7:0] tmp_val_0_V_fu_174;
reg   [7:0] tmp_val_1_V_fu_178;
reg   [7:0] tmp_val_2_V_fu_182;
wire   [7:0] tmp_fu_535_p1;
wire   [7:0] VideoFormat_off_i_i_fu_539_p2;
wire   [6:0] tmp_2_fu_545_p4;
wire   [7:0] VideoFormat_off1_i_i_fu_561_p2;
wire   [6:0] tmp_3_fu_567_p4;
wire   [7:0] VideoFormat_off2_i_i_fu_589_p2;
wire   [6:0] tmp_4_fu_595_p4;
wire   [7:0] VideoFormat_off3_i_i_fu_611_p2;
wire   [6:0] tmp_5_fu_617_p4;
wire   [7:0] VideoFormat_off4_i_i_fu_633_p2;
wire   [6:0] tmp_6_fu_639_p4;
wire   [12:0] tmp_cast_i_i_cast_fu_655_p1;
wire   [12:0] tmp_5_i_i_fu_659_p2;
wire   [9:0] loopWidth1_cast_i_i_s_fu_665_p4;
wire   [9:0] mul_fu_693_p1;
wire   [21:0] mul_fu_693_p2;
wire   [3:0] remPix_cast_i_i_fu_709_p1;
wire   [7:0] p_shl_i_i_fu_725_p3;
wire   [5:0] p_shl1_i_i_fu_736_p3;
wire   [8:0] p_shl_cast_i_i_fu_732_p1;
wire   [8:0] p_shl1_cast_i_i_fu_743_p1;
wire   [8:0] tmp_8_i_i_fu_747_p2;
wire   [8:0] tmp_9_i_i_fu_753_p2;
wire   [2:0] tmp_10_cast_i_i_fu_759_p4;
wire   [3:0] remPix_2_fu_717_p3;
wire   [2:0] tmp_8_fu_792_p4;
wire   [1:0] tmp_9_fu_814_p4;
wire   [2:0] remainTrx_fu_769_p3;
wire   [1:0] tmp_10_fu_854_p4;
wire   [16:0] y_cast_i_i_fu_876_p1;
wire   [8:0] x_cast_i_i_cast_fu_891_p1;
reg   [11:0] ap_NS_fsm;
reg    ap_block_pp0_stage0_flag00011011;
reg    ap_block_pp0_stage2_flag00011011;
reg    ap_block_pp0_stage3_flag00011011;
reg    ap_block_pp0_stage4_flag00011011;
reg    ap_block_pp0_stage5_flag00011011;
reg    ap_block_pp0_stage6_flag00011011;
reg    ap_idle_pp0;
wire    ap_enable_pp0;
wire   [21:0] mul_fu_693_p10;
reg    ap_condition_1138;
reg    ap_condition_1143;
reg    ap_condition_1147;
reg    ap_condition_1151;
reg    ap_condition_1155;
reg    ap_condition_1159;
reg    ap_condition_515;
reg    ap_condition_549;

// power-on initialization
initial begin
#0 ap_done_reg = 1'b0;
#0 ap_CS_fsm = 12'd1;
#0 ap_enable_reg_pp0_iter0 = 1'b0;
#0 ap_enable_reg_pp0_iter1 = 1'b0;
end

always @ (posedge ap_clk) begin
    if (ap_rst == 1'b1) begin
        ap_CS_fsm <= ap_ST_fsm_state1;
    end else begin
        ap_CS_fsm <= ap_NS_fsm;
    end
end

always @ (posedge ap_clk) begin
    if (ap_rst == 1'b1) begin
        ap_done_reg <= 1'b0;
    end else begin
        if ((1'b1 == ap_continue)) begin
            ap_done_reg <= 1'b0;
        end else if (((1'b1 == ap_CS_fsm_state3) & ((1'd1 == icmp_fu_555_p2) | (1'd1 == icmp1_fu_577_p2) | (1'd1 == tmp_i_i_fu_583_p2) | (1'd1 == icmp2_fu_605_p2) | (1'd1 == icmp3_fu_627_p2) | (1'd0 == icmp4_fu_649_p2) | (1'd1 == exitcond1_i_i_fu_880_p2)))) begin
            ap_done_reg <= 1'b1;
        end
    end
end

always @ (posedge ap_clk) begin
    if (ap_rst == 1'b1) begin
        ap_enable_reg_pp0_iter0 <= 1'b0;
    end else begin
        if (((1'b1 == ap_CS_fsm_pp0_stage1) & (ap_block_pp0_stage1_flag00011011 == 1'b0) & (1'b1 == ap_condition_pp0_exit_iter0_state5))) begin
            ap_enable_reg_pp0_iter0 <= 1'b0;
        end else if (((icmp_fu_555_p2 == 1'd0) & (icmp1_fu_577_p2 == 1'd0) & (1'd0 == tmp_i_i_fu_583_p2) & (1'd0 == icmp2_fu_605_p2) & (1'd0 == icmp3_fu_627_p2) & (1'd1 == icmp4_fu_649_p2) & (1'b1 == ap_CS_fsm_state3) & (1'd0 == exitcond1_i_i_fu_880_p2))) begin
            ap_enable_reg_pp0_iter0 <= 1'b1;
        end
    end
end

always @ (posedge ap_clk) begin
    if (ap_rst == 1'b1) begin
        ap_enable_reg_pp0_iter1 <= 1'b0;
    end else begin
        if (((1'b1 == ap_condition_pp0_exit_iter0_state5) & (((1'b1 == ap_CS_fsm_pp0_stage1) & (ap_block_pp0_stage1_flag00011011 == 1'b0)) | ((1'b1 == ap_CS_fsm_pp0_stage7) & (ap_block_pp0_stage7_flag00011011 == 1'b0))))) begin
            ap_enable_reg_pp0_iter1 <= (ap_condition_pp0_exit_iter0_state5 ^ 1'b1);
        end else if ((((1'b1 == ap_CS_fsm_pp0_stage1) & (ap_block_pp0_stage1_flag00011011 == 1'b0)) | ((1'b1 == ap_CS_fsm_pp0_stage7) & (ap_block_pp0_stage7_flag00011011 == 1'b0)))) begin
            ap_enable_reg_pp0_iter1 <= ap_enable_reg_pp0_iter0;
        end else if (((icmp_fu_555_p2 == 1'd0) & (icmp1_fu_577_p2 == 1'd0) & (1'd0 == tmp_i_i_fu_583_p2) & (1'd0 == icmp2_fu_605_p2) & (1'd0 == icmp3_fu_627_p2) & (1'd1 == icmp4_fu_649_p2) & (1'b1 == ap_CS_fsm_state3) & (1'd0 == exitcond1_i_i_fu_880_p2))) begin
            ap_enable_reg_pp0_iter1 <= 1'b0;
        end
    end
end

always @ (posedge ap_clk) begin
    if ((ap_condition_1138 == 1'b1)) begin
        if ((or_cond_i_i_reg_1268 == 1'd0)) begin
            ap_phi_precharge_reg_pp0_iter0_pix_val_V_0_2_i_i_reg_285 <= tmp_val_0_V_fu_174;
        end else if ((1'd1 == or_cond_i_i_reg_1268)) begin
            ap_phi_precharge_reg_pp0_iter0_pix_val_V_0_2_i_i_reg_285 <= StrmMPix_V_val_0_V_dout;
        end
    end
end

always @ (posedge ap_clk) begin
    if ((ap_condition_1143 == 1'b1)) begin
        if ((or_cond_1_i_i_reg_1314 == 1'd0)) begin
            ap_phi_precharge_reg_pp0_iter0_pix_val_V_0_3_i_i_reg_317 <= ap_phi_precharge_reg_pp0_iter0_pix_val_V_0_2_i_i_reg_285;
        end else if ((1'd1 == or_cond_1_i_i_reg_1314)) begin
            ap_phi_precharge_reg_pp0_iter0_pix_val_V_0_3_i_i_reg_317 <= StrmMPix_V_val_0_V_dout;
        end
    end
end

always @ (posedge ap_clk) begin
    if ((ap_condition_1147 == 1'b1)) begin
        if ((or_cond_2_i_i_reg_1333 == 1'd0)) begin
            ap_phi_precharge_reg_pp0_iter0_pix_val_V_0_4_i_i_reg_350 <= ap_phi_precharge_reg_pp0_iter0_pix_val_V_0_3_i_i_reg_317;
        end else if ((1'd1 == or_cond_2_i_i_reg_1333)) begin
            ap_phi_precharge_reg_pp0_iter0_pix_val_V_0_4_i_i_reg_350 <= StrmMPix_V_val_0_V_dout;
        end
    end
end

always @ (posedge ap_clk) begin
    if ((ap_condition_1151 == 1'b1)) begin
        if ((or_cond_3_i_i_reg_1352 == 1'd0)) begin
            ap_phi_precharge_reg_pp0_iter0_pix_val_V_0_5_i_i_reg_383 <= ap_phi_precharge_reg_pp0_iter0_pix_val_V_0_4_i_i_reg_350;
        end else if ((1'd1 == or_cond_3_i_i_reg_1352)) begin
            ap_phi_precharge_reg_pp0_iter0_pix_val_V_0_5_i_i_reg_383 <= StrmMPix_V_val_0_V_dout;
        end
    end
end

always @ (posedge ap_clk) begin
    if ((ap_condition_1155 == 1'b1)) begin
        if ((or_cond_4_i_i_reg_1371 == 1'd0)) begin
            ap_phi_precharge_reg_pp0_iter0_pix_val_V_0_6_i_i_reg_416 <= ap_phi_precharge_reg_pp0_iter0_pix_val_V_0_5_i_i_reg_383;
        end else if ((1'd1 == or_cond_4_i_i_reg_1371)) begin
            ap_phi_precharge_reg_pp0_iter0_pix_val_V_0_6_i_i_reg_416 <= StrmMPix_V_val_0_V_dout;
        end
    end
end

always @ (posedge ap_clk) begin
    if ((ap_condition_1159 == 1'b1)) begin
        if ((or_cond_5_i_i_reg_1390 == 1'd0)) begin
            ap_phi_precharge_reg_pp0_iter0_pix_val_V_0_7_i_i_reg_449 <= ap_phi_precharge_reg_pp0_iter0_pix_val_V_0_6_i_i_reg_416;
        end else if ((1'd1 == or_cond_5_i_i_reg_1390)) begin
            ap_phi_precharge_reg_pp0_iter0_pix_val_V_0_7_i_i_reg_449 <= StrmMPix_V_val_0_V_dout;
        end
    end
end

always @ (posedge ap_clk) begin
    if ((ap_condition_1138 == 1'b1)) begin
        if ((or_cond_i_i_reg_1268 == 1'd0)) begin
            ap_phi_precharge_reg_pp0_iter0_pix_val_V_1_2_i_i_reg_275 <= tmp_val_1_V_fu_178;
        end else if ((1'd1 == or_cond_i_i_reg_1268)) begin
            ap_phi_precharge_reg_pp0_iter0_pix_val_V_1_2_i_i_reg_275 <= StrmMPix_V_val_1_V_dout;
        end
    end
end

always @ (posedge ap_clk) begin
    if ((ap_condition_1143 == 1'b1)) begin
        if ((or_cond_1_i_i_reg_1314 == 1'd0)) begin
            ap_phi_precharge_reg_pp0_iter0_pix_val_V_1_3_i_i_reg_306 <= ap_phi_precharge_reg_pp0_iter0_pix_val_V_1_2_i_i_reg_275;
        end else if ((1'd1 == or_cond_1_i_i_reg_1314)) begin
            ap_phi_precharge_reg_pp0_iter0_pix_val_V_1_3_i_i_reg_306 <= StrmMPix_V_val_1_V_dout;
        end
    end
end

always @ (posedge ap_clk) begin
    if ((ap_condition_1147 == 1'b1)) begin
        if ((or_cond_2_i_i_reg_1333 == 1'd0)) begin
            ap_phi_precharge_reg_pp0_iter0_pix_val_V_1_4_i_i_reg_339 <= ap_phi_precharge_reg_pp0_iter0_pix_val_V_1_3_i_i_reg_306;
        end else if ((1'd1 == or_cond_2_i_i_reg_1333)) begin
            ap_phi_precharge_reg_pp0_iter0_pix_val_V_1_4_i_i_reg_339 <= StrmMPix_V_val_1_V_dout;
        end
    end
end

always @ (posedge ap_clk) begin
    if ((ap_condition_1151 == 1'b1)) begin
        if ((or_cond_3_i_i_reg_1352 == 1'd0)) begin
            ap_phi_precharge_reg_pp0_iter0_pix_val_V_1_5_i_i_reg_372 <= ap_phi_precharge_reg_pp0_iter0_pix_val_V_1_4_i_i_reg_339;
        end else if ((1'd1 == or_cond_3_i_i_reg_1352)) begin
            ap_phi_precharge_reg_pp0_iter0_pix_val_V_1_5_i_i_reg_372 <= StrmMPix_V_val_1_V_dout;
        end
    end
end

always @ (posedge ap_clk) begin
    if ((ap_condition_1155 == 1'b1)) begin
        if ((or_cond_4_i_i_reg_1371 == 1'd0)) begin
            ap_phi_precharge_reg_pp0_iter0_pix_val_V_1_6_i_i_reg_405 <= ap_phi_precharge_reg_pp0_iter0_pix_val_V_1_5_i_i_reg_372;
        end else if ((1'd1 == or_cond_4_i_i_reg_1371)) begin
            ap_phi_precharge_reg_pp0_iter0_pix_val_V_1_6_i_i_reg_405 <= StrmMPix_V_val_1_V_dout;
        end
    end
end

always @ (posedge ap_clk) begin
    if ((ap_condition_1159 == 1'b1)) begin
        if ((or_cond_5_i_i_reg_1390 == 1'd0)) begin
            ap_phi_precharge_reg_pp0_iter0_pix_val_V_1_7_i_i_reg_438 <= ap_phi_precharge_reg_pp0_iter0_pix_val_V_1_6_i_i_reg_405;
        end else if ((1'd1 == or_cond_5_i_i_reg_1390)) begin
            ap_phi_precharge_reg_pp0_iter0_pix_val_V_1_7_i_i_reg_438 <= StrmMPix_V_val_1_V_dout;
        end
    end
end

always @ (posedge ap_clk) begin
    if ((ap_condition_1138 == 1'b1)) begin
        if ((or_cond_i_i_reg_1268 == 1'd0)) begin
            ap_phi_precharge_reg_pp0_iter0_pix_val_V_2_2_i_i_reg_265 <= tmp_val_2_V_fu_182;
        end else if ((1'd1 == or_cond_i_i_reg_1268)) begin
            ap_phi_precharge_reg_pp0_iter0_pix_val_V_2_2_i_i_reg_265 <= StrmMPix_V_val_2_V_dout;
        end
    end
end

always @ (posedge ap_clk) begin
    if ((ap_condition_1143 == 1'b1)) begin
        if ((or_cond_1_i_i_reg_1314 == 1'd0)) begin
            ap_phi_precharge_reg_pp0_iter0_pix_val_V_2_3_i_i_reg_295 <= ap_phi_precharge_reg_pp0_iter0_pix_val_V_2_2_i_i_reg_265;
        end else if ((1'd1 == or_cond_1_i_i_reg_1314)) begin
            ap_phi_precharge_reg_pp0_iter0_pix_val_V_2_3_i_i_reg_295 <= StrmMPix_V_val_2_V_dout;
        end
    end
end

always @ (posedge ap_clk) begin
    if ((ap_condition_1147 == 1'b1)) begin
        if ((or_cond_2_i_i_reg_1333 == 1'd0)) begin
            ap_phi_precharge_reg_pp0_iter0_pix_val_V_2_4_i_i_reg_328 <= ap_phi_precharge_reg_pp0_iter0_pix_val_V_2_3_i_i_reg_295;
        end else if ((1'd1 == or_cond_2_i_i_reg_1333)) begin
            ap_phi_precharge_reg_pp0_iter0_pix_val_V_2_4_i_i_reg_328 <= StrmMPix_V_val_2_V_dout;
        end
    end
end

always @ (posedge ap_clk) begin
    if ((ap_condition_1151 == 1'b1)) begin
        if ((or_cond_3_i_i_reg_1352 == 1'd0)) begin
            ap_phi_precharge_reg_pp0_iter0_pix_val_V_2_5_i_i_reg_361 <= ap_phi_precharge_reg_pp0_iter0_pix_val_V_2_4_i_i_reg_328;
        end else if ((1'd1 == or_cond_3_i_i_reg_1352)) begin
            ap_phi_precharge_reg_pp0_iter0_pix_val_V_2_5_i_i_reg_361 <= StrmMPix_V_val_2_V_dout;
        end
    end
end

always @ (posedge ap_clk) begin
    if ((ap_condition_1155 == 1'b1)) begin
        if ((or_cond_4_i_i_reg_1371 == 1'd0)) begin
            ap_phi_precharge_reg_pp0_iter0_pix_val_V_2_6_i_i_reg_394 <= ap_phi_precharge_reg_pp0_iter0_pix_val_V_2_5_i_i_reg_361;
        end else if ((1'd1 == or_cond_4_i_i_reg_1371)) begin
            ap_phi_precharge_reg_pp0_iter0_pix_val_V_2_6_i_i_reg_394 <= StrmMPix_V_val_2_V_dout;
        end
    end
end

always @ (posedge ap_clk) begin
    if ((ap_condition_1159 == 1'b1)) begin
        if ((or_cond_5_i_i_reg_1390 == 1'd0)) begin
            ap_phi_precharge_reg_pp0_iter0_pix_val_V_2_7_i_i_reg_427 <= ap_phi_precharge_reg_pp0_iter0_pix_val_V_2_6_i_i_reg_394;
        end else if ((1'd1 == or_cond_5_i_i_reg_1390)) begin
            ap_phi_precharge_reg_pp0_iter0_pix_val_V_2_7_i_i_reg_427 <= StrmMPix_V_val_2_V_dout;
        end
    end
end

always @ (posedge ap_clk) begin
    if ((ap_condition_515 == 1'b1)) begin
        if (((tmp_13_i_i_reg_1248 == 1'd1) & (or_cond_6_i_i_reg_1394 == 1'd0))) begin
            ap_phi_precharge_reg_pp0_iter1_pix_val_V_0_8_i_i_reg_480 <= ap_phi_precharge_reg_pp0_iter0_pix_val_V_0_7_i_i_reg_449;
        end else if (((tmp_13_i_i_reg_1248 == 1'd1) & (1'd1 == or_cond_6_i_i_reg_1394))) begin
            ap_phi_precharge_reg_pp0_iter1_pix_val_V_0_8_i_i_reg_480 <= StrmMPix_V_val_0_V_dout;
        end else if ((1'b1 == 1'b1)) begin
            ap_phi_precharge_reg_pp0_iter1_pix_val_V_0_8_i_i_reg_480 <= ap_phi_precharge_reg_pp0_iter0_pix_val_V_0_8_i_i_reg_480;
        end
    end
end

always @ (posedge ap_clk) begin
    if ((ap_condition_515 == 1'b1)) begin
        if (((tmp_13_i_i_reg_1248 == 1'd1) & (or_cond_6_i_i_reg_1394 == 1'd0))) begin
            ap_phi_precharge_reg_pp0_iter1_pix_val_V_1_8_i_i_reg_470 <= ap_phi_precharge_reg_pp0_iter0_pix_val_V_1_7_i_i_reg_438;
        end else if (((tmp_13_i_i_reg_1248 == 1'd1) & (1'd1 == or_cond_6_i_i_reg_1394))) begin
            ap_phi_precharge_reg_pp0_iter1_pix_val_V_1_8_i_i_reg_470 <= StrmMPix_V_val_1_V_dout;
        end else if ((1'b1 == 1'b1)) begin
            ap_phi_precharge_reg_pp0_iter1_pix_val_V_1_8_i_i_reg_470 <= ap_phi_precharge_reg_pp0_iter0_pix_val_V_1_8_i_i_reg_470;
        end
    end
end

always @ (posedge ap_clk) begin
    if ((ap_condition_515 == 1'b1)) begin
        if (((tmp_13_i_i_reg_1248 == 1'd1) & (or_cond_6_i_i_reg_1394 == 1'd0))) begin
            ap_phi_precharge_reg_pp0_iter1_pix_val_V_2_8_i_i_reg_460 <= ap_phi_precharge_reg_pp0_iter0_pix_val_V_2_7_i_i_reg_427;
        end else if (((tmp_13_i_i_reg_1248 == 1'd1) & (1'd1 == or_cond_6_i_i_reg_1394))) begin
            ap_phi_precharge_reg_pp0_iter1_pix_val_V_2_8_i_i_reg_460 <= StrmMPix_V_val_2_V_dout;
        end else if ((1'b1 == 1'b1)) begin
            ap_phi_precharge_reg_pp0_iter1_pix_val_V_2_8_i_i_reg_460 <= ap_phi_precharge_reg_pp0_iter0_pix_val_V_2_8_i_i_reg_460;
        end
    end
end

always @ (posedge ap_clk) begin
    if (((tmp_13_i_i_reg_1248 == 1'd1) & (1'b1 == ap_CS_fsm_pp0_stage0) & (1'b1 == ap_enable_reg_pp0_iter1) & (ap_block_pp0_stage0_flag00011001 == 1'b0))) begin
        x_i_i_reg_254 <= x_reg_1252;
    end else if (((icmp_fu_555_p2 == 1'd0) & (icmp1_fu_577_p2 == 1'd0) & (1'd0 == tmp_i_i_fu_583_p2) & (1'd0 == icmp2_fu_605_p2) & (1'd0 == icmp3_fu_627_p2) & (1'd1 == icmp4_fu_649_p2) & (1'b1 == ap_CS_fsm_state3) & (1'd0 == exitcond1_i_i_fu_880_p2))) begin
        x_i_i_reg_254 <= 8'd0;
    end
end

always @ (posedge ap_clk) begin
    if ((1'b1 == ap_CS_fsm_state13)) begin
        y_i_i_reg_243 <= y_reg_1243;
    end else if ((1'b1 == ap_CS_fsm_state2)) begin
        y_i_i_reg_243 <= 16'd0;
    end
end

always @ (posedge ap_clk) begin
    if (((1'b1 == ap_CS_fsm_state1) & ~((1'b0 == ap_start) | (ap_done_reg == 1'b1) | (1'b0 == HwReg_height_cast8_loc_empty_n) | (1'b0 == tmp_3_loc_empty_n) | (1'b0 == HwReg_height_cast8_loc_out_full_n) | (1'b0 == tmp_3_loc_out_full_n) | (1'b0 == HwReg_width_cast9_loc_empty_n)))) begin
        HwReg_height_cast8_l_reg_1103 <= HwReg_height_cast8_loc_dout;
    end
end

always @ (posedge ap_clk) begin
    if (((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_CS_fsm_pp0_stage7) & (ap_block_pp0_stage7_flag00011001 == 1'b0))) begin
        ap_phi_precharge_reg_pp0_iter1_pix_val_V_0_9_i_i_reg_510 <= ap_phi_precharge_reg_pp0_iter0_pix_val_V_0_9_i_i_reg_510;
        ap_phi_precharge_reg_pp0_iter1_pix_val_V_1_9_i_i_reg_500 <= ap_phi_precharge_reg_pp0_iter0_pix_val_V_1_9_i_i_reg_500;
        ap_phi_precharge_reg_pp0_iter1_pix_val_V_2_9_i_i_reg_490 <= ap_phi_precharge_reg_pp0_iter0_pix_val_V_2_9_i_i_reg_490;
        pix_val_V_1_7_i_i_reg_438 <= ap_phi_precharge_reg_pp0_iter0_pix_val_V_1_7_i_i_reg_438;
        pix_val_V_2_7_i_i_reg_427 <= ap_phi_precharge_reg_pp0_iter0_pix_val_V_2_7_i_i_reg_427;
    end
end

always @ (posedge ap_clk) begin
    if ((1'b1 == ap_CS_fsm_state2)) begin
        icmp5_reg_1194 <= icmp5_fu_802_p2;
        icmp6_reg_1204 <= icmp6_fu_824_p2;
        icmp7_reg_1229 <= icmp7_fu_864_p2;
        loopWidth_cast_i_i_c_reg_1169 <= {{mul_fu_693_p2[20:12]}};
        tmp_11_cast_i_i_reg_1179[8 : 0] <= tmp_11_cast_i_i_fu_777_p1[8 : 0];
        tmp_12_i_i_reg_1184 <= tmp_12_i_i_fu_780_p2;
        tmp_24_2_i_i_reg_1199 <= tmp_24_2_i_i_fu_808_p2;
        tmp_24_4_i_i_reg_1209 <= tmp_24_4_i_i_fu_830_p2;
        tmp_24_5_i_i_reg_1214 <= tmp_24_5_i_i_fu_836_p2;
        tmp_24_6_i_i_reg_1219 <= tmp_24_6_i_i_fu_842_p2;
        tmp_24_i_i_reg_1189 <= tmp_24_i_i_fu_786_p2;
        tmp_25_2_i_i_reg_1234 <= tmp_25_2_i_i_fu_870_p2;
        tmp_25_i_i_reg_1224 <= tmp_25_i_i_fu_848_p2;
        tmp_7_i_i_reg_1174 <= tmp_7_i_i_fu_712_p2;
    end
end

always @ (posedge ap_clk) begin
    if (((1'b1 == ap_CS_fsm_pp0_stage0) & (ap_block_pp0_stage0_flag00011001 == 1'b0) & (1'd1 == tmp_13_i_i_fu_895_p2))) begin
        or_cond1_1_i_i_reg_1276 <= or_cond1_1_i_i_fu_921_p2;
        or_cond1_2_i_i_reg_1280 <= or_cond1_2_i_i_fu_926_p2;
        or_cond1_i_i_reg_1272 <= or_cond1_i_i_fu_916_p2;
        or_cond_i_i_reg_1268 <= or_cond_i_i_fu_911_p2;
        tmp_14_i_i_reg_1257 <= tmp_14_i_i_fu_906_p2;
    end
end

always @ (posedge ap_clk) begin
    if (((1'b1 == ap_CS_fsm_pp0_stage1) & (tmp_13_i_i_reg_1248 == 1'd1) & (ap_block_pp0_stage1_flag00011001 == 1'b0))) begin
        or_cond_1_i_i_reg_1314 <= or_cond_1_i_i_fu_940_p2;
    end
end

always @ (posedge ap_clk) begin
    if (((tmp_13_i_i_reg_1248 == 1'd1) & (1'b1 == ap_CS_fsm_pp0_stage2) & (ap_block_pp0_stage2_flag00011001 == 1'b0))) begin
        or_cond_2_i_i_reg_1333 <= or_cond_2_i_i_fu_944_p2;
    end
end

always @ (posedge ap_clk) begin
    if (((tmp_13_i_i_reg_1248 == 1'd1) & (1'b1 == ap_CS_fsm_pp0_stage3) & (ap_block_pp0_stage3_flag00011001 == 1'b0))) begin
        or_cond_3_i_i_reg_1352 <= or_cond_3_i_i_fu_948_p2;
    end
end

always @ (posedge ap_clk) begin
    if (((tmp_13_i_i_reg_1248 == 1'd1) & (1'b1 == ap_CS_fsm_pp0_stage4) & (ap_block_pp0_stage4_flag00011001 == 1'b0))) begin
        or_cond_4_i_i_reg_1371 <= or_cond_4_i_i_fu_952_p2;
    end
end

always @ (posedge ap_clk) begin
    if (((tmp_13_i_i_reg_1248 == 1'd1) & (1'b1 == ap_CS_fsm_pp0_stage5) & (ap_block_pp0_stage5_flag00011001 == 1'b0))) begin
        or_cond_5_i_i_reg_1390 <= or_cond_5_i_i_fu_977_p2;
        or_cond_6_i_i_reg_1394 <= or_cond_6_i_i_fu_981_p2;
        or_cond_7_i_i_reg_1398 <= or_cond_7_i_i_fu_985_p2;
    end
end

always @ (posedge ap_clk) begin
    if (((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_CS_fsm_pp0_stage2) & (ap_block_pp0_stage2_flag00011001 == 1'b0))) begin
        pix_val_V_0_2_i_i_reg_285 <= ap_phi_precharge_reg_pp0_iter0_pix_val_V_0_2_i_i_reg_285;
        pix_val_V_1_2_i_i_reg_275 <= ap_phi_precharge_reg_pp0_iter0_pix_val_V_1_2_i_i_reg_275;
        pix_val_V_2_2_i_i_reg_265 <= ap_phi_precharge_reg_pp0_iter0_pix_val_V_2_2_i_i_reg_265;
    end
end

always @ (posedge ap_clk) begin
    if (((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_CS_fsm_pp0_stage3) & (ap_block_pp0_stage3_flag00011001 == 1'b0))) begin
        pix_val_V_0_3_i_i_reg_317 <= ap_phi_precharge_reg_pp0_iter0_pix_val_V_0_3_i_i_reg_317;
        pix_val_V_1_3_i_i_reg_306 <= ap_phi_precharge_reg_pp0_iter0_pix_val_V_1_3_i_i_reg_306;
        pix_val_V_2_3_i_i_reg_295 <= ap_phi_precharge_reg_pp0_iter0_pix_val_V_2_3_i_i_reg_295;
    end
end

always @ (posedge ap_clk) begin
    if (((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_CS_fsm_pp0_stage5) & (ap_block_pp0_stage5_flag00011001 == 1'b0))) begin
        pix_val_V_0_5_i_i_reg_383 <= ap_phi_precharge_reg_pp0_iter0_pix_val_V_0_5_i_i_reg_383;
        pix_val_V_1_5_i_i_reg_372 <= ap_phi_precharge_reg_pp0_iter0_pix_val_V_1_5_i_i_reg_372;
        pix_val_V_2_5_i_i_reg_361 <= ap_phi_precharge_reg_pp0_iter0_pix_val_V_2_5_i_i_reg_361;
    end
end

always @ (posedge ap_clk) begin
    if (((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_CS_fsm_pp0_stage6) & (ap_block_pp0_stage6_flag00011001 == 1'b0))) begin
        pix_val_V_0_6_i_i_reg_416 <= ap_phi_precharge_reg_pp0_iter0_pix_val_V_0_6_i_i_reg_416;
        pix_val_V_1_6_i_i_reg_405 <= ap_phi_precharge_reg_pp0_iter0_pix_val_V_1_6_i_i_reg_405;
        pix_val_V_2_6_i_i_reg_394 <= ap_phi_precharge_reg_pp0_iter0_pix_val_V_2_6_i_i_reg_394;
    end
end

always @ (posedge ap_clk) begin
    if (((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_CS_fsm_pp0_stage4) & (ap_block_pp0_stage4_flag00011001 == 1'b0))) begin
        pix_val_V_2_4_i_i_reg_328 <= ap_phi_precharge_reg_pp0_iter0_pix_val_V_2_4_i_i_reg_328;
    end
end

always @ (posedge ap_clk) begin
    if (((1'b1 == ap_CS_fsm_state1) & ~((1'b0 == ap_start) | (ap_done_reg == 1'b1) | (1'b0 == HwReg_height_cast8_loc_empty_n) | (1'b0 == tmp_3_loc_empty_n) | (1'b0 == HwReg_height_cast8_loc_out_full_n) | (1'b0 == tmp_3_loc_out_full_n) | (1'b0 == HwReg_width_cast9_loc_empty_n)) & (icmp_fu_555_p2 == 1'd0) & (icmp1_fu_577_p2 == 1'd0) & (1'd0 == tmp_i_i_fu_583_p2) & (1'd0 == icmp2_fu_605_p2) & (1'd0 == icmp3_fu_627_p2) & (1'd1 == icmp4_fu_649_p2))) begin
        remPix_reg_1161 <= remPix_fu_681_p1;
        tmp_6_i_i_reg_1156 <= tmp_6_i_i_fu_675_p2;
    end
end

always @ (posedge ap_clk) begin
    if (((1'b1 == ap_CS_fsm_pp0_stage0) & (ap_block_pp0_stage0_flag00011001 == 1'b0))) begin
        tmp_13_i_i_reg_1248 <= tmp_13_i_i_fu_895_p2;
    end
end

always @ (posedge ap_clk) begin
    if (((tmp_13_i_i_reg_1248 == 1'd1) & (1'b1 == ap_CS_fsm_pp0_stage0) & (1'b1 == ap_enable_reg_pp0_iter1) & (ap_block_pp0_stage0_flag00011001 == 1'b0))) begin
        tmp_val_0_V_fu_174 <= pix_val_V_0_9_i_i_phi_fu_513_p4;
        tmp_val_1_V_fu_178 <= pix_val_V_1_9_i_i_phi_fu_503_p4;
        tmp_val_2_V_fu_182 <= pix_val_V_2_9_i_i_phi_fu_493_p4;
    end
end

always @ (posedge ap_clk) begin
    if (((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_CS_fsm_pp0_stage0) & (ap_block_pp0_stage0_flag00011001 == 1'b0))) begin
        x_reg_1252 <= x_fu_900_p2;
    end
end

always @ (posedge ap_clk) begin
    if (((icmp_fu_555_p2 == 1'd0) & (icmp1_fu_577_p2 == 1'd0) & (1'd0 == tmp_i_i_fu_583_p2) & (1'd0 == icmp2_fu_605_p2) & (1'd0 == icmp3_fu_627_p2) & (1'd1 == icmp4_fu_649_p2) & (1'b1 == ap_CS_fsm_state3))) begin
        y_reg_1243 <= y_fu_885_p2;
    end
end

always @ (*) begin
    if (((1'b1 == ap_CS_fsm_state1) & ~((1'b0 == ap_start) | (ap_done_reg == 1'b1)))) begin
        HwReg_height_cast8_loc_blk_n = HwReg_height_cast8_loc_empty_n;
    end else begin
        HwReg_height_cast8_loc_blk_n = 1'b1;
    end
end

always @ (*) begin
    if (((1'b1 == ap_CS_fsm_state1) & ~((1'b0 == ap_start) | (ap_done_reg == 1'b1)))) begin
        HwReg_height_cast8_loc_out_blk_n = HwReg_height_cast8_loc_out_full_n;
    end else begin
        HwReg_height_cast8_loc_out_blk_n = 1'b1;
    end
end

always @ (*) begin
    if (((1'b1 == ap_CS_fsm_state1) & ~((1'b0 == ap_start) | (ap_done_reg == 1'b1) | (1'b0 == HwReg_height_cast8_loc_empty_n) | (1'b0 == tmp_3_loc_empty_n) | (1'b0 == HwReg_height_cast8_loc_out_full_n) | (1'b0 == tmp_3_loc_out_full_n) | (1'b0 == HwReg_width_cast9_loc_empty_n)))) begin
        HwReg_height_cast8_loc_out_write = 1'b1;
    end else begin
        HwReg_height_cast8_loc_out_write = 1'b0;
    end
end

always @ (*) begin
    if (((1'b1 == ap_CS_fsm_state1) & ~((1'b0 == ap_start) | (ap_done_reg == 1'b1) | (1'b0 == HwReg_height_cast8_loc_empty_n) | (1'b0 == tmp_3_loc_empty_n) | (1'b0 == HwReg_height_cast8_loc_out_full_n) | (1'b0 == tmp_3_loc_out_full_n) | (1'b0 == HwReg_width_cast9_loc_empty_n)))) begin
        HwReg_height_cast8_loc_read = 1'b1;
    end else begin
        HwReg_height_cast8_loc_read = 1'b0;
    end
end

always @ (*) begin
    if (((1'b1 == ap_CS_fsm_state1) & ~((1'b0 == ap_start) | (ap_done_reg == 1'b1)))) begin
        HwReg_width_cast9_loc_blk_n = HwReg_width_cast9_loc_empty_n;
    end else begin
        HwReg_width_cast9_loc_blk_n = 1'b1;
    end
end

always @ (*) begin
    if (((1'b1 == ap_CS_fsm_state1) & ~((1'b0 == ap_start) | (ap_done_reg == 1'b1) | (1'b0 == HwReg_height_cast8_loc_empty_n) | (1'b0 == tmp_3_loc_empty_n) | (1'b0 == HwReg_height_cast8_loc_out_full_n) | (1'b0 == tmp_3_loc_out_full_n) | (1'b0 == HwReg_width_cast9_loc_empty_n)))) begin
        HwReg_width_cast9_loc_read = 1'b1;
    end else begin
        HwReg_width_cast9_loc_read = 1'b0;
    end
end

always @ (*) begin
    if ((((1'b1 == ap_CS_fsm_pp0_stage1) & (1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_predicate_op129_read_state5) & (ap_block_pp0_stage1_flag00011001 == 1'b0)) | ((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_CS_fsm_pp0_stage2) & (1'b1 == ap_predicate_op139_read_state6) & (ap_block_pp0_stage2_flag00011001 == 1'b0)) | ((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_CS_fsm_pp0_stage3) & (1'b1 == ap_predicate_op149_read_state7) & (ap_block_pp0_stage3_flag00011001 == 1'b0)) | ((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_CS_fsm_pp0_stage4) & (1'b1 == ap_predicate_op159_read_state8) & (ap_block_pp0_stage4_flag00011001 == 1'b0)) | ((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_CS_fsm_pp0_stage5) & (1'b1 == ap_predicate_op172_read_state9) & (ap_block_pp0_stage5_flag00011001 == 1'b0)) | ((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_CS_fsm_pp0_stage6) & (1'b1 == ap_predicate_op184_read_state10) & (ap_block_pp0_stage6_flag00011001 == 1'b0)) | ((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_CS_fsm_pp0_stage7) & (1'b1 == ap_predicate_op193_read_state11) & (ap_block_pp0_stage7_flag00011001 == 1'b0)) | ((1'b1 == ap_CS_fsm_pp0_stage0) & (1'b1 == ap_enable_reg_pp0_iter1) & (1'b1 == ap_predicate_op205_read_state12) & (ap_block_pp0_stage0_flag00011001 == 1'b0)))) begin
        StrmMPix_V_val_0_V0_update = 1'b1;
    end else begin
        StrmMPix_V_val_0_V0_update = 1'b0;
    end
end

always @ (*) begin
    if ((((1'b1 == ap_CS_fsm_pp0_stage1) & (1'b1 == ap_enable_reg_pp0_iter0) & (ap_block_pp0_stage1_flag00000000 == 1'b0) & (tmp_13_i_i_reg_1248 == 1'd1) & (1'd1 == or_cond_i_i_reg_1268)) | ((1'b1 == ap_enable_reg_pp0_iter0) & (tmp_13_i_i_reg_1248 == 1'd1) & (1'b1 == ap_CS_fsm_pp0_stage2) & (ap_block_pp0_stage2_flag00000000 == 1'b0) & (1'd1 == or_cond_1_i_i_reg_1314)) | ((1'b1 == ap_enable_reg_pp0_iter0) & (tmp_13_i_i_reg_1248 == 1'd1) & (1'b1 == ap_CS_fsm_pp0_stage3) & (ap_block_pp0_stage3_flag00000000 == 1'b0) & (1'd1 == or_cond_2_i_i_reg_1333)) | ((1'b1 == ap_enable_reg_pp0_iter0) & (tmp_13_i_i_reg_1248 == 1'd1) & (1'b1 == ap_CS_fsm_pp0_stage4) & (ap_block_pp0_stage4_flag00000000 == 1'b0) & (1'd1 == or_cond_3_i_i_reg_1352)) | ((1'b1 == ap_enable_reg_pp0_iter0) & (tmp_13_i_i_reg_1248 == 1'd1) & (1'b1 == ap_CS_fsm_pp0_stage5) & (ap_block_pp0_stage5_flag00000000 == 1'b0) & (1'd1 == or_cond_4_i_i_reg_1371)) | ((1'b1 == ap_enable_reg_pp0_iter0) & (tmp_13_i_i_reg_1248 == 1'd1) & (1'b1 == ap_CS_fsm_pp0_stage6) & (ap_block_pp0_stage6_flag00000000 == 1'b0) & (1'd1 == or_cond_5_i_i_reg_1390)) | ((1'b1 == ap_enable_reg_pp0_iter0) & (tmp_13_i_i_reg_1248 == 1'd1) & (1'b1 == ap_CS_fsm_pp0_stage7) & (ap_block_pp0_stage7_flag00000000 == 1'b0) & (1'd1 == or_cond_6_i_i_reg_1394)) | ((tmp_13_i_i_reg_1248 == 1'd1) & (1'b1 == ap_CS_fsm_pp0_stage0) & (1'b1 == ap_enable_reg_pp0_iter1) & (ap_block_pp0_stage0_flag00000000 == 1'b0) & (1'd1 == or_cond_7_i_i_reg_1398)))) begin
        StrmMPix_V_val_0_V_blk_n = StrmMPix_V_val_0_V_empty_n;
    end else begin
        StrmMPix_V_val_0_V_blk_n = 1'b1;
    end
end

always @ (*) begin
    if ((((1'b1 == ap_CS_fsm_pp0_stage1) & (1'b1 == ap_enable_reg_pp0_iter0) & (ap_block_pp0_stage1_flag00000000 == 1'b0) & (tmp_13_i_i_reg_1248 == 1'd1) & (1'd1 == or_cond_i_i_reg_1268)) | ((1'b1 == ap_enable_reg_pp0_iter0) & (tmp_13_i_i_reg_1248 == 1'd1) & (1'b1 == ap_CS_fsm_pp0_stage2) & (ap_block_pp0_stage2_flag00000000 == 1'b0) & (1'd1 == or_cond_1_i_i_reg_1314)) | ((1'b1 == ap_enable_reg_pp0_iter0) & (tmp_13_i_i_reg_1248 == 1'd1) & (1'b1 == ap_CS_fsm_pp0_stage3) & (ap_block_pp0_stage3_flag00000000 == 1'b0) & (1'd1 == or_cond_2_i_i_reg_1333)) | ((1'b1 == ap_enable_reg_pp0_iter0) & (tmp_13_i_i_reg_1248 == 1'd1) & (1'b1 == ap_CS_fsm_pp0_stage4) & (ap_block_pp0_stage4_flag00000000 == 1'b0) & (1'd1 == or_cond_3_i_i_reg_1352)) | ((1'b1 == ap_enable_reg_pp0_iter0) & (tmp_13_i_i_reg_1248 == 1'd1) & (1'b1 == ap_CS_fsm_pp0_stage5) & (ap_block_pp0_stage5_flag00000000 == 1'b0) & (1'd1 == or_cond_4_i_i_reg_1371)) | ((1'b1 == ap_enable_reg_pp0_iter0) & (tmp_13_i_i_reg_1248 == 1'd1) & (1'b1 == ap_CS_fsm_pp0_stage6) & (ap_block_pp0_stage6_flag00000000 == 1'b0) & (1'd1 == or_cond_5_i_i_reg_1390)) | ((1'b1 == ap_enable_reg_pp0_iter0) & (tmp_13_i_i_reg_1248 == 1'd1) & (1'b1 == ap_CS_fsm_pp0_stage7) & (ap_block_pp0_stage7_flag00000000 == 1'b0) & (1'd1 == or_cond_6_i_i_reg_1394)) | ((tmp_13_i_i_reg_1248 == 1'd1) & (1'b1 == ap_CS_fsm_pp0_stage0) & (1'b1 == ap_enable_reg_pp0_iter1) & (ap_block_pp0_stage0_flag00000000 == 1'b0) & (1'd1 == or_cond_7_i_i_reg_1398)))) begin
        StrmMPix_V_val_1_V_blk_n = StrmMPix_V_val_1_V_empty_n;
    end else begin
        StrmMPix_V_val_1_V_blk_n = 1'b1;
    end
end

always @ (*) begin
    if ((((1'b1 == ap_CS_fsm_pp0_stage1) & (1'b1 == ap_enable_reg_pp0_iter0) & (ap_block_pp0_stage1_flag00000000 == 1'b0) & (tmp_13_i_i_reg_1248 == 1'd1) & (1'd1 == or_cond_i_i_reg_1268)) | ((1'b1 == ap_enable_reg_pp0_iter0) & (tmp_13_i_i_reg_1248 == 1'd1) & (1'b1 == ap_CS_fsm_pp0_stage2) & (ap_block_pp0_stage2_flag00000000 == 1'b0) & (1'd1 == or_cond_1_i_i_reg_1314)) | ((1'b1 == ap_enable_reg_pp0_iter0) & (tmp_13_i_i_reg_1248 == 1'd1) & (1'b1 == ap_CS_fsm_pp0_stage3) & (ap_block_pp0_stage3_flag00000000 == 1'b0) & (1'd1 == or_cond_2_i_i_reg_1333)) | ((1'b1 == ap_enable_reg_pp0_iter0) & (tmp_13_i_i_reg_1248 == 1'd1) & (1'b1 == ap_CS_fsm_pp0_stage4) & (ap_block_pp0_stage4_flag00000000 == 1'b0) & (1'd1 == or_cond_3_i_i_reg_1352)) | ((1'b1 == ap_enable_reg_pp0_iter0) & (tmp_13_i_i_reg_1248 == 1'd1) & (1'b1 == ap_CS_fsm_pp0_stage5) & (ap_block_pp0_stage5_flag00000000 == 1'b0) & (1'd1 == or_cond_4_i_i_reg_1371)) | ((1'b1 == ap_enable_reg_pp0_iter0) & (tmp_13_i_i_reg_1248 == 1'd1) & (1'b1 == ap_CS_fsm_pp0_stage6) & (ap_block_pp0_stage6_flag00000000 == 1'b0) & (1'd1 == or_cond_5_i_i_reg_1390)) | ((1'b1 == ap_enable_reg_pp0_iter0) & (tmp_13_i_i_reg_1248 == 1'd1) & (1'b1 == ap_CS_fsm_pp0_stage7) & (ap_block_pp0_stage7_flag00000000 == 1'b0) & (1'd1 == or_cond_6_i_i_reg_1394)) | ((tmp_13_i_i_reg_1248 == 1'd1) & (1'b1 == ap_CS_fsm_pp0_stage0) & (1'b1 == ap_enable_reg_pp0_iter1) & (ap_block_pp0_stage0_flag00000000 == 1'b0) & (1'd1 == or_cond_7_i_i_reg_1398)))) begin
        StrmMPix_V_val_2_V_blk_n = StrmMPix_V_val_2_V_empty_n;
    end else begin
        StrmMPix_V_val_2_V_blk_n = 1'b1;
    end
end

always @ (*) begin
    if ((tmp_13_i_i_reg_1248 == 1'd0)) begin
        ap_condition_pp0_exit_iter0_state5 = 1'b1;
    end else begin
        ap_condition_pp0_exit_iter0_state5 = 1'b0;
    end
end

always @ (*) begin
    if (((1'b1 == ap_CS_fsm_state3) & ((1'd1 == icmp_fu_555_p2) | (1'd1 == icmp1_fu_577_p2) | (1'd1 == tmp_i_i_fu_583_p2) | (1'd1 == icmp2_fu_605_p2) | (1'd1 == icmp3_fu_627_p2) | (1'd0 == icmp4_fu_649_p2) | (1'd1 == exitcond1_i_i_fu_880_p2)))) begin
        ap_done = 1'b1;
    end else begin
        ap_done = ap_done_reg;
    end
end

always @ (*) begin
    if (((1'b0 == ap_start) & (1'b1 == ap_CS_fsm_state1))) begin
        ap_idle = 1'b1;
    end else begin
        ap_idle = 1'b0;
    end
end

always @ (*) begin
    if (((1'b0 == ap_enable_reg_pp0_iter0) & (1'b0 == ap_enable_reg_pp0_iter1))) begin
        ap_idle_pp0 = 1'b1;
    end else begin
        ap_idle_pp0 = 1'b0;
    end
end

always @ (*) begin
    if (((1'b1 == ap_CS_fsm_state3) & ((1'd1 == icmp_fu_555_p2) | (1'd1 == icmp1_fu_577_p2) | (1'd1 == tmp_i_i_fu_583_p2) | (1'd1 == icmp2_fu_605_p2) | (1'd1 == icmp3_fu_627_p2) | (1'd0 == icmp4_fu_649_p2) | (1'd1 == exitcond1_i_i_fu_880_p2)))) begin
        ap_ready = 1'b1;
    end else begin
        ap_ready = 1'b0;
    end
end

always @ (*) begin
    if ((((1'b1 == ap_enable_reg_pp0_iter0) & (tmp_13_i_i_reg_1248 == 1'd1) & (1'b1 == ap_CS_fsm_pp0_stage4) & (ap_block_pp0_stage4_flag00000000 == 1'b0) & (1'd1 == or_cond1_i_i_reg_1272)) | ((1'b1 == ap_enable_reg_pp0_iter0) & (tmp_13_i_i_reg_1248 == 1'd1) & (1'b1 == ap_CS_fsm_pp0_stage7) & (ap_block_pp0_stage7_flag00000000 == 1'b0) & (1'd1 == or_cond1_1_i_i_reg_1276)) | ((1'b1 == ap_CS_fsm_pp0_stage0) & (1'b1 == ap_enable_reg_pp0_iter1) & (ap_block_pp0_stage0_flag00000000 == 1'b0) & (1'd1 == or_cond1_2_i_i_reg_1280)))) begin
        bytes_plane0_V_V_blk_n = bytes_plane0_V_V_full_n;
    end else begin
        bytes_plane0_V_V_blk_n = 1'b1;
    end
end

always @ (*) begin
    if (((1'b1 == ap_CS_fsm_pp0_stage0) & (1'b1 == ap_enable_reg_pp0_iter1) & (1'd1 == or_cond1_2_i_i_reg_1280) & (ap_block_pp0_stage0_flag00001001 == 1'b0))) begin
        bytes_plane0_V_V_din = tmp_V_2_fu_1062_p9;
    end else if (((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_CS_fsm_pp0_stage7) & (1'b1 == ap_predicate_op199_write_state11) & (ap_block_pp0_stage7_flag00001001 == 1'b0))) begin
        bytes_plane0_V_V_din = tmp_V_1_fu_989_p9;
    end else if (((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_CS_fsm_pp0_stage4) & (1'b1 == ap_predicate_op166_write_state8) & (ap_block_pp0_stage4_flag00001001 == 1'b0))) begin
        bytes_plane0_V_V_din = tmp_V_fu_956_p9;
    end else begin
        bytes_plane0_V_V_din = 'bx;
    end
end

always @ (*) begin
    if ((((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_CS_fsm_pp0_stage4) & (1'b1 == ap_predicate_op166_write_state8) & (ap_block_pp0_stage4_flag00011001 == 1'b0)) | ((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_CS_fsm_pp0_stage7) & (1'b1 == ap_predicate_op199_write_state11) & (ap_block_pp0_stage7_flag00011001 == 1'b0)) | ((1'b1 == ap_CS_fsm_pp0_stage0) & (1'b1 == ap_enable_reg_pp0_iter1) & (1'd1 == or_cond1_2_i_i_reg_1280) & (ap_block_pp0_stage0_flag00011001 == 1'b0)))) begin
        bytes_plane0_V_V_write = 1'b1;
    end else begin
        bytes_plane0_V_V_write = 1'b0;
    end
end

always @ (*) begin
    if ((ap_condition_549 == 1'b1)) begin
        if ((or_cond_7_i_i_reg_1398 == 1'd0)) begin
            pix_val_V_0_9_i_i_phi_fu_513_p4 = ap_phi_precharge_reg_pp0_iter1_pix_val_V_0_8_i_i_reg_480;
        end else if ((1'd1 == or_cond_7_i_i_reg_1398)) begin
            pix_val_V_0_9_i_i_phi_fu_513_p4 = StrmMPix_V_val_0_V_dout;
        end else begin
            pix_val_V_0_9_i_i_phi_fu_513_p4 = ap_phi_precharge_reg_pp0_iter1_pix_val_V_0_9_i_i_reg_510;
        end
    end else begin
        pix_val_V_0_9_i_i_phi_fu_513_p4 = ap_phi_precharge_reg_pp0_iter1_pix_val_V_0_9_i_i_reg_510;
    end
end

always @ (*) begin
    if ((ap_condition_549 == 1'b1)) begin
        if ((or_cond_7_i_i_reg_1398 == 1'd0)) begin
            pix_val_V_1_9_i_i_phi_fu_503_p4 = ap_phi_precharge_reg_pp0_iter1_pix_val_V_1_8_i_i_reg_470;
        end else if ((1'd1 == or_cond_7_i_i_reg_1398)) begin
            pix_val_V_1_9_i_i_phi_fu_503_p4 = StrmMPix_V_val_1_V_dout;
        end else begin
            pix_val_V_1_9_i_i_phi_fu_503_p4 = ap_phi_precharge_reg_pp0_iter1_pix_val_V_1_9_i_i_reg_500;
        end
    end else begin
        pix_val_V_1_9_i_i_phi_fu_503_p4 = ap_phi_precharge_reg_pp0_iter1_pix_val_V_1_9_i_i_reg_500;
    end
end

always @ (*) begin
    if ((ap_condition_549 == 1'b1)) begin
        if ((or_cond_7_i_i_reg_1398 == 1'd0)) begin
            pix_val_V_2_9_i_i_phi_fu_493_p4 = ap_phi_precharge_reg_pp0_iter1_pix_val_V_2_8_i_i_reg_460;
        end else if ((1'd1 == or_cond_7_i_i_reg_1398)) begin
            pix_val_V_2_9_i_i_phi_fu_493_p4 = StrmMPix_V_val_2_V_dout;
        end else begin
            pix_val_V_2_9_i_i_phi_fu_493_p4 = ap_phi_precharge_reg_pp0_iter1_pix_val_V_2_9_i_i_reg_490;
        end
    end else begin
        pix_val_V_2_9_i_i_phi_fu_493_p4 = ap_phi_precharge_reg_pp0_iter1_pix_val_V_2_9_i_i_reg_490;
    end
end

always @ (*) begin
    if (((1'b1 == ap_CS_fsm_state1) & ~((1'b0 == ap_start) | (ap_done_reg == 1'b1)))) begin
        tmp_3_loc_blk_n = tmp_3_loc_empty_n;
    end else begin
        tmp_3_loc_blk_n = 1'b1;
    end
end

always @ (*) begin
    if (((1'b1 == ap_CS_fsm_state1) & ~((1'b0 == ap_start) | (ap_done_reg == 1'b1)))) begin
        tmp_3_loc_out_blk_n = tmp_3_loc_out_full_n;
    end else begin
        tmp_3_loc_out_blk_n = 1'b1;
    end
end

always @ (*) begin
    if (((1'b1 == ap_CS_fsm_state1) & ~((1'b0 == ap_start) | (ap_done_reg == 1'b1) | (1'b0 == HwReg_height_cast8_loc_empty_n) | (1'b0 == tmp_3_loc_empty_n) | (1'b0 == HwReg_height_cast8_loc_out_full_n) | (1'b0 == tmp_3_loc_out_full_n) | (1'b0 == HwReg_width_cast9_loc_empty_n)))) begin
        tmp_3_loc_out_write = 1'b1;
    end else begin
        tmp_3_loc_out_write = 1'b0;
    end
end

always @ (*) begin
    if (((1'b1 == ap_CS_fsm_state1) & ~((1'b0 == ap_start) | (ap_done_reg == 1'b1) | (1'b0 == HwReg_height_cast8_loc_empty_n) | (1'b0 == tmp_3_loc_empty_n) | (1'b0 == HwReg_height_cast8_loc_out_full_n) | (1'b0 == tmp_3_loc_out_full_n) | (1'b0 == HwReg_width_cast9_loc_empty_n)))) begin
        tmp_3_loc_read = 1'b1;
    end else begin
        tmp_3_loc_read = 1'b0;
    end
end

always @ (*) begin
    if (((tmp_13_i_i_reg_1248 == 1'd1) & (1'b1 == ap_CS_fsm_pp0_stage0) & (1'b1 == ap_enable_reg_pp0_iter1) & (ap_block_pp0_stage0_flag00000000 == 1'b0))) begin
        x_i_i_phi_fu_258_p4 = x_reg_1252;
    end else begin
        x_i_i_phi_fu_258_p4 = x_i_i_reg_254;
    end
end

always @ (*) begin
    case (ap_CS_fsm)
        ap_ST_fsm_state1 : begin
            if (((1'b1 == ap_CS_fsm_state1) & ~((1'b0 == ap_start) | (ap_done_reg == 1'b1) | (1'b0 == HwReg_height_cast8_loc_empty_n) | (1'b0 == tmp_3_loc_empty_n) | (1'b0 == HwReg_height_cast8_loc_out_full_n) | (1'b0 == tmp_3_loc_out_full_n) | (1'b0 == HwReg_width_cast9_loc_empty_n)) & (icmp_fu_555_p2 == 1'd0) & (icmp1_fu_577_p2 == 1'd0) & (1'd0 == tmp_i_i_fu_583_p2) & (1'd0 == icmp2_fu_605_p2) & (1'd0 == icmp3_fu_627_p2) & (1'd1 == icmp4_fu_649_p2))) begin
                ap_NS_fsm = ap_ST_fsm_state2;
            end else if (((1'b1 == ap_CS_fsm_state1) & ~((1'b0 == ap_start) | (ap_done_reg == 1'b1) | (1'b0 == HwReg_height_cast8_loc_empty_n) | (1'b0 == tmp_3_loc_empty_n) | (1'b0 == HwReg_height_cast8_loc_out_full_n) | (1'b0 == tmp_3_loc_out_full_n) | (1'b0 == HwReg_width_cast9_loc_empty_n)) & ((1'd1 == icmp_fu_555_p2) | (1'd1 == icmp1_fu_577_p2) | (1'd1 == tmp_i_i_fu_583_p2) | (1'd1 == icmp2_fu_605_p2) | (1'd1 == icmp3_fu_627_p2) | (1'd0 == icmp4_fu_649_p2)))) begin
                ap_NS_fsm = ap_ST_fsm_state3;
            end else begin
                ap_NS_fsm = ap_ST_fsm_state1;
            end
        end
        ap_ST_fsm_state2 : begin
            ap_NS_fsm = ap_ST_fsm_state3;
        end
        ap_ST_fsm_state3 : begin
            if (((1'b1 == ap_CS_fsm_state3) & ((1'd1 == icmp_fu_555_p2) | (1'd1 == icmp1_fu_577_p2) | (1'd1 == tmp_i_i_fu_583_p2) | (1'd1 == icmp2_fu_605_p2) | (1'd1 == icmp3_fu_627_p2) | (1'd0 == icmp4_fu_649_p2) | (1'd1 == exitcond1_i_i_fu_880_p2)))) begin
                ap_NS_fsm = ap_ST_fsm_state1;
            end else begin
                ap_NS_fsm = ap_ST_fsm_pp0_stage0;
            end
        end
        ap_ST_fsm_pp0_stage0 : begin
            if ((ap_block_pp0_stage0_flag00011011 == 1'b0)) begin
                ap_NS_fsm = ap_ST_fsm_pp0_stage1;
            end else begin
                ap_NS_fsm = ap_ST_fsm_pp0_stage0;
            end
        end
        ap_ST_fsm_pp0_stage1 : begin
            if (((ap_block_pp0_stage1_flag00011011 == 1'b0) & ~((1'b1 == ap_enable_reg_pp0_iter0) & (ap_block_pp0_stage1_flag00011011 == 1'b0) & (tmp_13_i_i_reg_1248 == 1'd0)))) begin
                ap_NS_fsm = ap_ST_fsm_pp0_stage2;
            end else if (((1'b1 == ap_enable_reg_pp0_iter0) & (ap_block_pp0_stage1_flag00011011 == 1'b0) & (tmp_13_i_i_reg_1248 == 1'd0))) begin
                ap_NS_fsm = ap_ST_fsm_state13;
            end else begin
                ap_NS_fsm = ap_ST_fsm_pp0_stage1;
            end
        end
        ap_ST_fsm_pp0_stage2 : begin
            if ((ap_block_pp0_stage2_flag00011011 == 1'b0)) begin
                ap_NS_fsm = ap_ST_fsm_pp0_stage3;
            end else begin
                ap_NS_fsm = ap_ST_fsm_pp0_stage2;
            end
        end
        ap_ST_fsm_pp0_stage3 : begin
            if ((ap_block_pp0_stage3_flag00011011 == 1'b0)) begin
                ap_NS_fsm = ap_ST_fsm_pp0_stage4;
            end else begin
                ap_NS_fsm = ap_ST_fsm_pp0_stage3;
            end
        end
        ap_ST_fsm_pp0_stage4 : begin
            if ((ap_block_pp0_stage4_flag00011011 == 1'b0)) begin
                ap_NS_fsm = ap_ST_fsm_pp0_stage5;
            end else begin
                ap_NS_fsm = ap_ST_fsm_pp0_stage4;
            end
        end
        ap_ST_fsm_pp0_stage5 : begin
            if ((ap_block_pp0_stage5_flag00011011 == 1'b0)) begin
                ap_NS_fsm = ap_ST_fsm_pp0_stage6;
            end else begin
                ap_NS_fsm = ap_ST_fsm_pp0_stage5;
            end
        end
        ap_ST_fsm_pp0_stage6 : begin
            if ((ap_block_pp0_stage6_flag00011011 == 1'b0)) begin
                ap_NS_fsm = ap_ST_fsm_pp0_stage7;
            end else begin
                ap_NS_fsm = ap_ST_fsm_pp0_stage6;
            end
        end
        ap_ST_fsm_pp0_stage7 : begin
            if ((ap_block_pp0_stage7_flag00011011 == 1'b0)) begin
                ap_NS_fsm = ap_ST_fsm_pp0_stage0;
            end else begin
                ap_NS_fsm = ap_ST_fsm_pp0_stage7;
            end
        end
        ap_ST_fsm_state13 : begin
            ap_NS_fsm = ap_ST_fsm_state3;
        end
        default : begin
            ap_NS_fsm = 'bx;
        end
    endcase
end

assign HwReg_height_cast8_loc_out_din = HwReg_height_cast8_loc_dout;

assign StrmMPix_V_val_0_V0_status = (StrmMPix_V_val_0_V_empty_n & StrmMPix_V_val_1_V_empty_n & StrmMPix_V_val_2_V_empty_n);

assign StrmMPix_V_val_0_V_read = StrmMPix_V_val_0_V0_update;

assign StrmMPix_V_val_1_V_read = StrmMPix_V_val_0_V0_update;

assign StrmMPix_V_val_2_V_read = StrmMPix_V_val_0_V0_update;

assign VideoFormat_off1_i_i_fu_561_p2 = ($signed(tmp_fu_535_p1) + $signed(8'd241));

assign VideoFormat_off2_i_i_fu_589_p2 = ($signed(tmp_fu_535_p1) + $signed(8'd238));

assign VideoFormat_off3_i_i_fu_611_p2 = ($signed(tmp_fu_535_p1) + $signed(8'd234));

assign VideoFormat_off4_i_i_fu_633_p2 = ($signed(tmp_fu_535_p1) + $signed(8'd236));

assign VideoFormat_off_i_i_fu_539_p2 = ($signed(8'd246) + $signed(tmp_fu_535_p1));

assign ap_CS_fsm_pp0_stage0 = ap_CS_fsm[32'd3];

assign ap_CS_fsm_pp0_stage1 = ap_CS_fsm[32'd4];

assign ap_CS_fsm_pp0_stage2 = ap_CS_fsm[32'd5];

assign ap_CS_fsm_pp0_stage3 = ap_CS_fsm[32'd6];

assign ap_CS_fsm_pp0_stage4 = ap_CS_fsm[32'd7];

assign ap_CS_fsm_pp0_stage5 = ap_CS_fsm[32'd8];

assign ap_CS_fsm_pp0_stage6 = ap_CS_fsm[32'd9];

assign ap_CS_fsm_pp0_stage7 = ap_CS_fsm[32'd10];

assign ap_CS_fsm_state1 = ap_CS_fsm[32'd0];

assign ap_CS_fsm_state13 = ap_CS_fsm[32'd11];

assign ap_CS_fsm_state2 = ap_CS_fsm[32'd1];

assign ap_CS_fsm_state3 = ap_CS_fsm[32'd2];

assign ap_block_pp0_stage0_flag00000000 = ~(1'b1 == 1'b1);

always @ (*) begin
    ap_block_pp0_stage0_flag00001001 = ((1'b1 == ap_enable_reg_pp0_iter1) & (((1'b0 == StrmMPix_V_val_0_V0_status) & (1'b1 == ap_predicate_op205_read_state12)) | ((1'd1 == or_cond1_2_i_i_reg_1280) & (1'b0 == bytes_plane0_V_V_full_n))));
end

always @ (*) begin
    ap_block_pp0_stage0_flag00011001 = ((1'b1 == ap_enable_reg_pp0_iter1) & (((1'b0 == StrmMPix_V_val_0_V0_status) & (1'b1 == ap_predicate_op205_read_state12)) | ((1'd1 == or_cond1_2_i_i_reg_1280) & (1'b0 == bytes_plane0_V_V_full_n))));
end

always @ (*) begin
    ap_block_pp0_stage0_flag00011011 = ((1'b1 == ap_enable_reg_pp0_iter1) & (((1'b0 == StrmMPix_V_val_0_V0_status) & (1'b1 == ap_predicate_op205_read_state12)) | ((1'd1 == or_cond1_2_i_i_reg_1280) & (1'b0 == bytes_plane0_V_V_full_n))));
end

assign ap_block_pp0_stage1_flag00000000 = ~(1'b1 == 1'b1);

always @ (*) begin
    ap_block_pp0_stage1_flag00011001 = ((1'b1 == ap_enable_reg_pp0_iter0) & (1'b0 == StrmMPix_V_val_0_V0_status) & (1'b1 == ap_predicate_op129_read_state5));
end

always @ (*) begin
    ap_block_pp0_stage1_flag00011011 = ((1'b1 == ap_enable_reg_pp0_iter0) & (1'b0 == StrmMPix_V_val_0_V0_status) & (1'b1 == ap_predicate_op129_read_state5));
end

assign ap_block_pp0_stage2_flag00000000 = ~(1'b1 == 1'b1);

always @ (*) begin
    ap_block_pp0_stage2_flag00011001 = ((1'b1 == ap_enable_reg_pp0_iter0) & (1'b0 == StrmMPix_V_val_0_V0_status) & (1'b1 == ap_predicate_op139_read_state6));
end

always @ (*) begin
    ap_block_pp0_stage2_flag00011011 = ((1'b1 == ap_enable_reg_pp0_iter0) & (1'b0 == StrmMPix_V_val_0_V0_status) & (1'b1 == ap_predicate_op139_read_state6));
end

assign ap_block_pp0_stage3_flag00000000 = ~(1'b1 == 1'b1);

always @ (*) begin
    ap_block_pp0_stage3_flag00011001 = ((1'b1 == ap_enable_reg_pp0_iter0) & (1'b0 == StrmMPix_V_val_0_V0_status) & (1'b1 == ap_predicate_op149_read_state7));
end

always @ (*) begin
    ap_block_pp0_stage3_flag00011011 = ((1'b1 == ap_enable_reg_pp0_iter0) & (1'b0 == StrmMPix_V_val_0_V0_status) & (1'b1 == ap_predicate_op149_read_state7));
end

assign ap_block_pp0_stage4_flag00000000 = ~(1'b1 == 1'b1);

always @ (*) begin
    ap_block_pp0_stage4_flag00001001 = ((1'b1 == ap_enable_reg_pp0_iter0) & (((1'b0 == StrmMPix_V_val_0_V0_status) & (1'b1 == ap_predicate_op159_read_state8)) | ((1'b0 == bytes_plane0_V_V_full_n) & (1'b1 == ap_predicate_op166_write_state8))));
end

always @ (*) begin
    ap_block_pp0_stage4_flag00011001 = ((1'b1 == ap_enable_reg_pp0_iter0) & (((1'b0 == StrmMPix_V_val_0_V0_status) & (1'b1 == ap_predicate_op159_read_state8)) | ((1'b0 == bytes_plane0_V_V_full_n) & (1'b1 == ap_predicate_op166_write_state8))));
end

always @ (*) begin
    ap_block_pp0_stage4_flag00011011 = ((1'b1 == ap_enable_reg_pp0_iter0) & (((1'b0 == StrmMPix_V_val_0_V0_status) & (1'b1 == ap_predicate_op159_read_state8)) | ((1'b0 == bytes_plane0_V_V_full_n) & (1'b1 == ap_predicate_op166_write_state8))));
end

assign ap_block_pp0_stage5_flag00000000 = ~(1'b1 == 1'b1);

always @ (*) begin
    ap_block_pp0_stage5_flag00011001 = ((1'b1 == ap_enable_reg_pp0_iter0) & (1'b0 == StrmMPix_V_val_0_V0_status) & (1'b1 == ap_predicate_op172_read_state9));
end

always @ (*) begin
    ap_block_pp0_stage5_flag00011011 = ((1'b1 == ap_enable_reg_pp0_iter0) & (1'b0 == StrmMPix_V_val_0_V0_status) & (1'b1 == ap_predicate_op172_read_state9));
end

assign ap_block_pp0_stage6_flag00000000 = ~(1'b1 == 1'b1);

always @ (*) begin
    ap_block_pp0_stage6_flag00011001 = ((1'b1 == ap_enable_reg_pp0_iter0) & (1'b0 == StrmMPix_V_val_0_V0_status) & (1'b1 == ap_predicate_op184_read_state10));
end

always @ (*) begin
    ap_block_pp0_stage6_flag00011011 = ((1'b1 == ap_enable_reg_pp0_iter0) & (1'b0 == StrmMPix_V_val_0_V0_status) & (1'b1 == ap_predicate_op184_read_state10));
end

assign ap_block_pp0_stage7_flag00000000 = ~(1'b1 == 1'b1);

always @ (*) begin
    ap_block_pp0_stage7_flag00001001 = ((1'b1 == ap_enable_reg_pp0_iter0) & (((1'b0 == StrmMPix_V_val_0_V0_status) & (1'b1 == ap_predicate_op193_read_state11)) | ((1'b0 == bytes_plane0_V_V_full_n) & (1'b1 == ap_predicate_op199_write_state11))));
end

always @ (*) begin
    ap_block_pp0_stage7_flag00011001 = ((1'b1 == ap_enable_reg_pp0_iter0) & (((1'b0 == StrmMPix_V_val_0_V0_status) & (1'b1 == ap_predicate_op193_read_state11)) | ((1'b0 == bytes_plane0_V_V_full_n) & (1'b1 == ap_predicate_op199_write_state11))));
end

always @ (*) begin
    ap_block_pp0_stage7_flag00011011 = ((1'b1 == ap_enable_reg_pp0_iter0) & (((1'b0 == StrmMPix_V_val_0_V0_status) & (1'b1 == ap_predicate_op193_read_state11)) | ((1'b0 == bytes_plane0_V_V_full_n) & (1'b1 == ap_predicate_op199_write_state11))));
end

always @ (*) begin
    ap_block_state1 = ((1'b0 == ap_start) | (ap_done_reg == 1'b1) | (1'b0 == HwReg_height_cast8_loc_empty_n) | (1'b0 == tmp_3_loc_empty_n) | (1'b0 == HwReg_height_cast8_loc_out_full_n) | (1'b0 == tmp_3_loc_out_full_n) | (1'b0 == HwReg_width_cast9_loc_empty_n));
end

always @ (*) begin
    ap_block_state10_pp0_stage6_iter0 = ((1'b0 == StrmMPix_V_val_0_V0_status) & (1'b1 == ap_predicate_op184_read_state10));
end

always @ (*) begin
    ap_block_state11_pp0_stage7_iter0 = (((1'b0 == StrmMPix_V_val_0_V0_status) & (1'b1 == ap_predicate_op193_read_state11)) | ((1'b0 == bytes_plane0_V_V_full_n) & (1'b1 == ap_predicate_op199_write_state11)));
end

always @ (*) begin
    ap_block_state12_pp0_stage0_iter1 = (((1'b0 == StrmMPix_V_val_0_V0_status) & (1'b1 == ap_predicate_op205_read_state12)) | ((1'd1 == or_cond1_2_i_i_reg_1280) & (1'b0 == bytes_plane0_V_V_full_n)));
end

assign ap_block_state4_pp0_stage0_iter0 = ~(1'b1 == 1'b1);

always @ (*) begin
    ap_block_state5_pp0_stage1_iter0 = ((1'b0 == StrmMPix_V_val_0_V0_status) & (1'b1 == ap_predicate_op129_read_state5));
end

always @ (*) begin
    ap_block_state6_pp0_stage2_iter0 = ((1'b0 == StrmMPix_V_val_0_V0_status) & (1'b1 == ap_predicate_op139_read_state6));
end

always @ (*) begin
    ap_block_state7_pp0_stage3_iter0 = ((1'b0 == StrmMPix_V_val_0_V0_status) & (1'b1 == ap_predicate_op149_read_state7));
end

always @ (*) begin
    ap_block_state8_pp0_stage4_iter0 = (((1'b0 == StrmMPix_V_val_0_V0_status) & (1'b1 == ap_predicate_op159_read_state8)) | ((1'b0 == bytes_plane0_V_V_full_n) & (1'b1 == ap_predicate_op166_write_state8)));
end

always @ (*) begin
    ap_block_state9_pp0_stage5_iter0 = ((1'b0 == StrmMPix_V_val_0_V0_status) & (1'b1 == ap_predicate_op172_read_state9));
end

always @ (*) begin
    ap_condition_1138 = ((1'b1 == ap_CS_fsm_pp0_stage1) & (1'b1 == ap_enable_reg_pp0_iter0) & (tmp_13_i_i_reg_1248 == 1'd1) & (ap_block_pp0_stage1_flag00011001 == 1'b0));
end

always @ (*) begin
    ap_condition_1143 = ((1'b1 == ap_enable_reg_pp0_iter0) & (tmp_13_i_i_reg_1248 == 1'd1) & (1'b1 == ap_CS_fsm_pp0_stage2) & (ap_block_pp0_stage2_flag00011001 == 1'b0));
end

always @ (*) begin
    ap_condition_1147 = ((1'b1 == ap_enable_reg_pp0_iter0) & (tmp_13_i_i_reg_1248 == 1'd1) & (1'b1 == ap_CS_fsm_pp0_stage3) & (ap_block_pp0_stage3_flag00011001 == 1'b0));
end

always @ (*) begin
    ap_condition_1151 = ((1'b1 == ap_enable_reg_pp0_iter0) & (tmp_13_i_i_reg_1248 == 1'd1) & (1'b1 == ap_CS_fsm_pp0_stage4) & (ap_block_pp0_stage4_flag00011001 == 1'b0));
end

always @ (*) begin
    ap_condition_1155 = ((1'b1 == ap_enable_reg_pp0_iter0) & (tmp_13_i_i_reg_1248 == 1'd1) & (1'b1 == ap_CS_fsm_pp0_stage5) & (ap_block_pp0_stage5_flag00011001 == 1'b0));
end

always @ (*) begin
    ap_condition_1159 = ((1'b1 == ap_enable_reg_pp0_iter0) & (tmp_13_i_i_reg_1248 == 1'd1) & (1'b1 == ap_CS_fsm_pp0_stage6) & (ap_block_pp0_stage6_flag00011001 == 1'b0));
end

always @ (*) begin
    ap_condition_515 = ((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_CS_fsm_pp0_stage7) & (ap_block_pp0_stage7_flag00011001 == 1'b0));
end

always @ (*) begin
    ap_condition_549 = ((tmp_13_i_i_reg_1248 == 1'd1) & (1'b1 == ap_CS_fsm_pp0_stage0) & (1'b1 == ap_enable_reg_pp0_iter1) & (ap_block_pp0_stage0_flag00000000 == 1'b0));
end

assign ap_enable_pp0 = (ap_idle_pp0 ^ 1'b1);

assign ap_phi_precharge_reg_pp0_iter0_pix_val_V_0_8_i_i_reg_480 = 'bx;

assign ap_phi_precharge_reg_pp0_iter0_pix_val_V_0_9_i_i_reg_510 = 'bx;

assign ap_phi_precharge_reg_pp0_iter0_pix_val_V_1_8_i_i_reg_470 = 'bx;

assign ap_phi_precharge_reg_pp0_iter0_pix_val_V_1_9_i_i_reg_500 = 'bx;

assign ap_phi_precharge_reg_pp0_iter0_pix_val_V_2_8_i_i_reg_460 = 'bx;

assign ap_phi_precharge_reg_pp0_iter0_pix_val_V_2_9_i_i_reg_490 = 'bx;

always @ (*) begin
    ap_predicate_op129_read_state5 = ((tmp_13_i_i_reg_1248 == 1'd1) & (1'd1 == or_cond_i_i_reg_1268));
end

always @ (*) begin
    ap_predicate_op139_read_state6 = ((tmp_13_i_i_reg_1248 == 1'd1) & (1'd1 == or_cond_1_i_i_reg_1314));
end

always @ (*) begin
    ap_predicate_op149_read_state7 = ((tmp_13_i_i_reg_1248 == 1'd1) & (1'd1 == or_cond_2_i_i_reg_1333));
end

always @ (*) begin
    ap_predicate_op159_read_state8 = ((tmp_13_i_i_reg_1248 == 1'd1) & (1'd1 == or_cond_3_i_i_reg_1352));
end

always @ (*) begin
    ap_predicate_op166_write_state8 = ((tmp_13_i_i_reg_1248 == 1'd1) & (1'd1 == or_cond1_i_i_reg_1272));
end

always @ (*) begin
    ap_predicate_op172_read_state9 = ((tmp_13_i_i_reg_1248 == 1'd1) & (1'd1 == or_cond_4_i_i_reg_1371));
end

always @ (*) begin
    ap_predicate_op184_read_state10 = ((tmp_13_i_i_reg_1248 == 1'd1) & (1'd1 == or_cond_5_i_i_reg_1390));
end

always @ (*) begin
    ap_predicate_op193_read_state11 = ((tmp_13_i_i_reg_1248 == 1'd1) & (1'd1 == or_cond_6_i_i_reg_1394));
end

always @ (*) begin
    ap_predicate_op199_write_state11 = ((tmp_13_i_i_reg_1248 == 1'd1) & (1'd1 == or_cond1_1_i_i_reg_1276));
end

always @ (*) begin
    ap_predicate_op205_read_state12 = ((tmp_13_i_i_reg_1248 == 1'd1) & (1'd1 == or_cond_7_i_i_reg_1398));
end

assign exitcond1_i_i_fu_880_p2 = ((y_cast_i_i_fu_876_p1 == tmp_11_cast_i_i_reg_1179) ? 1'b1 : 1'b0);

assign icmp1_fu_577_p2 = ((tmp_3_fu_567_p4 == 7'd0) ? 1'b1 : 1'b0);

assign icmp2_fu_605_p2 = ((tmp_4_fu_595_p4 == 7'd0) ? 1'b1 : 1'b0);

assign icmp3_fu_627_p2 = ((tmp_5_fu_617_p4 == 7'd0) ? 1'b1 : 1'b0);

assign icmp4_fu_649_p2 = ((tmp_6_fu_639_p4 == 7'd0) ? 1'b1 : 1'b0);

assign icmp5_fu_802_p2 = ((tmp_8_fu_792_p4 != 3'd0) ? 1'b1 : 1'b0);

assign icmp6_fu_824_p2 = ((tmp_9_fu_814_p4 != 2'd0) ? 1'b1 : 1'b0);

assign icmp7_fu_864_p2 = ((tmp_10_fu_854_p4 != 2'd0) ? 1'b1 : 1'b0);

assign icmp_fu_555_p2 = ((tmp_2_fu_545_p4 == 7'd0) ? 1'b1 : 1'b0);

assign loopWidth1_cast_i_i_s_fu_665_p4 = {{tmp_5_i_i_fu_659_p2[12:3]}};

assign loopWidth_cast_i_i_c_fu_699_p4 = {{mul_fu_693_p2[20:12]}};

assign mul_fu_693_p1 = mul_fu_693_p10;

assign mul_fu_693_p10 = tmp_6_i_i_reg_1156;

assign mul_fu_693_p2 = (22'd1366 * mul_fu_693_p1);

assign or_cond1_1_i_i_fu_921_p2 = (tmp_14_i_i_fu_906_p2 | icmp7_reg_1229);

assign or_cond1_2_i_i_fu_926_p2 = (tmp_14_i_i_fu_906_p2 | tmp_25_2_i_i_reg_1234);

assign or_cond1_i_i_fu_916_p2 = (tmp_14_i_i_fu_906_p2 | tmp_25_i_i_reg_1224);

assign or_cond_1_i_i_fu_940_p2 = (tmp_14_i_i_reg_1257 | icmp5_reg_1194);

assign or_cond_2_i_i_fu_944_p2 = (tmp_14_i_i_reg_1257 | tmp_24_2_i_i_reg_1199);

assign or_cond_3_i_i_fu_948_p2 = (tmp_14_i_i_reg_1257 | icmp6_reg_1204);

assign or_cond_4_i_i_fu_952_p2 = (tmp_14_i_i_reg_1257 | tmp_24_4_i_i_reg_1209);

assign or_cond_5_i_i_fu_977_p2 = (tmp_14_i_i_reg_1257 | tmp_24_5_i_i_reg_1214);

assign or_cond_6_i_i_fu_981_p2 = (tmp_14_i_i_reg_1257 | tmp_24_6_i_i_reg_1219);

assign or_cond_7_i_i_fu_985_p2 = (tmp_14_i_i_reg_1257 | tmp_7_i_i_reg_1174);

assign or_cond_i_i_fu_911_p2 = (tmp_14_i_i_fu_906_p2 | tmp_24_i_i_reg_1189);

assign p_shl1_cast_i_i_fu_743_p1 = p_shl1_i_i_fu_736_p3;

assign p_shl1_i_i_fu_736_p3 = {{remPix_reg_1161}, {3'd0}};

assign p_shl_cast_i_i_fu_732_p1 = p_shl_i_i_fu_725_p3;

assign p_shl_i_i_fu_725_p3 = {{remPix_reg_1161}, {5'd0}};

assign remPix_2_fu_717_p3 = ((tmp_7_i_i_fu_712_p2[0:0] === 1'b1) ? 4'd8 : remPix_cast_i_i_fu_709_p1);

assign remPix_cast_i_i_fu_709_p1 = remPix_reg_1161;

assign remPix_fu_681_p1 = HwReg_width_cast9_loc_dout[2:0];

assign remainTrx_fu_769_p3 = ((tmp_7_i_i_fu_712_p2[0:0] === 1'b1) ? 3'd3 : tmp_10_cast_i_i_fu_759_p4);

assign tmp_10_cast_i_i_fu_759_p4 = {{tmp_9_i_i_fu_753_p2[8:6]}};

assign tmp_10_fu_854_p4 = {{remainTrx_fu_769_p3[2:1]}};

assign tmp_11_cast_i_i_fu_777_p1 = HwReg_height_cast8_l_reg_1103;

assign tmp_12_i_i_fu_780_p2 = ($signed(9'd511) + $signed(loopWidth_cast_i_i_c_fu_699_p4));

assign tmp_13_i_i_fu_895_p2 = (($signed(x_cast_i_i_cast_fu_891_p1) < $signed(loopWidth_cast_i_i_c_reg_1169)) ? 1'b1 : 1'b0);

assign tmp_14_i_i_fu_906_p2 = (($signed(x_cast_i_i_cast_fu_891_p1) < $signed(tmp_12_i_i_reg_1184)) ? 1'b1 : 1'b0);

assign tmp_24_2_i_i_fu_808_p2 = ((remPix_2_fu_717_p3 > 4'd2) ? 1'b1 : 1'b0);

assign tmp_24_4_i_i_fu_830_p2 = ((remPix_2_fu_717_p3 > 4'd4) ? 1'b1 : 1'b0);

assign tmp_24_5_i_i_fu_836_p2 = ((remPix_2_fu_717_p3 > 4'd5) ? 1'b1 : 1'b0);

assign tmp_24_6_i_i_fu_842_p2 = ((remPix_2_fu_717_p3 > 4'd6) ? 1'b1 : 1'b0);

assign tmp_24_i_i_fu_786_p2 = ((remPix_2_fu_717_p3 != 4'd0) ? 1'b1 : 1'b0);

assign tmp_25_2_i_i_fu_870_p2 = ((remainTrx_fu_769_p3 > 3'd2) ? 1'b1 : 1'b0);

assign tmp_25_i_i_fu_848_p2 = ((remainTrx_fu_769_p3 != 3'd0) ? 1'b1 : 1'b0);

assign tmp_2_fu_545_p4 = {{VideoFormat_off_i_i_fu_539_p2[7:1]}};

assign tmp_3_fu_567_p4 = {{VideoFormat_off1_i_i_fu_561_p2[7:1]}};

assign tmp_3_loc_out_din = tmp_3_loc_dout;

assign tmp_4_fu_595_p4 = {{VideoFormat_off2_i_i_fu_589_p2[7:1]}};

assign tmp_5_fu_617_p4 = {{VideoFormat_off3_i_i_fu_611_p2[7:1]}};

assign tmp_5_i_i_fu_659_p2 = (13'd7 + tmp_cast_i_i_cast_fu_655_p1);

assign tmp_6_fu_639_p4 = {{VideoFormat_off4_i_i_fu_633_p2[7:1]}};

assign tmp_6_i_i_fu_675_p2 = (10'd2 + loopWidth1_cast_i_i_s_fu_665_p4);

assign tmp_7_i_i_fu_712_p2 = ((remPix_reg_1161 == 3'd0) ? 1'b1 : 1'b0);

assign tmp_8_fu_792_p4 = {{remPix_2_fu_717_p3[3:1]}};

assign tmp_8_i_i_fu_747_p2 = (p_shl_cast_i_i_fu_732_p1 - p_shl1_cast_i_i_fu_743_p1);

assign tmp_9_fu_814_p4 = {{remPix_2_fu_717_p3[3:2]}};

assign tmp_9_i_i_fu_753_p2 = (9'd63 + tmp_8_i_i_fu_747_p2);

assign tmp_V_1_fu_989_p9 = {{{{{{{{ap_phi_precharge_reg_pp0_iter0_pix_val_V_0_7_i_i_reg_449}, {pix_val_V_2_6_i_i_reg_394}}, {pix_val_V_1_6_i_i_reg_405}}, {pix_val_V_0_6_i_i_reg_416}}, {pix_val_V_2_5_i_i_reg_361}}, {pix_val_V_1_5_i_i_reg_372}}, {pix_val_V_0_5_i_i_reg_383}}, {pix_val_V_2_4_i_i_reg_328}};

assign tmp_V_2_fu_1062_p9 = {{{{{{{{pix_val_V_2_9_i_i_phi_fu_493_p4}, {pix_val_V_1_9_i_i_phi_fu_503_p4}}, {pix_val_V_0_9_i_i_phi_fu_513_p4}}, {ap_phi_precharge_reg_pp0_iter1_pix_val_V_2_8_i_i_reg_460}}, {ap_phi_precharge_reg_pp0_iter1_pix_val_V_1_8_i_i_reg_470}}, {ap_phi_precharge_reg_pp0_iter1_pix_val_V_0_8_i_i_reg_480}}, {pix_val_V_2_7_i_i_reg_427}}, {pix_val_V_1_7_i_i_reg_438}};

assign tmp_V_fu_956_p9 = {{{{{{{{ap_phi_precharge_reg_pp0_iter0_pix_val_V_1_4_i_i_reg_339}, {ap_phi_precharge_reg_pp0_iter0_pix_val_V_0_4_i_i_reg_350}}, {pix_val_V_2_3_i_i_reg_295}}, {pix_val_V_1_3_i_i_reg_306}}, {pix_val_V_0_3_i_i_reg_317}}, {pix_val_V_2_2_i_i_reg_265}}, {pix_val_V_1_2_i_i_reg_275}}, {pix_val_V_0_2_i_i_reg_285}};

assign tmp_cast_i_i_cast_fu_655_p1 = tmp_3_loc_dout;

assign tmp_fu_535_p1 = HwReg_video_format[7:0];

assign tmp_i_i_fu_583_p2 = ((tmp_fu_535_p1 == 8'd12) ? 1'b1 : 1'b0);

assign x_cast_i_i_cast_fu_891_p1 = x_i_i_phi_fu_258_p4;

assign x_fu_900_p2 = (x_i_i_phi_fu_258_p4 + 8'd1);

assign y_cast_i_i_fu_876_p1 = y_i_i_reg_243;

assign y_fu_885_p2 = (y_i_i_reg_243 + 16'd1);

always @ (posedge ap_clk) begin
    tmp_11_cast_i_i_reg_1179[16:9] <= 8'b00000000;
end

endmodule //design_1_v_frmbuf_wr_0_0_MultiPixStream2Bytes
