### Device Usage Page (usage_statistics_webtalk.html)

This HTML page displays the device usage statistics that will be sent to Xilinx.
To see the actual file transmitted to Xilinx, please click here.

software_version_and_target_device
beta | FALSE | build_version | 1957588
date_generated | Thu Dec 7 08:28:45 2017 | os_platform | WIN64
product_version | Vivado v2017.2.1 (64-bit) | project_id | deb49a5fbf574345b113d43e227ab142
project_iteration | 6 | random_id | 37d0c093bab0537194e81b0efab8e0b3
registration_id | 211346427_1777525171_210656923_464 | route_design | TRUE
target_device | xc7z010 | target_family | zynq
target_package | clg400 | target_speed | -1
tool_flow | Vivado

user_environment
cpu_name | AMD FX(tm)-8300 Eight-Core Processor | cpu_speed | 3322 MHz
os_name | Microsoft Windows 7 , 64-bit | os_release | Service Pack 1 (build 7601)
system_ram | 8.000 GB | total_processors | 1

vivado_usage

java_command_handlers
addsources=2 | autoconnectport=19 | autoconnecttarget=1 | coreview=1
createblockdesign=2 | createtophdl=2 | customizecore=1 | customizersbblock=14
disconnectrsbpin=1 | editcopy=1 | editpaste=2 | editundo=2
launchprogramfpga=4 | managecompositetargets=1 | newexporthardware=4 | newlaunchhardware=1
openblockdesign=2 | openhardwaremanager=5 | openrecenttarget=1 | programdevice=4
runbitgen=6 | saversbdesign=4 | settopnode=1 | showview=5
toggleviewnavigator=3 | viewlayoutcmd=2

other_data
guimode=2

project_data
constraintsetcount=1 | core_container=false | currentimplrun=impl_1 | currentsynthesisrun=synth_1
default_library=xil_defaultlib | designmode=RTL | export_simulation_activehdl=0 | export_simulation_ies=0
export_simulation_modelsim=0 | export_simulation_questa=0 | export_simulation_riviera=0 | export_simulation_vcs=0
export_simulation_xsim=0 | implstrategy=Vivado Implementation Defaults | launch_simulation_activehdl=0 | launch_simulation_ies=0
launch_simulation_modelsim=0 | launch_simulation_questa=0 | launch_simulation_riviera=0 | launch_simulation_vcs=0
launch_simulation_xsim=0 | simulator_language=Mixed | srcsetcount=7 | synthesisstrategy=Vivado Synthesis Defaults
target_language=Verilog | target_simulator=XSim | totalimplruns=21 | totalsynthesisruns=21

unisim_transformation
post_unisim_transformation
bibuf=130 | bufg=3 | carry4=548 | dsp48e1=67
fdce=139 | fdpe=27 | fdre=10453 | fdse=315
gnd=493 | ibuf=13 | lut1=933 | lut2=1297
lut3=1939 | lut4=2034 | lut5=1271 | lut6=2367
muxf7=170 | muxf8=82 | obuf=26 | ps7=1
ramb18e1=16 | ramb36e1=5 | ramd32=558 | rams32=186
srl16e=101 | srlc32e=417 | vcc=391
pre_unisim_transformation
bibuf=130 | bufg=3 | carry4=548 | dsp48e1=67
fdce=139 | fdpe=27 | fdre=10453 | fdse=315
gnd=493 | ibuf=13 | lut1=933 | lut2=1297
lut3=1939 | lut4=2034 | lut5=1271 | lut6=2367
muxf7=170 | muxf8=82 | obuf=25 | ps7=1
ram32m=93 | ramb18e1=16 | ramb36e1=5 | srl16e=101
srlc32e=417 | vcc=391

power_opt_design
command_line_options_spo
-cell_types=default::all | -clocks=default::[not_specified] | -exclude_cells=default::[not_specified] | -include_cells=default::[not_specified]
usage
bram_ports_augmented=1 | bram_ports_newly_gated=3 | bram_ports_total=42 | flow_state=default
slice_registers_augmented=0 | slice_registers_newly_gated=0 | slice_registers_total=10208 | srls_augmented=0
srls_newly_gated=0 | srls_total=492

ip_statistics
IP_Integrator/1
bdsource=SBD | core_container=NA | iptotal=1 | maxhierdepth=1
numblks=14 | numhdlrefblks=0 | numhierblks=4 | numhlsblks=0
numnonxlnxblks=0 | numpkgbdblks=0 | numreposblks=10 | numsysgenblks=0
synth_mode=OOC_per_IP | x_iplanguage=VERILOG | x_iplibrary=BlockDiagram | x_ipname=bd_68b9
x_ipvendor=xilinx.com | x_ipversion=1.00.a
IP_Integrator/2
bdsource=SBD | core_container=NA | iptotal=1 | maxhierdepth=1
numblks=15 | numhdlrefblks=0 | numhierblks=4 | numhlsblks=0
numnonxlnxblks=0 | numpkgbdblks=0 | numreposblks=11 | numsysgenblks=0
synth_mode=OOC_per_IP | x_iplanguage=VERILOG | x_iplibrary=BlockDiagram | x_ipname=bd_6f02
x_ipvendor=xilinx.com | x_ipversion=1.00.a
IP_Integrator/3
bdsource=USER | core_container=NA | da_axi4_cnt=14 | da_ps7_cnt=1
iptotal=1 | maxhierdepth=0 | numblks=30 | numhdlrefblks=3
numhierblks=7 | numhlsblks=1 | numnonxlnxblks=1 | numpkgbdblks=0
numreposblks=23 | numsysgenblks=0 | synth_mode=OOC_per_IP | x_iplanguage=VERILOG
x_iplibrary=BlockDiagram | x_ipname=design_1 | x_ipvendor=xilinx.com | x_ipversion=1.00.a
axi_clock_converter_v2_1_12_axi_clock_converter/1
c_axi_addr_width=6 | c_axi_aruser_width=1 | c_axi_awuser_width=1 | c_axi_buser_width=1
c_axi_data_width=32 | c_axi_id_width=1 | c_axi_is_aclk_async=1 | c_axi_protocol=2
c_axi_ruser_width=1 | c_axi_supports_read=1 | c_axi_supports_user_signals=0 | c_axi_supports_write=1
c_axi_wuser_width=1 | c_family=zynq | c_m_axi_aclk_ratio=2 | c_s_axi_aclk_ratio=1
c_synchronizer_stage=3 | core_container=NA | iptotal=2 | x_ipcorerevision=12
x_iplanguage=VERILOG | x_iplibrary=ip | x_ipname=axi_clock_converter | x_ipproduct=Vivado 2017.2.1
x_ipsimlanguage=MIXED | x_ipvendor=xilinx.com | x_ipversion=2.1
axi_crossbar_v2_1_14_axi_crossbar/1
c_axi_addr_width=32 | c_axi_aruser_width=1 | c_axi_awuser_width=1 | c_axi_buser_width=1
c_axi_data_width=32 | c_axi_id_width=1 | c_axi_protocol=2 | c_axi_ruser_width=1
c_axi_supports_user_signals=0 | c_axi_wuser_width=1 | c_connectivity_mode=0 | c_family=zynq
c_m_axi_addr_width=0x0000001000000010000000100000001000000010 | c_m_axi_base_addr=0x000000004281000000000000428000000000000043c200000000000043c100000000000043c00000 | c_m_axi_read_connectivity=0x0000000100000001000000010000000100000001 | c_m_axi_read_issuing=0x0000000100000001000000010000000100000001
c_m_axi_secure=0x0000000000000000000000000000000000000000 | c_m_axi_write_connectivity=0x0000000100000001000000010000000100000001 | c_m_axi_write_issuing=0x0000000100000001000000010000000100000001 | c_num_addr_ranges=1
c_num_master_slots=5 | c_num_slave_slots=1 | c_r_register=1 | c_s_axi_arb_priority=0x00000000
c_s_axi_base_id=0x00000000 | c_s_axi_read_acceptance=0x00000001 | c_s_axi_single_thread=0x00000001 | c_s_axi_thread_id_width=0x00000000
c_s_axi_write_acceptance=0x00000001 | core_container=NA | iptotal=1 | x_ipcorerevision=14
x_iplanguage=VERILOG | x_iplibrary=ip | x_ipname=axi_crossbar | x_ipproduct=Vivado 2017.2.1
x_ipsimlanguage=MIXED | x_ipvendor=xilinx.com | x_ipversion=2.1
axi_protocol_converter_v2_1_13_axi_protocol_converter/1
c_axi_addr_width=32 | c_axi_aruser_width=1 | c_axi_awuser_width=1 | c_axi_buser_width=1
c_axi_data_width=32 | c_axi_id_width=12 | c_axi_ruser_width=1 | c_axi_supports_read=1
c_axi_supports_user_signals=0 | c_axi_supports_write=1 | c_axi_wuser_width=1 | c_family=zynq
c_ignore_id=0 | c_m_axi_protocol=2 | c_s_axi_protocol=1 | c_translation_mode=2
core_container=NA | iptotal=1 | x_ipcorerevision=13 | x_iplanguage=VERILOG
x_iplibrary=ip | x_ipname=axi_protocol_converter | x_ipproduct=Vivado 2017.2.1 | x_ipsimlanguage=MIXED
x_ipvendor=xilinx.com | x_ipversion=2.1
axi_timer/1
c_count_width=32 | c_family=zynq | c_gen0_assert=1 | c_gen1_assert=1
c_one_timer_only=0 | c_s_axi_addr_width=5 | c_s_axi_data_width=32 | c_trig0_assert=1
c_trig1_assert=1 | core_container=NA | iptotal=1 | x_ipcorerevision=15
x_iplanguage=VERILOG | x_iplibrary=ip | x_ipname=axi_timer | x_ipproduct=Vivado 2017.2.1
x_ipsimlanguage=MIXED | x_ipvendor=xilinx.com | x_ipversion=2.0
axi_timer/2
c_count_width=32 | c_family=zynq | c_gen0_assert=1 | c_gen1_assert=1
c_one_timer_only=0 | c_s_axi_addr_width=5 | c_s_axi_data_width=32 | c_trig0_assert=1
c_trig1_assert=1 | core_container=NA | iptotal=1 | x_ipcorerevision=15
x_iplanguage=VERILOG | x_iplibrary=ip | x_ipname=axi_timer | x_ipproduct=Vivado 2017.2.1
x_ipsimlanguage=MIXED | x_ipvendor=xilinx.com | x_ipversion=2.0
bd_68b9/1
advanced_properties=0 | component_name=design_1_axi_smc_1_1 | core_container=NA | has_aresetn=1
iptotal=1 | num_clks=1 | num_mi=1 | num_si=1
x_ipcorerevision=5 | x_iplanguage=VERILOG | x_iplibrary=ip | x_ipname=smartconnect
x_ipproduct=Vivado 2017.2.1 | x_ipsimlanguage=MIXED | x_ipvendor=xilinx.com | x_ipversion=1.0
bd_6f02/1
advanced_properties=0 | component_name=design_1_axi_smc_1 | core_container=NA | has_aresetn=1
iptotal=1 | num_clks=1 | num_mi=1 | num_si=1
x_ipcorerevision=5 | x_iplanguage=VERILOG | x_iplibrary=ip | x_ipname=smartconnect
x_ipproduct=Vivado 2017.2.1 | x_ipsimlanguage=MIXED | x_ipvendor=xilinx.com | x_ipversion=1.0
debounce/1
core_container=NA | iptotal=1 | x_ipcorerevision=1 | x_iplanguage=VERILOG
x_iplibrary=module_ref | x_ipname=debounce | x_ipproduct=Vivado 2017.2.1 | x_ipsimlanguage=MIXED
x_ipvendor=xilinx.com | x_ipversion=1.0
design_1_v_frmbuf_rd_0_0_v_frmbuf_rd/1
c_m_axi_mm_video_addr_width=32 | c_m_axi_mm_video_aruser_width=1 | c_m_axi_mm_video_awuser_width=1 | c_m_axi_mm_video_buser_width=1
c_m_axi_mm_video_cache_value=0x3 | c_m_axi_mm_video_data_width=64 | c_m_axi_mm_video_id_width=1 | c_m_axi_mm_video_prot_value=0x0
c_m_axi_mm_video_ruser_width=1 | c_m_axi_mm_video_user_value=0x00000000 | c_m_axi_mm_video_wuser_width=1 | c_s_axi_ctrl_addr_width=6
c_s_axi_ctrl_data_width=32 | core_container=NA | iptotal=1 | x_ipcorerevision=1
x_iplanguage=VERILOG | x_iplibrary=ip | x_ipname=v_frmbuf_rd | x_ipproduct=Vivado 2017.2.1
x_ipsimlanguage=MIXED | x_ipvendor=xilinx.com | x_ipversion=1.0
design_1_v_frmbuf_wr_0_0_v_frmbuf_wr/1
c_m_axi_mm_video_addr_width=32 | c_m_axi_mm_video_aruser_width=1 | c_m_axi_mm_video_awuser_width=1 | c_m_axi_mm_video_buser_width=1
c_m_axi_mm_video_cache_value=0x3 | c_m_axi_mm_video_data_width=64 | c_m_axi_mm_video_id_width=1 | c_m_axi_mm_video_prot_value=0x0
c_m_axi_mm_video_ruser_width=1 | c_m_axi_mm_video_user_value=0x00000000 | c_m_axi_mm_video_wuser_width=1 | c_s_axi_ctrl_addr_width=6
c_s_axi_ctrl_data_width=32 | core_container=NA | iptotal=1 | x_ipcorerevision=1
x_iplanguage=VERILOG | x_iplibrary=ip | x_ipname=v_frmbuf_wr | x_ipproduct=Vivado 2017.2.1
x_ipsimlanguage=MIXED | x_ipvendor=xilinx.com | x_ipversion=1.0
hls_ip_2017_2/1
core_container=NA | hls_input_arch=dataflow | hls_input_clock=10.000000 | hls_input_fixed=0
hls_input_float=0 | hls_input_part=xc7z010clg400-1 | hls_input_type=cxx | hls_syn_clock=9.371333
hls_syn_dsp=3 | hls_syn_ff=2901 | hls_syn_lat=-1 | hls_syn_lut=3471
hls_syn_mem=4 | hls_syn_tpt=-1 | iptotal=1
hls_ip_2017_2/2
core_container=NA | hls_input_arch=dataflow | hls_input_clock=10.000000 | hls_input_fixed=0
hls_input_float=0 | hls_input_part=xc7z010clg400-1 | hls_input_type=cxx | hls_syn_clock=9.371333
hls_syn_dsp=3 | hls_syn_ff=2713 | hls_syn_lat=-1 | hls_syn_lut=3440
hls_syn_mem=4 | hls_syn_tpt=-1 | iptotal=1
hls_ip_2017_2/3
core_container=NA | hls_input_arch=dataflow | hls_input_clock=10.000000 | hls_input_fixed=0
hls_input_float=0 | hls_input_part=xc7z010clg400-1 | hls_input_type=cxx | hls_syn_clock=9.400000
hls_syn_dsp=57 | hls_syn_ff=9903 | hls_syn_lat=-1 | hls_syn_lut=5885
hls_syn_mem=15 | hls_syn_tpt=-1 | iptotal=1
ov7670_axi_stream_capture/1
core_container=NA | iptotal=1 | x_ipcorerevision=1 | x_iplanguage=VERILOG
x_iplibrary=module_ref | x_ipname=ov7670_axi_stream_capture | x_ipproduct=Vivado 2017.2.1 | x_ipsimlanguage=MIXED
x_ipvendor=xilinx.com | x_ipversion=1.0
ov7670_controller/1
core_container=NA | iptotal=1 | x_ipcorerevision=1 | x_iplanguage=VERILOG
x_iplibrary=module_ref | x_ipname=ov7670_controller | x_ipproduct=Vivado 2017.2.1 | x_ipsimlanguage=MIXED
x_ipvendor=xilinx.com | x_ipversion=1.0
proc_sys_reset/1
c_aux_reset_high=0 | c_aux_rst_width=4 | c_ext_reset_high=0 | c_ext_rst_width=4
c_family=zynq | c_num_bus_rst=1 | c_num_interconnect_aresetn=1 | c_num_perp_aresetn=1
c_num_perp_rst=1 | core_container=NA | iptotal=2 | x_ipcorerevision=11
x_iplanguage=VERILOG | x_iplibrary=ip | x_ipname=proc_sys_reset | x_ipproduct=Vivado 2017.2.1
x_ipsimlanguage=MIXED | x_ipvendor=xilinx.com | x_ipversion=5.0
processing_system7_v5.5_user_configuration/1
core_container=NA | iptotal=1 | pcw_apu_clk_ratio_enable=6:2:1 | pcw_apu_peripheral_freqmhz=650
pcw_armpll_ctrl_fbdiv=26 | pcw_can0_grp_clk_enable=0 | pcw_can0_peripheral_clksrc=External | pcw_can0_peripheral_enable=0
pcw_can0_peripheral_freqmhz=-1 | pcw_can1_grp_clk_enable=0 | pcw_can1_peripheral_clksrc=External | pcw_can1_peripheral_enable=0
pcw_can1_peripheral_freqmhz=-1 | pcw_can_peripheral_clksrc=IO PLL | pcw_can_peripheral_freqmhz=100 | pcw_cpu_cpu_pll_freqmhz=1300.000
pcw_cpu_peripheral_clksrc=ARM PLL | pcw_crystal_peripheral_freqmhz=50.000000 | pcw_dci_peripheral_clksrc=DDR PLL | pcw_dci_peripheral_freqmhz=10.159
pcw_ddr_ddr_pll_freqmhz=1050.000 | pcw_ddr_hpr_to_critical_priority_level=15 | pcw_ddr_hprlpr_queue_partition=HPR(0)/LPR(32) | pcw_ddr_lpr_to_critical_priority_level=2
pcw_ddr_peripheral_clksrc=DDR PLL | pcw_ddr_port0_hpr_enable=0 | pcw_ddr_port1_hpr_enable=0 | pcw_ddr_port2_hpr_enable=0
pcw_ddr_port3_hpr_enable=0 | pcw_ddr_write_to_critical_priority_level=2 | pcw_ddrpll_ctrl_fbdiv=21 | pcw_enet0_enet0_io=MIO 16 .. 27
pcw_enet0_grp_mdio_enable=1 | pcw_enet0_peripheral_clksrc=IO PLL | pcw_enet0_peripheral_enable=1 | pcw_enet0_peripheral_freqmhz=1000 Mbps
pcw_enet0_reset_enable=0 | pcw_enet1_grp_mdio_enable=0 | pcw_enet1_peripheral_clksrc=IO PLL | pcw_enet1_peripheral_enable=0
pcw_enet1_peripheral_freqmhz=1000 Mbps | pcw_enet1_reset_enable=0 | pcw_enet_reset_polarity=Active Low | pcw_fclk0_peripheral_clksrc=IO PLL
pcw_fclk1_peripheral_clksrc=IO PLL | pcw_fclk2_peripheral_clksrc=IO PLL | pcw_fclk3_peripheral_clksrc=IO PLL | pcw_fpga0_peripheral_freqmhz=100
pcw_fpga1_peripheral_freqmhz=25 | pcw_fpga2_peripheral_freqmhz=35 | pcw_fpga3_peripheral_freqmhz=50 | pcw_fpga_fclk0_enable=1
pcw_fpga_fclk1_enable=1 | pcw_fpga_fclk2_enable=1 | pcw_fpga_fclk3_enable=0 | pcw_ftm_cti_in0=DISABLED
pcw_ftm_cti_in1=DISABLED | pcw_ftm_cti_in2=DISABLED | pcw_ftm_cti_in3=DISABLED | pcw_ftm_cti_out0=DISABLED
pcw_ftm_cti_out1=DISABLED | pcw_ftm_cti_out2=DISABLED | pcw_ftm_cti_out3=DISABLED | pcw_gpio_emio_gpio_enable=0
pcw_gpio_mio_gpio_enable=1 | pcw_gpio_mio_gpio_io=MIO | pcw_gpio_peripheral_enable=0 | pcw_i2c0_grp_int_enable=0
pcw_i2c0_peripheral_enable=0 | pcw_i2c0_reset_enable=0 | pcw_i2c1_grp_int_enable=0 | pcw_i2c1_peripheral_enable=0
pcw_i2c1_reset_enable=0 | pcw_i2c_reset_polarity=Active Low | pcw_io_io_pll_freqmhz=1000.000 | pcw_iopll_ctrl_fbdiv=20
pcw_irq_f2p_mode=DIRECT | pcw_m_axi_gp0_freqmhz=100 | pcw_m_axi_gp1_freqmhz=10 | pcw_nand_cycles_t_ar=1
pcw_nand_cycles_t_clr=1 | pcw_nand_cycles_t_rc=11 | pcw_nand_cycles_t_rea=1 | pcw_nand_cycles_t_rr=1
pcw_nand_cycles_t_wc=11 | pcw_nand_cycles_t_wp=1 | pcw_nand_grp_d8_enable=0 | pcw_nand_peripheral_enable=0
pcw_nor_cs0_t_ceoe=1 | pcw_nor_cs0_t_pc=1 | pcw_nor_cs0_t_rc=11 | pcw_nor_cs0_t_tr=1
pcw_nor_cs0_t_wc=11 | pcw_nor_cs0_t_wp=1 | pcw_nor_cs0_we_time=0 | pcw_nor_cs1_t_ceoe=1
pcw_nor_cs1_t_pc=1 | pcw_nor_cs1_t_rc=11 | pcw_nor_cs1_t_tr=1 | pcw_nor_cs1_t_wc=11
pcw_nor_cs1_t_wp=1 | pcw_nor_cs1_we_time=0 | pcw_nor_grp_a25_enable=0 | pcw_nor_grp_cs0_enable=0
pcw_nor_grp_cs1_enable=0 | pcw_nor_grp_sram_cs0_enable=0 | pcw_nor_grp_sram_cs1_enable=0 | pcw_nor_grp_sram_int_enable=0
pcw_nor_peripheral_enable=0 | pcw_nor_sram_cs0_t_ceoe=1 | pcw_nor_sram_cs0_t_pc=1 | pcw_nor_sram_cs0_t_rc=11
pcw_nor_sram_cs0_t_tr=1 | pcw_nor_sram_cs0_t_wc=11 | pcw_nor_sram_cs0_t_wp=1 | pcw_nor_sram_cs0_we_time=0
pcw_nor_sram_cs1_t_ceoe=1 | pcw_nor_sram_cs1_t_pc=1 | pcw_nor_sram_cs1_t_rc=11 | pcw_nor_sram_cs1_t_tr=1
pcw_nor_sram_cs1_t_wc=11 | pcw_nor_sram_cs1_t_wp=1 | pcw_nor_sram_cs1_we_time=0 | pcw_override_basic_clock=0
pcw_pcap_peripheral_clksrc=IO PLL | pcw_pcap_peripheral_freqmhz=200 | pcw_pjtag_peripheral_enable=0 | pcw_preset_bank0_voltage=LVCMOS 3.3V
pcw_preset_bank1_voltage=LVCMOS 1.8V | pcw_qspi_grp_fbclk_enable=1 | pcw_qspi_grp_fbclk_io=MIO 8 | pcw_qspi_grp_io1_enable=0
pcw_qspi_grp_single_ss_enable=1 | pcw_qspi_grp_single_ss_io=MIO 1 .. 6 | pcw_qspi_grp_ss1_enable=0 | pcw_qspi_internal_highaddress=0xFCFFFFFF
pcw_qspi_peripheral_clksrc=IO PLL | pcw_qspi_peripheral_enable=1 | pcw_qspi_peripheral_freqmhz=200 | pcw_qspi_qspi_io=MIO 1 .. 6
pcw_s_axi_acp_freqmhz=10 | pcw_s_axi_gp0_freqmhz=10 | pcw_s_axi_gp1_freqmhz=10 | pcw_s_axi_hp0_data_width=64
pcw_s_axi_hp0_freqmhz=100 | pcw_s_axi_hp1_data_width=64 | pcw_s_axi_hp1_freqmhz=100 | pcw_s_axi_hp2_data_width=64
pcw_s_axi_hp2_freqmhz=10 | pcw_s_axi_hp3_data_width=64 | pcw_s_axi_hp3_freqmhz=10 | pcw_sd0_grp_cd_enable=1
pcw_sd0_grp_cd_io=MIO 47 | pcw_sd0_grp_pow_enable=0 | pcw_sd0_grp_wp_enable=1 | pcw_sd0_grp_wp_io=EMIO
pcw_sd0_peripheral_enable=1 | pcw_sd0_sd0_io=MIO 40 .. 45 | pcw_sd1_grp_cd_enable=0 | pcw_sd1_grp_pow_enable=0
pcw_sd1_grp_wp_enable=0 | pcw_sd1_peripheral_enable=0 | pcw_sdio_peripheral_clksrc=IO PLL | pcw_sdio_peripheral_freqmhz=50
pcw_smc_peripheral_clksrc=IO PLL | pcw_smc_peripheral_freqmhz=100 | pcw_spi0_grp_ss0_enable=0 | pcw_spi0_grp_ss1_enable=0
pcw_spi0_grp_ss2_enable=0 | pcw_spi0_peripheral_enable=0 | pcw_spi1_grp_ss0_enable=0 | pcw_spi1_grp_ss1_enable=0
pcw_spi1_grp_ss2_enable=0 | pcw_spi1_peripheral_enable=0 | pcw_spi_peripheral_clksrc=IO PLL | pcw_spi_peripheral_freqmhz=166.666666
pcw_tpiu_peripheral_clksrc=External | pcw_tpiu_peripheral_freqmhz=200 | pcw_trace_grp_16bit_enable=0 | pcw_trace_grp_2bit_enable=0
pcw_trace_grp_32bit_enable=0 | pcw_trace_grp_4bit_enable=0 | pcw_trace_grp_8bit_enable=0 | pcw_trace_peripheral_enable=0
pcw_ttc0_clk0_peripheral_clksrc=CPU_1X | pcw_ttc0_clk0_peripheral_freqmhz=133.333333 | pcw_ttc0_clk1_peripheral_clksrc=CPU_1X | pcw_ttc0_clk1_peripheral_freqmhz=133.333333
pcw_ttc0_clk2_peripheral_clksrc=CPU_1X | pcw_ttc0_clk2_peripheral_freqmhz=133.333333 | pcw_ttc0_peripheral_enable=1 | pcw_ttc0_ttc0_io=EMIO
pcw_ttc1_clk0_peripheral_clksrc=CPU_1X | pcw_ttc1_clk0_peripheral_freqmhz=133.333333 | pcw_ttc1_clk1_peripheral_clksrc=CPU_1X | pcw_ttc1_clk1_peripheral_freqmhz=133.333333
pcw_ttc1_clk2_peripheral_clksrc=CPU_1X | pcw_ttc1_clk2_peripheral_freqmhz=133.333333 | pcw_ttc1_peripheral_enable=0 | pcw_ttc_peripheral_freqmhz=50
pcw_uart0_baud_rate=115200 | pcw_uart0_grp_full_enable=0 | pcw_uart0_peripheral_enable=0 | pcw_uart1_baud_rate=115200
pcw_uart1_grp_full_enable=0 | pcw_uart1_peripheral_enable=1 | pcw_uart1_uart1_io=MIO 48 .. 49 | pcw_uart_peripheral_clksrc=IO PLL
pcw_uart_peripheral_freqmhz=100 | pcw_uiparam_ddr_adv_enable=0 | pcw_uiparam_ddr_al=0 | pcw_uiparam_ddr_bank_addr_count=3
pcw_uiparam_ddr_bl=8 | pcw_uiparam_ddr_board_delay0=0.176 | pcw_uiparam_ddr_board_delay1=0.159 | pcw_uiparam_ddr_board_delay2=0.162
pcw_uiparam_ddr_board_delay3=0.187 | pcw_uiparam_ddr_bus_width=32 Bit | pcw_uiparam_ddr_cl=7 | pcw_uiparam_ddr_clock_0_length_mm=0
pcw_uiparam_ddr_clock_0_package_length=54.563 | pcw_uiparam_ddr_clock_0_propogation_delay=160 | pcw_uiparam_ddr_clock_1_length_mm=0 | pcw_uiparam_ddr_clock_1_package_length=54.563
pcw_uiparam_ddr_clock_1_propogation_delay=160 | pcw_uiparam_ddr_clock_2_length_mm=0 | pcw_uiparam_ddr_clock_2_package_length=54.563 | pcw_uiparam_ddr_clock_2_propogation_delay=160
pcw_uiparam_ddr_clock_3_length_mm=0 | pcw_uiparam_ddr_clock_3_package_length=54.563 | pcw_uiparam_ddr_clock_3_propogation_delay=160 | pcw_uiparam_ddr_clock_stop_en=0
pcw_uiparam_ddr_col_addr_count=10 | pcw_uiparam_ddr_cwl=6 | pcw_uiparam_ddr_device_capacity=2048 MBits | pcw_uiparam_ddr_dq_0_length_mm=0
pcw_uiparam_ddr_dq_0_package_length=104.5365 | pcw_uiparam_ddr_dq_0_propogation_delay=160 | pcw_uiparam_ddr_dq_1_length_mm=0 | pcw_uiparam_ddr_dq_1_package_length=70.676
pcw_uiparam_ddr_dq_1_propogation_delay=160 | pcw_uiparam_ddr_dq_2_length_mm=0 | pcw_uiparam_ddr_dq_2_package_length=59.1615 | pcw_uiparam_ddr_dq_2_propogation_delay=160
pcw_uiparam_ddr_dq_3_length_mm=0 | pcw_uiparam_ddr_dq_3_package_length=81.319 | pcw_uiparam_ddr_dq_3_propogation_delay=160 | pcw_uiparam_ddr_dqs_0_length_mm=0
pcw_uiparam_ddr_dqs_0_package_length=101.239 | pcw_uiparam_ddr_dqs_0_propogation_delay=160 | pcw_uiparam_ddr_dqs_1_length_mm=0 | pcw_uiparam_ddr_dqs_1_package_length=79.5025
pcw_uiparam_ddr_dqs_1_propogation_delay=160 | pcw_uiparam_ddr_dqs_2_length_mm=0 | pcw_uiparam_ddr_dqs_2_package_length=60.536 | pcw_uiparam_ddr_dqs_2_propogation_delay=160
pcw_uiparam_ddr_dqs_3_length_mm=0 | pcw_uiparam_ddr_dqs_3_package_length=71.7715 | pcw_uiparam_ddr_dqs_3_propogation_delay=160 | pcw_uiparam_ddr_dqs_to_clk_delay_0=-0.073
pcw_uiparam_ddr_dqs_to_clk_delay_1=-0.034 | pcw_uiparam_ddr_dqs_to_clk_delay_2=-0.03 | pcw_uiparam_ddr_dqs_to_clk_delay_3=-0.082 | pcw_uiparam_ddr_dram_width=16 Bits
pcw_uiparam_ddr_ecc=Disabled | pcw_uiparam_ddr_enable=1 | pcw_uiparam_ddr_freq_mhz=525 | pcw_uiparam_ddr_high_temp=Normal (0-85)
pcw_uiparam_ddr_memory_type=DDR 3 | pcw_uiparam_ddr_partno=MT41K128M16 JT-125 | pcw_uiparam_ddr_row_addr_count=14 | pcw_uiparam_ddr_speed_bin=DDR3_1066F
pcw_uiparam_ddr_t_faw=40.0 | pcw_uiparam_ddr_t_ras_min=35.0 | pcw_uiparam_ddr_t_rc=48.75 | pcw_uiparam_ddr_t_rcd=7
pcw_uiparam_ddr_t_rp=7 | pcw_uiparam_ddr_train_data_eye=1 | pcw_uiparam_ddr_train_read_gate=1 | pcw_uiparam_ddr_train_write_level=1
pcw_uiparam_ddr_use_internal_vref=0 | pcw_usb0_peripheral_enable=1 | pcw_usb0_peripheral_freqmhz=60 | pcw_usb0_reset_enable=0
pcw_usb0_usb0_io=MIO 28 .. 39 | pcw_usb1_peripheral_enable=0 | pcw_usb1_peripheral_freqmhz=60 | pcw_usb1_reset_enable=0
pcw_usb_reset_polarity=Active Low | pcw_use_cross_trigger=0 | pcw_use_m_axi_gp0=1 | pcw_use_m_axi_gp1=0
pcw_use_s_axi_acp=0 | pcw_use_s_axi_gp0=0 | pcw_use_s_axi_gp1=0 | pcw_use_s_axi_hp0=1
pcw_use_s_axi_hp1=1 | pcw_use_s_axi_hp2=0 | pcw_use_s_axi_hp3=0 | pcw_wdt_peripheral_clksrc=CPU_1X
pcw_wdt_peripheral_enable=0 | pcw_wdt_peripheral_freqmhz=133.333333
processing_system7_v5_5_processing_system7/1
c_dm_width=4 | c_dq_width=32 | c_dqs_width=4 | c_emio_gpio_width=64
c_en_emio_enet0=0 | c_en_emio_enet1=0 | c_en_emio_pjtag=0 | c_en_emio_trace=0
c_fclk_clk0_buf=TRUE | c_fclk_clk1_buf=TRUE | c_fclk_clk2_buf=TRUE | c_fclk_clk3_buf=FALSE
c_gp0_en_modifiable_txn=1 | c_gp1_en_modifiable_txn=1 | c_include_acp_trans_check=0 | c_include_trace_buffer=0
c_irq_f2p_mode=DIRECT | c_m_axi_gp0_enable_static_remap=0 | c_m_axi_gp0_id_width=12 | c_m_axi_gp0_thread_id_width=12
c_m_axi_gp1_enable_static_remap=0 | c_m_axi_gp1_id_width=12 | c_m_axi_gp1_thread_id_width=12 | c_mio_primitive=54
c_num_f2p_intr_inputs=1 | c_package_name=clg400 | c_ps7_si_rev=PRODUCTION | c_s_axi_acp_aruser_val=31
c_s_axi_acp_awuser_val=31 | c_s_axi_acp_id_width=3 | c_s_axi_gp0_id_width=6 | c_s_axi_gp1_id_width=6
c_s_axi_hp0_data_width=64 | c_s_axi_hp0_id_width=6 | c_s_axi_hp1_data_width=64 | c_s_axi_hp1_id_width=6
c_s_axi_hp2_data_width=64 | c_s_axi_hp2_id_width=6 | c_s_axi_hp3_data_width=64 | c_s_axi_hp3_id_width=6
c_trace_buffer_clock_delay=12 | c_trace_buffer_fifo_size=128 | c_trace_internal_width=2 | c_trace_pipeline_width=8
c_use_axi_nonsecure=0 | c_use_default_acp_user_val=0 | c_use_m_axi_gp0=1 | c_use_m_axi_gp1=0
c_use_s_axi_acp=0 | c_use_s_axi_gp0=0 | c_use_s_axi_hp0=1 | c_use_s_axi_hp1=1
c_use_s_axi_hp2=0 | c_use_s_axi_hp3=0 | core_container=NA | iptotal=1
use_trace_data_edge_detector=0 | x_ipcorerevision=5 | x_iplanguage=VERILOG | x_iplibrary=ip
x_ipname=processing_system7 | x_ipproduct=Vivado 2017.2.1 | x_ipsimlanguage=MIXED | x_ipvendor=xilinx.com
x_ipversion=5.5
sc_exit_v1_0_4_top/1
c_addr_width=32 | c_enable_pipelining=0x1 | c_family=zynq | c_has_lock=0
c_is_cascaded=0 | c_m_aruser_width=0 | c_m_awuser_width=0 | c_m_buser_width=0
c_m_id_width=0 | c_m_protocol=1 | c_m_ruser_bits_per_byte=0 | c_m_ruser_width=0
c_m_wuser_bits_per_byte=0 | c_m_wuser_width=0 | c_max_ruser_bits_per_byte=0 | c_max_wuser_bits_per_byte=0
c_mep_identifier_width=2 | c_num_msc=1 | c_rdata_width=64 | c_read_acceptance=1
c_s_id_width=2 | c_ssc_route_array=0b0001 | c_ssc_route_width=1 | c_wdata_width=64
c_write_acceptance=1 | core_container=NA | iptotal=1 | x_ipcorerevision=4
x_iplanguage=VERILOG | x_iplibrary=ip | x_ipname=sc_exit | x_ipproduct=Vivado 2017.2.1
x_ipsimlanguage=MIXED | x_ipvendor=xilinx.com | x_ipversion=1.0
sc_exit_v1_0_4_top/2
c_addr_width=32 | c_enable_pipelining=0x1 | c_family=zynq | c_has_lock=0
c_is_cascaded=0 | c_m_aruser_width=0 | c_m_awuser_width=0 | c_m_buser_width=0
c_m_id_width=0 | c_m_protocol=1 | c_m_ruser_bits_per_byte=0 | c_m_ruser_width=0
c_m_wuser_bits_per_byte=0 | c_m_wuser_width=0 | c_max_ruser_bits_per_byte=0 | c_max_wuser_bits_per_byte=0
c_mep_identifier_width=2 | c_num_msc=1 | c_rdata_width=64 | c_read_acceptance=1
c_s_id_width=2 | c_ssc_route_array=0b0010 | c_ssc_route_width=1 | c_wdata_width=64
c_write_acceptance=1 | core_container=NA | iptotal=1 | x_ipcorerevision=4
x_iplanguage=VERILOG | x_iplibrary=ip | x_ipname=sc_exit | x_ipproduct=Vivado 2017.2.1
x_ipsimlanguage=MIXED | x_ipvendor=xilinx.com | x_ipversion=1.0
sc_mmu_v1_0_4_top/1
c_addr_width=32 | c_enable_pipelining=0x1 | c_family=zynq | c_id_width=0
c_is_cascaded=0 | c_msc_route_array=0b1 | c_msc_route_width=1 | c_num_msc=1
c_num_seg=1 | c_rdata_width=64 | c_read_acceptance=32 | c_s_aruser_width=0
c_s_awuser_width=0 | c_s_buser_width=0 | c_s_protocol=0 | c_s_ruser_width=0
c_s_wuser_width=0 | c_seg_base_addr_array=0x0000000000000000 | c_seg_secure_read_array=0b0 | c_seg_secure_write_array=0b0
c_seg_sep_route_array=0x0000000000000000 | c_seg_size_array=0x0000001d | c_seg_supports_read_array=0x1 | c_seg_supports_write_array=0x1
c_supports_read_decerr=1 | c_supports_wrap=1 | c_supports_write_decerr=1 | c_wdata_width=64
c_write_acceptance=32 | core_container=NA | iptotal=1 | x_ipcorerevision=4
x_iplanguage=VERILOG | x_iplibrary=ip | x_ipname=sc_mmu | x_ipproduct=Vivado 2017.2.1
x_ipsimlanguage=MIXED | x_ipvendor=xilinx.com | x_ipversion=1.0
sc_mmu_v1_0_4_top/2
c_addr_width=32 | c_enable_pipelining=0x1 | c_family=zynq | c_id_width=0
c_is_cascaded=0 | c_msc_route_array=0b1 | c_msc_route_width=1 | c_num_msc=1
c_num_seg=1 | c_rdata_width=64 | c_read_acceptance=32 | c_s_aruser_width=0
c_s_awuser_width=0 | c_s_buser_width=0 | c_s_protocol=0 | c_s_ruser_width=0
c_s_wuser_width=0 | c_seg_base_addr_array=0x0000000000000000 | c_seg_secure_read_array=0b0 | c_seg_secure_write_array=0b0
c_seg_sep_route_array=0x0000000000000000 | c_seg_size_array=0x0000001d | c_seg_supports_read_array=0x1 | c_seg_supports_write_array=0x1
c_supports_read_decerr=1 | c_supports_wrap=1 | c_supports_write_decerr=1 | c_wdata_width=64
c_write_acceptance=32 | core_container=NA | iptotal=1 | x_ipcorerevision=4
x_iplanguage=VERILOG | x_iplibrary=ip | x_ipname=sc_mmu | x_ipproduct=Vivado 2017.2.1
x_ipsimlanguage=MIXED | x_ipvendor=xilinx.com | x_ipversion=1.0
sc_node_v1_0_5_top/1
c_aclk_relationship=1 | c_aclken_conversion=0 | c_addr_width=32 | c_arbiter_mode=1
c_channel=2 | c_disable_ip=0 | c_enable_pipelining=0x01 | c_family=zynq
c_fifo_ip=0 | c_fifo_size=5 | c_fifo_type=0 | c_id_width=2
c_m_num_bytes_array=0x00000008 | c_m_pipeline=0 | c_m_send_pipeline=0 | c_max_payld_bytes=8
c_num_mi=1 | c_num_si=1 | c_payld_width=140 | c_s_latency=0
c_s_num_bytes_array=0x00000008 | c_s_pipeline=0 | c_sc_route_width=1 | c_synchronization_stages=2
c_user_bits_per_byte=0 | c_user_width=0 | core_container=NA | iptotal=1
x_ipcorerevision=5 | x_iplanguage=VERILOG | x_iplibrary=ip | x_ipname=sc_node
x_ipproduct=Vivado 2017.2.1 | x_ipsimlanguage=MIXED | x_ipvendor=xilinx.com | x_ipversion=1.0
sc_node_v1_0_5_top/2
c_aclk_relationship=1 | c_aclken_conversion=0 | c_addr_width=32 | c_arbiter_mode=1
c_channel=0 | c_disable_ip=0 | c_enable_pipelining=0x01 | c_family=zynq
c_fifo_ip=0 | c_fifo_size=5 | c_fifo_type=0 | c_id_width=2
c_m_num_bytes_array=0x00000008 | c_m_pipeline=0 | c_m_send_pipeline=0 | c_max_payld_bytes=8
c_num_mi=1 | c_num_si=1 | c_payld_width=84 | c_s_latency=0
c_s_num_bytes_array=0x00000008 | c_s_pipeline=0 | c_sc_route_width=1 | c_synchronization_stages=2
c_user_bits_per_byte=0 | c_user_width=512 | core_container=NA | iptotal=1
x_ipcorerevision=5 | x_iplanguage=VERILOG | x_iplibrary=ip | x_ipname=sc_node
x_ipproduct=Vivado 2017.2.1 | x_ipsimlanguage=MIXED | x_ipvendor=xilinx.com | x_ipversion=1.0
sc_node_v1_0_5_top/3
c_aclk_relationship=1 | c_aclken_conversion=0 | c_addr_width=32 | c_arbiter_mode=1
c_channel=3 | c_disable_ip=0 | c_enable_pipelining=0x01 | c_family=zynq
c_fifo_ip=0 | c_fifo_size=5 | c_fifo_type=0 | c_id_width=2
c_m_num_bytes_array=0x00000008 | c_m_pipeline=0 | c_m_send_pipeline=0 | c_max_payld_bytes=8
c_num_mi=1 | c_num_si=1 | c_payld_width=140 | c_s_latency=0
c_s_num_bytes_array=0x00000008 | c_s_pipeline=0 | c_sc_route_width=1 | c_synchronization_stages=2
c_user_bits_per_byte=0 | c_user_width=0 | core_container=NA | iptotal=1
x_ipcorerevision=5 | x_iplanguage=VERILOG | x_iplibrary=ip | x_ipname=sc_node
x_ipproduct=Vivado 2017.2.1 | x_ipsimlanguage=MIXED | x_ipvendor=xilinx.com | x_ipversion=1.0
sc_node_v1_0_5_top/4
c_aclk_relationship=1 | c_aclken_conversion=0 | c_addr_width=32 | c_arbiter_mode=1
c_channel=4 | c_disable_ip=0 | c_enable_pipelining=0x01 | c_family=zynq
c_fifo_ip=0 | c_fifo_size=5 | c_fifo_type=0 | c_id_width=2
c_m_num_bytes_array=0x00000008 | c_m_pipeline=0 | c_m_send_pipeline=0 | c_max_payld_bytes=8
c_num_mi=1 | c_num_si=1 | c_payld_width=6 | c_s_latency=0
c_s_num_bytes_array=0x00000008 | c_s_pipeline=0 | c_sc_route_width=1 | c_synchronization_stages=2
c_user_bits_per_byte=0 | c_user_width=0 | core_container=NA | iptotal=1
x_ipcorerevision=5 | x_iplanguage=VERILOG | x_iplibrary=ip | x_ipname=sc_node
x_ipproduct=Vivado 2017.2.1 | x_ipsimlanguage=MIXED | x_ipvendor=xilinx.com | x_ipversion=1.0
sc_node_v1_0_5_top/5
c_aclk_relationship=1 | c_aclken_conversion=0 | c_addr_width=32 | c_arbiter_mode=1
c_channel=1 | c_disable_ip=0 | c_enable_pipelining=0x01 | c_family=zynq
c_fifo_ip=0 | c_fifo_size=5 | c_fifo_type=0 | c_id_width=2
c_m_num_bytes_array=0x00000008 | c_m_pipeline=0 | c_m_send_pipeline=0 | c_max_payld_bytes=8
c_num_mi=1 | c_num_si=1 | c_payld_width=88 | c_s_latency=0
c_s_num_bytes_array=0x00000008 | c_s_pipeline=0 | c_sc_route_width=1 | c_synchronization_stages=2
c_user_bits_per_byte=0 | c_user_width=512 | core_container=NA | iptotal=1
x_ipcorerevision=5 | x_iplanguage=VERILOG | x_iplibrary=ip | x_ipname=sc_node
x_ipproduct=Vivado 2017.2.1 | x_ipsimlanguage=MIXED | x_ipvendor=xilinx.com | x_ipversion=1.0
sc_si_converter_v1_0_4_top/1
c_addr_width=32 | c_enable_pipelining=0x1 | c_has_burst=0 | c_id_width=2
c_is_cascaded=0 | c_limit_read_length=0 | c_limit_write_length=0 | c_max_ruser_bits_per_byte=0
c_max_wuser_bits_per_byte=0 | c_mep_identifier_width=2 | c_msc_rdata_width_array=0x00000040 | c_msc_wdata_width_array=0x00000040
c_num_msc=1 | c_num_read_threads=1 | c_num_seg=1 | c_num_write_threads=1
c_rdata_width=64 | c_read_acceptance=32 | c_read_watermark=0 | c_s_ruser_bits_per_byte=0
c_s_wuser_bits_per_byte=0 | c_sep_protocol_array=0x00000001 | c_sep_rdata_width_array=0x00000040 | c_sep_wdata_width_array=0x00000040
c_supports_narrow=0 | c_wdata_width=64 | c_write_acceptance=32 | c_write_watermark=0
core_container=NA | iptotal=1 | x_ipcorerevision=4 | x_iplanguage=VERILOG
x_iplibrary=ip | x_ipname=sc_si_converter | x_ipproduct=Vivado 2017.2.1 | x_ipsimlanguage=MIXED
x_ipvendor=xilinx.com | x_ipversion=1.0
sc_si_converter_v1_0_4_top/2
c_addr_width=32 | c_enable_pipelining=0x1 | c_has_burst=0 | c_id_width=2
c_is_cascaded=0 | c_limit_read_length=0 | c_limit_write_length=0 | c_max_ruser_bits_per_byte=0
c_max_wuser_bits_per_byte=0 | c_mep_identifier_width=2 | c_msc_rdata_width_array=0x00000040 | c_msc_wdata_width_array=0x00000040
c_num_msc=1 | c_num_read_threads=1 | c_num_seg=1 | c_num_write_threads=1
c_rdata_width=64 | c_read_acceptance=32 | c_read_watermark=0 | c_s_ruser_bits_per_byte=0
c_s_wuser_bits_per_byte=0 | c_sep_protocol_array=0x00000001 | c_sep_rdata_width_array=0x00000040 | c_sep_wdata_width_array=0x00000040
c_supports_narrow=0 | c_wdata_width=64 | c_write_acceptance=32 | c_write_watermark=0
core_container=NA | iptotal=1 | x_ipcorerevision=4 | x_iplanguage=VERILOG
x_iplibrary=ip | x_ipname=sc_si_converter | x_ipproduct=Vivado 2017.2.1 | x_ipsimlanguage=MIXED
x_ipvendor=xilinx.com | x_ipversion=1.0
v_axi4s_vid_out_v4_0_6/1
c_addr_width=10 | c_addr_width_pixel_remap_420=10 | c_components_per_pixel=3 | c_family=zynq
c_has_async_clk=1 | c_hysteresis_level=12 | c_include_pixel_remap_420=0 | c_include_pixel_repeat=0
c_native_component_width=8 | c_native_data_width=24 | c_pixels_per_clock=1 | c_s_axis_component_width=8
c_s_axis_tdata_width=24 | c_sync_lock_threshold=4 | c_vtg_master_slave=1 | core_container=false
iptotal=1 | x_ipcorerevision=6 | x_iplanguage=VERILOG | x_iplibrary=ip
x_ipname=v_axi4s_vid_out | x_ipproduct=Vivado 2017.2.1 | x_ipsimlanguage=MIXED | x_ipvendor=xilinx.com
x_ipversion=4.0
v_tc/1
c_det_achroma_en=0 | c_det_avideo_en=1 | c_det_fieldid_en=0 | c_det_hblank_en=1
c_det_hsync_en=1 | c_det_vblank_en=1 | c_det_vsync_en=1 | c_detect_en=0
c_fsync_hstart0=0 | c_fsync_hstart1=0 | c_fsync_hstart10=0 | c_fsync_hstart11=0
c_fsync_hstart12=0 | c_fsync_hstart13=0 | c_fsync_hstart14=0 | c_fsync_hstart15=0
c_fsync_hstart2=0 | c_fsync_hstart3=0 | c_fsync_hstart4=0 | c_fsync_hstart5=0
c_fsync_hstart6=0 | c_fsync_hstart7=0 | c_fsync_hstart8=0 | c_fsync_hstart9=0
c_fsync_vstart0=0 | c_fsync_vstart1=0 | c_fsync_vstart10=0 | c_fsync_vstart11=0
c_fsync_vstart12=0 | c_fsync_vstart13=0 | c_fsync_vstart14=0 | c_fsync_vstart15=0
c_fsync_vstart2=0 | c_fsync_vstart3=0 | c_fsync_vstart4=0 | c_fsync_vstart5=0
c_fsync_vstart6=0 | c_fsync_vstart7=0 | c_fsync_vstart8=0 | c_fsync_vstart9=0
c_gen_achroma_en=0 | c_gen_achroma_polarity=1 | c_gen_auto_switch=0 | c_gen_avideo_en=1
c_gen_avideo_polarity=1 | c_gen_cparity=0 | c_gen_f0_vblank_hend=640 | c_gen_f0_vblank_hstart=640
c_gen_f0_vframe_size=525 | c_gen_f0_vsync_hend=640 | c_gen_f0_vsync_hstart=640 | c_gen_f0_vsync_vend=491
c_gen_f0_vsync_vstart=489 | c_gen_f1_vblank_hend=640 | c_gen_f1_vblank_hstart=640 | c_gen_f1_vframe_size=525
c_gen_f1_vsync_hend=640 | c_gen_f1_vsync_hstart=640 | c_gen_f1_vsync_vend=491 | c_gen_f1_vsync_vstart=489
c_gen_fieldid_en=0 | c_gen_fieldid_polarity=1 | c_gen_hactive_size=640 | c_gen_hblank_en=1
c_gen_hblank_polarity=1 | c_gen_hframe_size=800 | c_gen_hsync_en=1 | c_gen_hsync_end=752
c_gen_hsync_polarity=1 | c_gen_hsync_start=656 | c_gen_interlaced=0 | c_gen_vactive_size=480
c_gen_vblank_en=1 | c_gen_vblank_polarity=1 | c_gen_video_format=2 | c_gen_vsync_en=1
c_gen_vsync_polarity=1 | c_generate_en=1 | c_has_axi4_lite=0 | c_has_intc_if=0
c_interlace_en=0 | c_max_lines=4096 | c_max_pixels=4096 | c_num_fsyncs=1
c_sync_en=0 | core_container=NA | iptotal=1 | x_ipcorerevision=10
x_iplanguage=VERILOG | x_iplibrary=ip | x_ipname=v_tc | x_ipproduct=Vivado 2017.2.1
x_ipsimlanguage=MIXED | x_ipvendor=xilinx.com | x_ipversion=6.1
xlconstant_v1_1_3_xlconstant/1
const_val=0x1 | const_width=1 | core_container=NA | iptotal=1
x_ipcorerevision=3 | x_iplanguage=VERILOG | x_iplibrary=ip | x_ipname=xlconstant
x_ipproduct=Vivado 2017.2.1 | x_ipsimlanguage=MIXED | x_ipvendor=xilinx.com | x_ipversion=1.1
xlslice_v1_0_1_xlslice/1
core_container=NA | din_from=23 | din_to=19 | din_width=24
iptotal=1 | x_ipcorerevision=1 | x_iplanguage=VERILOG | x_iplibrary=ip
x_ipname=xlslice | x_ipproduct=Vivado 2017.2.1 | x_ipsimlanguage=MIXED | x_ipvendor=xilinx.com
x_ipversion=1.0
xlslice_v1_0_1_xlslice/2
core_container=NA | din_from=15 | din_to=10 | din_width=24
iptotal=1 | x_ipcorerevision=1 | x_iplanguage=VERILOG | x_iplibrary=ip
x_ipname=xlslice | x_ipproduct=Vivado 2017.2.1 | x_ipsimlanguage=MIXED | x_ipvendor=xilinx.com
x_ipversion=1.0
xlslice_v1_0_1_xlslice/3
core_container=NA | din_from=7 | din_to=3 | din_width=24
iptotal=1 | x_ipcorerevision=1 | x_iplanguage=VERILOG | x_iplibrary=ip
x_ipname=xlslice | x_ipproduct=Vivado 2017.2.1 | x_ipsimlanguage=MIXED | x_ipvendor=xilinx.com
x_ipversion=1.0
xpm_cdc_handshake/1
core_container=NA | dest_ext_hsk=1 | dest_sync_ff=2 | iptotal=10
sim_assert_chk=0 | src_sync_ff=2 | version=0 | width=36
xpm_cdc_single/1
core_container=NA | dest_sync_ff=2 | iptotal=20 | sim_assert_chk=0
src_input_reg=0 | version=0
xpm_memory_base/1
version=0 | addr_width_a=5 | addr_width_b=5 | auto_sleep_time=0
byte_write_width_a=102 | byte_write_width_b=102 | clocking_mode=0 | core_container=NA
ecc_mode=0 | iptotal=4 | max_num_char=0 | memory_optimization=1
memory_primitive=1 | memory_size=3264 | memory_type=1 | message_control=0
num_char_loc=0 | p_ecc_mode=no_ecc | p_enable_byte_write_a=0 | p_enable_byte_write_b=0
p_max_depth_data=32 | p_memory_opt=yes | p_memory_primitive=distributed | p_min_width_data=102
p_min_width_data_a=102 | p_min_width_data_b=102 | p_min_width_data_ecc=102 | p_min_width_data_ldw=4
p_min_width_data_shft=102 | p_num_cols_write_a=1 | p_num_cols_write_b=1 | p_num_rows_read_a=1
p_num_rows_read_b=1 | p_num_rows_write_a=1 | p_num_rows_write_b=1 | p_sdp_write_mode=yes
p_width_addr_lsb_read_a=0 | p_width_addr_lsb_read_b=0 | p_width_addr_lsb_write_a=0 | p_width_addr_lsb_write_b=0
p_width_addr_read_a=5 | p_width_addr_read_b=5 | p_width_addr_write_a=5 | p_width_addr_write_b=5
p_width_col_write_a=102 | p_width_col_write_b=102 | read_data_width_a=102 | read_data_width_b=102
read_latency_a=2 | read_latency_b=0 | read_reset_value_a=0 | read_reset_value_b=0
use_mem_init=0 | version=0 | wakeup_time=0 | write_data_width_a=102
write_data_width_b=102 | write_mode_a=0 | write_mode_b=1

report_drc
command_line_options
-append=default::[not_specified] | -checks=default::[not_specified] | -fail_on=default::[not_specified] | -force=default::[not_specified]
-format=default::[not_specified] | -messages=default::[not_specified] | -name=default::[not_specified] | -return_string=default::[not_specified]
-ruledecks=default::[not_specified] | -upgrade_cw=default::[not_specified] | -waived=default::[not_specified]
results
check-3=1 | dpip-1=26 | dpop-1=37 | dpop-2=55
pdrc-153=1 | plck-12=1 | reqp-1839=20 | rpbf-3=1
rtstat-10=1

report_methodology
command_line_options
-append=default::[not_specified] | -checks=default::[not_specified] | -fail_on=default::[not_specified] | -force=default::[not_specified]
-format=default::[not_specified] | -messages=default::[not_specified] | -name=default::[not_specified] | -return_string=default::[not_specified]
-waived=default::[not_specified]
results
timing-17=1000 | timing-18=26 | xdcb-5=2

report_power
command_line_options
-advisory=default::[not_specified] | -append=default::[not_specified] | -file=[specified] | -format=default::text
-hier=default::power | -l=default::[not_specified] | -name=default::[not_specified] | -no_propagation=default::[not_specified]
-return_string=default::[not_specified] | -rpx=[specified] | -verbose=default::[not_specified] | -vid=default::[not_specified]
-xpe=default::[not_specified]
usage
airflow=250 (LFM) | ambient_temp=25.0 (C) | bi-dir_toggle=12.500000 | bidir_output_enable=1.000000
board_layers=8to11 (8 to 11 Layers) | board_selection=medium (10"x10") | bram=0.009671 | clocks=0.016424
confidence_level_clock_activity=Low | confidence_level_design_state=High | confidence_level_device_models=High | confidence_level_internal_activity=Medium
confidence_level_io_activity=Low | confidence_level_overall=Low | customer=TBD | customer_class=TBD
devstatic=0.134125 | die=xc7z010clg400-1 | dsp=0.049272 | dsp_output_toggle=12.500000
dynamic=1.701851 | effective_thetaja=11.5 | enable_probability=0.990000 | family=zynq
ff_toggle=12.500000 | flow_state=routed | heatsink=none | i/o=0.002049
input_toggle=12.500000 | junction_temp=46.2 (C) | logic=0.024330 | mgtavcc_dynamic_current=0.000000
mgtavcc_static_current=0.000000 | mgtavcc_total_current=0.000000 | mgtavcc_voltage=1.000000 | mgtavtt_dynamic_current=0.000000
mgtavtt_static_current=0.000000 | mgtavtt_total_current=0.000000 | mgtavtt_voltage=1.200000 | mgtvccaux_dynamic_current=0.000000
mgtvccaux_static_current=0.000000 | mgtvccaux_total_current=0.000000 | mgtvccaux_voltage=1.800000 | netlist_net_matched=NA
off-chip_power=0.000000 | on-chip_power=1.835975 | output_enable=1.000000 | output_load=5.000000
output_toggle=12.500000 | package=clg400 | pct_clock_constrained=15.000000 | pct_inputs_defined=0
platform=nt64 | process=typical | ps7=1.564751 | ram_enable=50.000000
ram_write=50.000000 | read_saif=False | set/reset_probability=0.000000 | signal_rate=False
signals=0.035354 | simulation_file=None | speedgrade=-1 | static_prob=False
temp_grade=commercial | thetajb=9.3 (C/W) | thetasa=0.0 (C/W) | toggle_rate=False
user_board_temp=25.0 (C) | user_effective_thetaja=11.5 | user_junc_temp=46.2 (C) | user_thetajb=9.3 (C/W)
user_thetasa=0.0 (C/W) | vccadc_dynamic_current=0.000000 | vccadc_static_current=0.020000 | vccadc_total_current=0.020000
vccadc_voltage=1.800000 | vccaux_dynamic_current=0.000074 | vccaux_io_dynamic_current=0.000000 | vccaux_io_static_current=0.000000
vccaux_io_total_current=0.000000 | vccaux_io_voltage=1.800000 | vccaux_static_current=0.011813 | vccaux_total_current=0.011886
vccaux_voltage=1.800000 | vccbram_dynamic_current=0.000351 | vccbram_static_current=0.001338 | vccbram_total_current=0.001689
vccbram_voltage=1.000000 | vccint_dynamic_current=0.134738 | vccint_static_current=0.008241 | vccint_total_current=0.142979
vccint_voltage=1.000000 | vcco12_dynamic_current=0.000000 | vcco12_static_current=0.000000 | vcco12_total_current=0.000000
vcco12_voltage=1.200000 | vcco135_dynamic_current=0.000000 | vcco135_static_current=0.000000 | vcco135_total_current=0.000000
vcco135_voltage=1.350000 | vcco15_dynamic_current=0.000000 | vcco15_static_current=0.000000 | vcco15_total_current=0.000000
vcco15_voltage=1.500000 | vcco18_dynamic_current=0.000000 | vcco18_static_current=0.000000 | vcco18_total_current=0.000000
vcco18_voltage=1.800000 | vcco25_dynamic_current=0.000000 | vcco25_static_current=0.000000 | vcco25_total_current=0.000000
vcco25_voltage=2.500000 | vcco33_dynamic_current=0.000569 | vcco33_static_current=0.001000 | vcco33_total_current=0.001569
vcco33_voltage=3.300000 | vcco_ddr_dynamic_current=0.455616 | vcco_ddr_static_current=0.002000 | vcco_ddr_total_current=0.457616
vcco_ddr_voltage=1.500000 | vcco_mio0_dynamic_current=0.001750 | vcco_mio0_static_current=0.001000 | vcco_mio0_total_current=0.002750
vcco_mio0_voltage=3.300000 | vcco_mio1_dynamic_current=0.002965 | vcco_mio1_static_current=0.001000 | vcco_mio1_total_current=0.003965
vcco_mio1_voltage=1.800000 | vccpaux_dynamic_current=0.074377 | vccpaux_static_current=0.010330 | vccpaux_total_current=0.084707
vccpaux_voltage=1.800000 | vccpint_dynamic_current=0.711588 | vccpint_static_current=0.031889 | vccpint_total_current=0.743477
vccpint_voltage=1.000000 | vccpll_dynamic_current=0.013749 | vccpll_static_current=0.003000 | vccpll_total_current=0.016749
vccpll_voltage=1.800000 | version=2017.2.1

report_utilization
clocking
bufgctrl_available=32 | bufgctrl_fixed=0 | bufgctrl_used=4 | bufgctrl_util_percentage=12.50
bufhce_available=48 | bufhce_fixed=0 | bufhce_used=0 | bufhce_util_percentage=0.00
bufio_available=8 | bufio_fixed=0 | bufio_used=0 | bufio_util_percentage=0.00
bufmrce_available=4 | bufmrce_fixed=0 | bufmrce_used=0 | bufmrce_util_percentage=0.00
bufr_available=8 | bufr_fixed=0 | bufr_used=0 | bufr_util_percentage=0.00
mmcme2_adv_available=2 | mmcme2_adv_fixed=0 | mmcme2_adv_used=0 | mmcme2_adv_util_percentage=0.00
plle2_adv_available=2 | plle2_adv_fixed=0 | plle2_adv_used=0 | plle2_adv_util_percentage=0.00
dsp
dsp48e1_only_used=67 | dsps_available=80 | dsps_fixed=0 | dsps_used=67
dsps_util_percentage=83.75
io_standard
blvds_25=0 | diff_hstl_i=0 | diff_hstl_i_18=0 | diff_hstl_ii=0
diff_hstl_ii_18=0 | diff_hsul_12=0 | diff_mobile_ddr=0 | diff_sstl135=0
diff_sstl135_r=0 | diff_sstl15=1 | diff_sstl15_r=0 | diff_sstl18_i=0
diff_sstl18_ii=0 | hstl_i=0 | hstl_i_18=1 | hstl_ii=0
hstl_ii_18=0 | hsul_12=0 | lvcmos12=0 | lvcmos15=0
lvcmos18=1 | lvcmos25=0 | lvcmos33=1 | lvds_25=0
lvttl=0 | mini_lvds_25=0 | mobile_ddr=0 | pci33_3=0
ppds_25=0 | rsds_25=0 | sstl135=0 | sstl135_r=0
sstl15=1 | sstl15_r=0 | sstl18_i=0 | sstl18_ii=0
tmds_33=0
memory
block_ram_tile_available=60 | block_ram_tile_fixed=0 | block_ram_tile_used=13 | block_ram_tile_util_percentage=21.67
ramb18_available=120 | ramb18_fixed=0 | ramb18_used=16 | ramb18_util_percentage=13.33
ramb18e1_only_used=16 | ramb36_fifo_available=60 | ramb36_fifo_fixed=0 | ramb36_fifo_used=5
ramb36_fifo_util_percentage=8.33 | ramb36e1_only_used=5
primitives
bibuf_functional_category=IO | bibuf_used=130 | bufg_functional_category=Clock | bufg_used=4
carry4_functional_category=CarryLogic | carry4_used=523 | dsp48e1_functional_category=Block Arithmetic | dsp48e1_used=67
fdce_functional_category=Flop & Latch | fdce_used=141 | fdpe_functional_category=Flop & Latch | fdpe_used=27
fdre_functional_category=Flop & Latch | fdre_used=9767 | fdse_functional_category=Flop & Latch | fdse_used=275
ibuf_functional_category=IO | ibuf_used=13 | lut1_functional_category=LUT | lut1_used=234
lut2_functional_category=LUT | lut2_used=1238 | lut3_functional_category=LUT | lut3_used=1924
lut4_functional_category=LUT | lut4_used=1918 | lut5_functional_category=LUT | lut5_used=1252
lut6_functional_category=LUT | lut6_used=2187 | muxf7_functional_category=MuxFx | muxf7_used=170
muxf8_functional_category=MuxFx | muxf8_used=82 | obuf_functional_category=IO | obuf_used=26
ps7_functional_category=Specialized Resource | ps7_used=1 | ramb18e1_functional_category=Block Memory | ramb18e1_used=16
ramb36e1_functional_category=Block Memory | ramb36e1_used=5 | ramd32_functional_category=Distributed Memory | ramd32_used=276
rams32_functional_category=Distributed Memory | rams32_used=92 | srl16e_functional_category=Distributed Memory | srl16e_used=99
srlc32e_functional_category=Distributed Memory | srlc32e_used=393
slice_logic
f7_muxes_available=8800 | f7_muxes_fixed=0 | f7_muxes_used=170 | f7_muxes_util_percentage=1.93
f8_muxes_available=4400 | f8_muxes_fixed=0 | f8_muxes_used=82 | f8_muxes_util_percentage=1.86
lut_as_distributed_ram_fixed=0 | lut_as_distributed_ram_used=184 | lut_as_logic_available=17600 | lut_as_logic_fixed=0
lut_as_logic_used=7317 | lut_as_logic_util_percentage=41.57 | lut_as_memory_available=6000 | lut_as_memory_fixed=0
lut_as_memory_used=655 | lut_as_memory_util_percentage=10.92 | lut_as_shift_register_fixed=0 | lut_as_shift_register_used=471
register_as_flip_flop_available=35200 | register_as_flip_flop_fixed=0 | register_as_flip_flop_used=10210 | register_as_flip_flop_util_percentage=29.01
register_as_latch_available=35200 | register_as_latch_fixed=0 | register_as_latch_used=0 | register_as_latch_util_percentage=0.00
slice_luts_available=17600 | slice_luts_fixed=0 | slice_luts_used=7972 | slice_luts_util_percentage=45.30
slice_registers_available=35200 | slice_registers_fixed=0 | slice_registers_used=10210 | slice_registers_util_percentage=29.01
fully_used_lut_ff_pairs_fixed=29.01 | fully_used_lut_ff_pairs_used=815 | lut_as_distributed_ram_fixed=0 | lut_as_distributed_ram_used=184
lut_as_logic_available=17600 | lut_as_logic_fixed=0 | lut_as_logic_used=7317 | lut_as_logic_util_percentage=41.57
lut_as_memory_available=6000 | lut_as_memory_fixed=0 | lut_as_memory_used=655 | lut_as_memory_util_percentage=10.92
lut_as_shift_register_fixed=0 | lut_as_shift_register_used=471 | lut_ff_pairs_with_one_unused_flip_flop_fixed=471 | lut_ff_pairs_with_one_unused_flip_flop_used=3293
lut_ff_pairs_with_one_unused_lut_output_fixed=3293 | lut_ff_pairs_with_one_unused_lut_output_used=3343 | lut_flip_flop_pairs_available=17600 | lut_flip_flop_pairs_fixed=0
lut_flip_flop_pairs_used=4380 | lut_flip_flop_pairs_util_percentage=24.89 | slice_available=4400 | slice_fixed=0
slice_used=3339 | slice_util_percentage=75.89 | slicel_fixed=0 | slicel_used=2166
slicem_fixed=0 | slicem_used=1173 | unique_control_sets_used=404 | using_o5_and_o6_fixed=404
using_o5_and_o6_used=21 | using_o5_output_only_fixed=21 | using_o5_output_only_used=32 | using_o6_output_only_fixed=32
using_o6_output_only_used=418
specific_feature
bscane2_available=4 | bscane2_fixed=0 | bscane2_used=0 | bscane2_util_percentage=0.00
capturee2_available=1 | capturee2_fixed=0 | capturee2_used=0 | capturee2_util_percentage=0.00
dna_port_available=1 | dna_port_fixed=0 | dna_port_used=0 | dna_port_util_percentage=0.00
efuse_usr_available=1 | efuse_usr_fixed=0 | efuse_usr_used=0 | efuse_usr_util_percentage=0.00
frame_ecce2_available=1 | frame_ecce2_fixed=0 | frame_ecce2_used=0 | frame_ecce2_util_percentage=0.00
icape2_available=2 | icape2_fixed=0 | icape2_used=0 | icape2_util_percentage=0.00
startupe2_available=1 | startupe2_fixed=0 | startupe2_used=0 | startupe2_util_percentage=0.00
xadc_available=1 | xadc_fixed=0 | xadc_used=0 | xadc_util_percentage=0.00

router
usage
actual_expansions=7538009 | bogomips=0 | bram18=16 | bram36=5
bufg=0 | bufr=0 | congestion_level=0 | ctrls=404
dsp=67 | effort=2 | estimated_expansions=14393934 | ff=10210
global_clocks=4 | high_fanout_nets=9 | iob=39 | lut=8482
movable_instances=21674 | nets=28697 | pins=150550 | pll=0
router_runtime=0.000000 | router_timing_driven=1 | threads=2 | timing_constraints_exist=1

synthesis
command_line_options
-assert=default::[not_specified] | -bufg=default::12 | -cascade_dsp=default::auto | -constrset=default::[not_specified]
-control_set_opt_threshold=default::auto | -directive=default::default | -fanout_limit=default::10000 | -flatten_hierarchy=default::rebuilt
-fsm_extraction=default::auto | -gated_clock_conversion=default::off | -generic=default::[not_specified] | -include_dirs=default::[not_specified]
-keep_equivalent_registers=default::[not_specified] | -max_bram=default::-1 | -max_bram_cascade_height=default::-1 | -max_dsp=default::-1
-max_uram=default::-1 | -max_uram_cascade_height=default::-1 | -mode=default::default | -name=default::[not_specified]
-no_lc=default::[not_specified] | -no_srlextract=default::[not_specified] | -no_timing_driven=default::[not_specified] | -part=xc7z010clg400-1
-resource_sharing=default::auto | -retiming=default::[not_specified] | -rtl=default::[not_specified] | -rtl_skip_constraints=default::[not_specified]
-rtl_skip_ip=default::[not_specified] | -seu_protect=default::none | -sfcu=default::[not_specified] | -shreg_min_size=default::3
-top=design_1_wrapper | -verilog_define=default::[not_specified]
usage
elapsed=00:01:08s | hls_ip=0 | memory_gain=411.559MB | memory_peak=799.148MB