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-- IP VLNV: xilinx.com:module_ref:ov7670_axi_stream_capture:1.0
-- IP Revision: 1

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;

ENTITY design_1_ov7670_axi_stream_capture_0_0 IS
  PORT (
    pclk : IN STD_LOGIC;
    vsync : IN STD_LOGIC;
    href : IN STD_LOGIC;
    d : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
    m_axis_tvalid : OUT STD_LOGIC;
    m_axis_tready : IN STD_LOGIC;
    m_axis_tlast : OUT STD_LOGIC;
    m_axis_tdata : OUT STD_LOGIC_VECTOR(23 DOWNTO 0);
    m_axis_tuser : OUT STD_LOGIC;
    aclk : OUT STD_LOGIC
  );
END design_1_ov7670_axi_stream_capture_0_0;

ARCHITECTURE design_1_ov7670_axi_stream_capture_0_0_arch OF design_1_ov7670_axi_stream_capture_0_0 IS
  ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
  ATTRIBUTE DowngradeIPIdentifiedWarnings OF design_1_ov7670_axi_stream_capture_0_0_arch: ARCHITECTURE IS "yes";
  COMPONENT ov7670_axi_stream_capture IS
    PORT (
      pclk : IN STD_LOGIC;
      vsync : IN STD_LOGIC;
      href : IN STD_LOGIC;
      d : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
      m_axis_tvalid : OUT STD_LOGIC;
      m_axis_tready : IN STD_LOGIC;
      m_axis_tlast : OUT STD_LOGIC;
      m_axis_tdata : OUT STD_LOGIC_VECTOR(23 DOWNTO 0);
      m_axis_tuser : OUT STD_LOGIC;
      aclk : OUT STD_LOGIC
    );
  END COMPONENT ov7670_axi_stream_capture;
  ATTRIBUTE X_INTERFACE_INFO : STRING;
  ATTRIBUTE X_INTERFACE_INFO OF m_axis_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 m_axis TVALID";
  ATTRIBUTE X_INTERFACE_INFO OF m_axis_tready: SIGNAL IS "xilinx.com:interface:axis:1.0 m_axis TREADY";
  ATTRIBUTE X_INTERFACE_INFO OF m_axis_tlast: SIGNAL IS "xilinx.com:interface:axis:1.0 m_axis TLAST";
  ATTRIBUTE X_INTERFACE_INFO OF m_axis_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 m_axis TDATA";
  ATTRIBUTE X_INTERFACE_INFO OF m_axis_tuser: SIGNAL IS "xilinx.com:interface:axis:1.0 m_axis TUSER";
  ATTRIBUTE X_INTERFACE_INFO OF aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 aclk CLK";
BEGIN
  U0 : ov7670_axi_stream_capture
    PORT MAP (
      pclk => pclk,
      vsync => vsync,
      href => href,
      d => d,
      m_axis_tvalid => m_axis_tvalid,
      m_axis_tready => m_axis_tready,
      m_axis_tlast => m_axis_tlast,
      m_axis_tdata => m_axis_tdata,
      m_axis_tuser => m_axis_tuser,
      aclk => aclk
    );
END design_1_ov7670_axi_stream_capture_0_0_arch;
