Device Usage Page (usage_statistics_webtalk.html)

This HTML page displays the device usage statistics that will be sent to Xilinx.
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software_version_and_target_device
betaFALSE build_version1577090
date_generatedThu Dec 15 04:24:20 2016 os_platformWIN64
product_versionVivado v2016.2 (64-bit) project_id822f60a474e84399af9d98d71a5b3819
project_iteration2 random_ide44c9a77-c5ef-48dc-9c92-e859e58b8b2d
registration_ide44c9a77-c5ef-48dc-9c92-e859e58b8b2d route_designTRUE
target_devicexc7a35t target_familyartix7
target_packagecpg236 target_speed-1
tool_flowVivado

user_environment
cpu_nameIntel(R) Core(TM) i7-6700K CPU @ 4.00GHz cpu_speed4008 MHz
os_nameMicrosoft Windows 8 or later , 64-bit os_releasemajor release (build 9200)
system_ram17.000 GB total_processors1

vivado_usage
other_data
guimode=5
project_data
constraintsetcount=1 core_container=false currentimplrun=impl_1 currentsynthesisrun=synth_1
default_library=xil_defaultlib designmode=RTL export_simulation_activehdl=0 export_simulation_ies=0
export_simulation_modelsim=0 export_simulation_questa=0 export_simulation_riviera=0 export_simulation_vcs=0
export_simulation_xsim=0 implstrategy=Vivado Implementation Defaults launch_simulation_activehdl=0 launch_simulation_ies=0
launch_simulation_modelsim=0 launch_simulation_questa=0 launch_simulation_riviera=0 launch_simulation_vcs=0
launch_simulation_xsim=0 simulator_language=Mixed srcsetcount=11 synthesisstrategy=Vivado Synthesis Defaults
target_language=VHDL target_simulator=XSim totalimplruns=1 totalsynthesisruns=1

unisim_transformation
post_unisim_transformation
bufg=1 carry4=32 fdce=8 fdpe=8
fdre=164 gnd=9 ibuf=10 ldce=16
lut1=11 lut2=32 lut3=16 lut4=29
lut5=23 lut6=84 muxf7=1 obuf=13
vcc=9
pre_unisim_transformation
bufg=1 carry4=32 fdce=8 fdpe=8
fdre=164 gnd=9 ibuf=10 ldce=16
lut1=11 lut2=32 lut3=16 lut4=29
lut5=23 lut6=84 muxf7=1 obuf=13
vcc=9

report_drc
command_line_options
-append=default::[not_specified] -checks=default::[not_specified] -fail_on=default::[not_specified] -force=default::[not_specified]
-format=default::[not_specified] -messages=default::[not_specified] -name=default::[not_specified] -return_string=default::[not_specified]
-ruledecks=default::[not_specified]
results
cfgbvs-1=1

report_utilization
clocking
bufgctrl_available=32 bufgctrl_fixed=0 bufgctrl_used=1 bufgctrl_util_percentage=3.13
bufhce_available=72 bufhce_fixed=0 bufhce_used=0 bufhce_util_percentage=0.00
bufio_available=20 bufio_fixed=0 bufio_used=0 bufio_util_percentage=0.00
bufmrce_available=10 bufmrce_fixed=0 bufmrce_used=0 bufmrce_util_percentage=0.00
bufr_available=20 bufr_fixed=0 bufr_used=0 bufr_util_percentage=0.00
mmcme2_adv_available=5 mmcme2_adv_fixed=0 mmcme2_adv_used=0 mmcme2_adv_util_percentage=0.00
plle2_adv_available=5 plle2_adv_fixed=0 plle2_adv_used=0 plle2_adv_util_percentage=0.00
dsp
dsps_available=90 dsps_fixed=0 dsps_used=0 dsps_util_percentage=0.00
io_standard
blvds_25=0 diff_hstl_i=0 diff_hstl_i_18=0 diff_hstl_ii=0
diff_hstl_ii_18=0 diff_hsul_12=0 diff_mobile_ddr=0 diff_sstl135=0
diff_sstl135_r=0 diff_sstl15=0 diff_sstl15_r=0 diff_sstl18_i=0
diff_sstl18_ii=0 hstl_i=0 hstl_i_18=0 hstl_ii=0
hstl_ii_18=0 hsul_12=0 lvcmos12=0 lvcmos15=0
lvcmos18=1 lvcmos25=0 lvcmos33=1 lvds_25=0
lvttl=0 mini_lvds_25=0 mobile_ddr=0 pci33_3=0
ppds_25=0 rsds_25=0 sstl135=0 sstl135_r=0
sstl15=0 sstl15_r=0 sstl18_i=0 sstl18_ii=0
tmds_33=0
memory
block_ram_tile_available=50 block_ram_tile_fixed=0 block_ram_tile_used=0 block_ram_tile_util_percentage=0.00
ramb18_available=100 ramb18_fixed=0 ramb18_used=0 ramb18_util_percentage=0.00
ramb36_fifo_available=50 ramb36_fifo_fixed=0 ramb36_fifo_used=0 ramb36_fifo_util_percentage=0.00
primitives
bufg_functional_category=Clock bufg_used=1 carry4_functional_category=CarryLogic carry4_used=32
fdce_functional_category=Flop & Latch fdce_used=8 fdpe_functional_category=Flop & Latch fdpe_used=8
fdre_functional_category=Flop & Latch fdre_used=164 ibuf_functional_category=IO ibuf_used=10
ldce_functional_category=Flop & Latch ldce_used=16 lut1_functional_category=LUT lut1_used=11
lut2_functional_category=LUT lut2_used=32 lut3_functional_category=LUT lut3_used=16
lut4_functional_category=LUT lut4_used=29 lut5_functional_category=LUT lut5_used=23
lut6_functional_category=LUT lut6_used=84 muxf7_functional_category=MuxFx muxf7_used=1
obuf_functional_category=IO obuf_used=13
slice_logic
f7_muxes_available=16300 f7_muxes_fixed=0 f7_muxes_used=1 f7_muxes_util_percentage=<0.01
f8_muxes_available=8150 f8_muxes_fixed=0 f8_muxes_used=0 f8_muxes_util_percentage=0.00
lut_as_logic_available=20800 lut_as_logic_fixed=0 lut_as_logic_used=174 lut_as_logic_util_percentage=0.84
lut_as_memory_available=9600 lut_as_memory_fixed=0 lut_as_memory_used=0 lut_as_memory_util_percentage=0.00
register_as_flip_flop_available=41600 register_as_flip_flop_fixed=0 register_as_flip_flop_used=180 register_as_flip_flop_util_percentage=0.43
register_as_latch_available=41600 register_as_latch_fixed=0 register_as_latch_used=16 register_as_latch_util_percentage=0.04
slice_luts_available=20800 slice_luts_fixed=0 slice_luts_used=174 slice_luts_util_percentage=0.84
slice_registers_available=41600 slice_registers_fixed=0 slice_registers_used=196 slice_registers_util_percentage=0.47
fully_used_lut_ff_pairs_fixed=0.47 fully_used_lut_ff_pairs_used=4 lut_as_distributed_ram_fixed=0 lut_as_distributed_ram_used=0
lut_as_logic_available=20800 lut_as_logic_fixed=0 lut_as_logic_used=174 lut_as_logic_util_percentage=0.84
lut_as_memory_available=9600 lut_as_memory_fixed=0 lut_as_memory_used=0 lut_as_memory_util_percentage=0.00
lut_as_shift_register_fixed=0 lut_as_shift_register_used=0 lut_ff_pairs_with_one_unused_flip_flop_fixed=0 lut_ff_pairs_with_one_unused_flip_flop_used=45
lut_ff_pairs_with_one_unused_lut_fixed=45 lut_ff_pairs_with_one_unused_lut_used=40 lut_flip_flop_pairs_available=20800 lut_flip_flop_pairs_fixed=0
lut_flip_flop_pairs_used=49 lut_flip_flop_pairs_util_percentage=0.24 slice_available=8150 slice_fixed=0
slice_used=99 slice_util_percentage=1.21 slicel_fixed=0 slicel_used=70
slicem_fixed=0 slicem_used=29 unique_control_sets_used=32 using_o5_and_o6_fixed=32
using_o5_and_o6_used=21 using_o5_output_only_fixed=21 using_o5_output_only_used=0 using_o6_output_only_fixed=0
using_o6_output_only_used=153
specific_feature
bscane2_available=4 bscane2_fixed=0 bscane2_used=0 bscane2_util_percentage=0.00
capturee2_available=1 capturee2_fixed=0 capturee2_used=0 capturee2_util_percentage=0.00
dna_port_available=1 dna_port_fixed=0 dna_port_used=0 dna_port_util_percentage=0.00
efuse_usr_available=1 efuse_usr_fixed=0 efuse_usr_used=0 efuse_usr_util_percentage=0.00
frame_ecce2_available=1 frame_ecce2_fixed=0 frame_ecce2_used=0 frame_ecce2_util_percentage=0.00
icape2_available=2 icape2_fixed=0 icape2_used=0 icape2_util_percentage=0.00
pcie_2_1_available=1 pcie_2_1_fixed=0 pcie_2_1_used=0 pcie_2_1_util_percentage=0.00
startupe2_available=1 startupe2_fixed=0 startupe2_used=0 startupe2_util_percentage=0.00
xadc_available=1 xadc_fixed=0 xadc_used=0 xadc_util_percentage=0.00

router
usage
actual_expansions=221376 bogomips=0 bram18=0 bram36=0
bufg=0 bufr=0 congestion_level=0 ctrls=32
dsp=0 effort=2 estimated_expansions=236844 ff=196
global_clocks=1 high_fanout_nets=0 iob=23 lut=191
movable_instances=466 nets=595 pins=2679 pll=0
router_runtime=71.061000 router_timing_driven=1 threads=2 timing_constraints_exist=1

synthesis
command_line_options
-assert=default::[not_specified] -bufg=default::12 -cascade_dsp=default::auto -constrset=default::[not_specified]
-control_set_opt_threshold=default::auto -directive=default::default -fanout_limit=default::10000 -flatten_hierarchy=default::rebuilt
-fsm_extraction=default::auto -gated_clock_conversion=default::off -generic=default::[not_specified] -include_dirs=default::[not_specified]
-keep_equivalent_registers=default::[not_specified] -max_bram=default::-1 -max_bram_cascade_height=default::-1 -max_dsp=default::-1
-max_uram=default::-1 -max_uram_cascade_height=default::-1 -mode=default::default -name=default::[not_specified]
-no_lc=default::[not_specified] -no_srlextract=default::[not_specified] -no_timing_driven=default::[not_specified] -part=xc7a35tcpg236-1
-resource_sharing=default::auto -retiming=default::[not_specified] -rtl=default::[not_specified] -rtl_skip_constraints=default::[not_specified]
-rtl_skip_ip=default::[not_specified] -seu_protect=default::none -shreg_min_size=default::3 -top=MainModule
-verilog_define=default::[not_specified]
usage
elapsed=00:01:35s hls_ip=0 memory_gain=405.418MB memory_peak=611.813MB