VHDL Light Source Detection: Component VGA & Time Generator

NOTE: This page is one part of a larger build. Please ensure you start HERE, so you understand where the following fits in within the larger project.

VGA and Time Generator are parts of the Basys 3 that can be used to display what camera is seeing and give timing for the components in the board respectively.

VGA is an analog computer display standard marketed first by IBM in 1987. Video Graphics Array (VGA) is commonly named with video adapters, VGA itself is often used to refer to a screen resolution of 640×480. Today's VGA cards already use the Graphic Accelerator chipset, which is a chipset today that has incorporated three-dimensional acceleration capabilities (3D) integrated into its chipset. VGA serves to translate / convert digital signals from a computer into a graphical display on the monitor screen.

VGA Controller

The VGA controller provides timing signals to control the layer through the VGA port. The VGA controller internally tightens signal timings based on pixel frequency. The VGA Controller also controls the flow of video data through the VGA port. Pixel frequency clock can be derived from the system clock on your board; either using MMCM/PLL or by generating a strobe or a clock enable from the system clock using counters.

The VGA Component has ports the following list:

• Clk (clock)
• Rst (reset)
• VGA_Red
• VGA_Green
• VGA_Blue
• H_sync
• V_sync

Clock port is used for the timing the VGA, reset port is used for resetting the code from the start, the ports VGA_Red/Green/Blue are for the colors, although we will use monochrome colors (all three colors are used) since we use the Y signal from YCbCr.

H_sync (horizontal synchronization) is first adopted for CRTs screens back in the day to shoot the electrons from left to right of the screen, while V_sync (vertical synchronization) is used for shooting the electrons to the screen from upper part of the screen to the bottom per 1 frame.

There's also Href, also known as Horizonal Reference, it's activated when clocking out active image

data for each scan line as the reference.

Our Component also uses Camera Control's ports such as, pclk to receive 25 MHz timing which is crucial for VGA, Vsync, Href, and Pixelout for receiving pixel to be displayed on the VGA.

This project is focused on displaying the white color to monitor and assigning YCbCr to the VGA

Now we move on to the steps of how to make the codes

For this project, the application needed is vivado, mainly for the VGA code that can be implemented to the Basys 3 board. We used vivado 2015.4. Newer version of vivado can also be used on this project. Which can be found on this link: https://www.xilinx.com/support/download.htm

This project’s code is a combination between 2 sources mashed into a single code. Sources can be found on the references. Pretty neat.

Now we dive into the coding part, the settings can be found on the picture below

For the rest of the setups, just click “next” till find the “default part”, here...the board that we used is mainly for the Basys 3 board, here we pick Artix 7.

For the final touch, press next and the finish button will appear, press it till vivado loads the workspace.

Here are the ports that is used in this project as mentioned before:

• Clk (clock)
• Rst (reset)
• VGA_Red
• VGA_Green
• VGA_Blue
• H_sync
• V_sync

Reminder that the clock is used for the timings, reset is used for resetting the code till started again, red/green/blue are for the colors (though it’s used for white color). H_sync (horizontal synchronization) is for shooting the CRT (cathode ray tube) from left to right of the screen, while V_sync (vertical synchronization) is used for shooting the CRT per 1 frame (up to bottom).

As you can see in the coding above, there is an “std_logic” and “std_logic_vector”. Std_logic is a logic wire, it can do such things for example (or gate, and gate, xor gate, etc). Meanwhile, the std_logic_vector, is used mainly for the std_logic that has bits on it, like you can see on the RGB, these codes running on 4 bits, hence we use 3 downto 0, which means that the most significant bit to the least significant bit.

Here, architecture is used to making the foundation of the codes, such as the starting command list.

From the picture number 2, we can see the details regarding VGA frame:

Here, the resolution that we used is 640x480. H_sync is shooting the CRT from the left side to the right side, it goes low if the CRT goes back to its original position. In H_sync, there are moments when it goes high and low, this is called porches. Basically the front end of the H_sync is called front porch and the backend is called back porch. The middle part of the H_sync is when the H_sync displays the RGB or image. The gray part of the H_sync is called blanking, so when the h_pos (position of H counter) reaches the gray part, it goes low till h_pos enters the front porch, it goes high again. The gap between front and back porch is called sync pulse.

For the size of porches can be see in the picture number 3

Hence the code above follows this configuration, so that both v_sync and h_sync the active area will display the 640x480 resolution. For who’s wanted to displaying higher resolution than 640x480, the tables can be found on this link: http://web.mit.edu/6.111/www/s2004/NEWKIT/vga.shtml

Now we move on to the timing, also known as Counter, it controls the h_sync and v_sync goes high or low. It’s based on the porch table on step 5 (3rd picture). Codes can be seen here:

As you can see, there is a code called “process”, which means that we make commands to some ports. Here we use clk as the processed port. Below that, there’s an “event”. Event is used for making some changes on the code, here...event makes a condition that if the clock goes high or you can say this as “rising edge”.

Then we make statements that the h_pos count will be added by 1 until it reaches 799, if it reaches 799, then the h_pos will go back to 1. Same goes to v_pos, added by 1 till it reaches 520 and goes back to 1 again.

On to the next statements, now is about the active zone of h_sync and v_sync. If the h_pos reaches 16 till 112 (16 front porch + 96 sync pulse), it goes low, if the h_pos is outside of the zone from 16 to 112, h_sync goes high. Same thing for v_pos, it counts till v_pos reaches from 8 to 11, if v_pos is outside 8 to 11, v_sync goes high.

Now we move on to Video_on, here the ports that we called for the command are clk, rst, h_pos, and v_pos.

Here, Video_on used to display the image result when it turned on. The ports that are called on this process are: clk, rst, h_pos, and v_pos.

If the reset is active, then everything will be low or turned off. If it isn’t, then the clock starts. When the h_pos and v_pos are at horizontal display (639) and vertical display (479) respectively, the video will be turned on. If it’s outside of the active display area, the Video_on will be low.

This is the final part of making the command for the codes, here...draw is used to assign red, green, and blue to the display when it is turned on.

When reset is high...red, green, and blue are low. If reset goes low, clock goes high and the video_on will also be high, here we can see if red, green, and blue are on the display area (h_pos is between 1 to 639, v_pos is between 1 to 479) will going high or “1111”. If not, it goes low or can be said “0000”. Then there’s blanking, which is used to empty the RGB or make them go low when h_pos reaches from 1 to 160 and v_pos reaches from 1 to 40.

To see the workings of Counter, Video_On, and Draw or RGB, we will explain it in a Block Diagram to simplify the explanation here.

There you have it for the codings, next we move on to the simulation phase.

First thing first, we are going to make the test bench to make the simulation of the entity. On the test bench, here will be an additional code called “component” For the simulation, we use signal. It used to call other component’s ports.

Here we’re calling the previous ports that was used on the implementation code. After finishing calling the used ports, next we do the simulation itself, DUT stands for Design Under Test, used to mapping the called port for the simulation. Here we focus to see clk, rst, rgb, h_sync, and v_sync on the simulation. Next we make the clock for the test, for starting the simulator, we wait for 20 milliseconds due to the 25 MHz pixel clock. If it is done, run the simulation, choose “run behavioral simulation” Wait for Vivado to load the simulation Here we can see the simulation results, we do it in 1ms. H_sync is the most active part here, due to shooting the CRT from left side to the right side, V_sync here is only active for 1 frame and does not change frame due to showing only color white. Red, green, and blue here represented by an “f” which means it’s on, by combining both red, green, and blue, we have white color. Here we can see the blanking part of the RGB, it goes high till reaching almost the end part on H_sync. And goes up a few seconds later after H_sync goes high again

Constraints are a crucial part of the FPGA project to connect the ports from the .vhd files to the physical pins, buttons, switches, 7-segment digital number, and so on.

Here are the required Constraints in Basys3_Master.xdc file for the VGA.

Change and match the names after the get_ports part in the .xdc constraints file with the port names in .vhd VGA file. For example

#set_property PACKAGE_PIN G19 [get_ports {vgaRed[0]}]
To
#set_property IOSTANDARD LVCMOS33 [get_ports VGA_Red[0]]

Basys 3 Board has an internal clock in which its purpose is to make timing of the components and synchronize each other components that require it.

Clock Signal

Clock signal as a particular type of signal that oscillates between a high and a low state. It decides the digital circuit to follow in time to coordinate its sequence of actions and synchronize a circuit's operation for timing purposes. Clock Signal is calculated in hertz. Clock Divider Divides the input clock frequency and produces output clock. Example output clocks are 50MHz, 25 MHz, 62.5 KHz, etc.

Pixel Clock

The pixel clock (pclk or dot clock) is the speed at which the pixels are transmitted such that a full frame of pixels fits within one refresh cycle. For example, a VGA's dot clock set to 25MHz (corresponding to 25 million pixels per second) is just enough to display a resolution of 640x480 at 60Hz (note the active display is only a part of the frame). Most higher resolution video can therefore use a wide range of dot clocks, well above 25Hz, with the current range allowing enough bandwidth to easily exceed 1600x1200 at a 100 Hz.

Here's the code for the finished component: VGA_sync.vhd

Adrian N. Wibowo, Alfredo Fandy, Farrell Rabbani, Samuel

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