The Optimum Implementation of Improved Successive Cancellation Polar Decoder on FPGA Platform

We planed to do our polar encoders and decoders by using FPGA digital devices programmed in VHDL programing languages. For this, first of all, before building the hardware, polar encoders and repeated repairs code decoders are simulated in MATLAB. After that, hardware will be built in FPGA environment. Results achieved both from simulation and hardware will be compared. To run the algorithm faster in FPGA environment, we propose to decode many bites at the same time. The speed gain will be in clock time. The proposed model and classic decoder models will be tested on both double delete channels and AWGN channels.

https://youtu.be/9KE1WmID-2U

Encoding and decoding

In the above lines, we have mentioned how to calculate the producer matrix of polar code and how to perform the encoding operation using this matrix. The mentioned processes initially will be done in the MATLAB environment. The resulting producer matrix will be used for polar coding in the FPGA environment.

Several algorithms have been proposed in the scientific world for the decoding of polar codes. The two most basic of these algorithms are successive cancellation decoding and list decoding. This expression had been computed in a recursive manner in [1]. The detailed information about the successive cancellation decoding algorithm can be found in [1]. The successive cancellation decoding is a complex algorithm.