SR Latch Tutorial - Simple Step-by-Step Explainer

Ever wonder how digital circuits “remember” things? No, not like a Raspberry Pi running Linux. I mean way down at the bare-metal logic gate level. That’s where latches come in.

Today, we’re diving into the SR Latch (Set-Reset Latch) and its slightly fancier cousins: the Gated SR Latch and the Clocked SR Latch. Don’t worry, you won’t need a PhD to get it. If you’ve played around with logic gates before, you’re already halfway there.

All you need is the Proteus Design Suite (or any digital logic simulator like Logisim, Multisim, or Digital Works).

Think of the SR Latch as the sticky note of digital logic. You tell it something once, and it hangs onto that info until you tell it otherwise.

1. S (Set) = “Write a 1.”
2. R (Reset) = “Write a 0.”
3. Q = The note it’s holding.

The beauty is that once you set or reset it, the output sticks. Even if you stop giving it input, it remembers. That’s why it’s the smallest, simplest form of memory in digital electronics.

SR latches can be built from NOR gates or NAND gates. The only difference? NAND ones use “active low” inputs, so the signals look inverted compared to the NOR version.

Quick note before we go further: Add a clock pulse to a latch, and suddenly it becomes a flip-flop. Same family, slightly different behavior. Engineers argue about terminology, but just remember: flip-flops are the clocked cousins of latches.

Alright, here’s the simple logic rundown. (Imagine you’re flipping a light switch with weird rules.)

1. S = 0, R = 0 → Nothing changes. The latch holds its last state.
2. S = 0, R = 1 → Reset mode. Output becomes 0.
3. S = 1, R = 0 → Set mode. Output becomes 1.
4. S = 1, R = 1 → Whoops. Invalid state. Both outputs fight each other, and chaos ensues. Engineers pretend this state doesn’t exist.

When you simulate this in Proteus (or any digital simulator), you can actually watch the outputs flip around depending on the S and R values. It’s oddly satisfying.

Hobbyist tip: If you want to try this on real hardware, grab a 7400-series NAND IC (like a 7400 quad NAND gate). Wire two of them up as cross-coupled feedback loops, and you’ve got yourself your first physical latch.

The basic latch is always listening, which is fine… until it isn’t. Sometimes you want it to pay attention only when you say so. Enter the Enable pin.

This version is called the Gated SR Latch.

1. When Enable = HIGH, it behaves like a normal SR Latch.
2. When Enable = LOW, it ignores you and just holds the last output.

Think of it like talking to a kid with headphones on. If Enable isn’t active, they don’t hear your Set/Reset commands.

The last variation we’ll look at is the Clocked SR Latch, which most people also just call an SR Flip-Flop.

Instead of an Enable pin, you’ve now got a Clock input. This makes the latch edge-triggered, meaning it only updates when the clock signal ticks (rising or falling edge, depending on design).

Why does this matter? Because in sequential logic, timing is everything. You don’t want memory changing randomly; you want it synchronized with the system clock.

Here’s how it behaves on a clock edge:

1. S = R = 0 → No change.
2. S = 1, R = 0 → Set Q = 1.
3. S = 0, R = 1 → Reset Q = 0.
4. S = 1, R = 1 → Same invalid nonsense as before. Don’t go there.

Hobbyist tip: This is where things start looking like real-world computer memory. Practically every flip-flop you’ll meet has a clock input, because without it, CPUs would be total chaos.

And there you have it: the SR Latch family tree.

1. Basic SR Latch = the sticky note.
2. Gated SR Latch = sticky note with a lock on it.
3. Clocked SR Latch (Flip-Flop) = sticky note that only updates on the beat of a drum.

Play with them in simulation, then try wiring one up with a 7400 NAND chip. Once you get the hang of SR, moving on to D, JK, or T latches is a natural next step.

If you’re serious about digital electronics, these little circuits are unavoidable. Luckily, they’re simple and kind of fun once you see them in action.

This Instructable was prepared with info adapted from this SR latch tutorial.