Phase LockLoop CD4046 1Mhz PLL (help Needed)

I am hopping to get some advice on is this is correct as I have never made a componet from skratch before!

I am trying to create a CD4046 Phase-Locked Loop (PLL) as it is essential in this circuit for phase detection and synchronization between the reference and received signals. It takes an input from the Teensy-generated reference signal (Pin 14 - SIGNALIN) and compares it with the received signal (Pin 3 - COMPARATORIN), output from the AD8260. The VCO output (Pin 4 - VCOOUT) tracks the input phase, generating a frequency-locked output. The phase difference is provided as an analog control voltage (Pin 2 - PHASECOMPOUT), filtered and digitized by the AD7357 ADC. The CD4046 operates at 3.3V or 5V, with external R1 and C1 setting its frequency range.

Key points

CD4046 PLL into Phase detector comparator sensor project with the Teensy 4.1, AD8260-EVALZ, and EVAL-AD7357EDZ, the design needs to focus on:

1. Handling the signal characteristics from the Teensy (likely a digital PWM or signal generated in your DSP pipeline).
2. Interfacing with the analog components, ensuring proper impedance matching and signal integrity.
3. Optimizing for high-frequency signals and phase-sensitive detection since the system involves precision measurements.

Adjusted Circuit Design Components

1. Signal from the Teensy to CD4046

1. The Teensy will generate a signal to feed into the Phase Comparator of the CD4046.
2. If the signal is PWM or digital, a low-pass filter (RC or active) may be required to clean the input signal to avoid unwanted harmonics.
3. If already a clean sinusoidal or periodic signal, you can directly connect the output to the Phase Comparator Input (pin 3).

2. Voltage-Controlled Oscillator (VCO) Configuration

1. Set the VCO frequency range to match the system's operational frequency band:
2. R1 and C1 determine the VCO's frequency range:
3. R1=10 kΩ
4. Fine-tune R1 and C1 based on the expected frequency from your sensor system.

3. Phase Comparator

1. Select Phase Comparator I (pin 4) or Phase Comparator II (pin 5) based on your application:
2. Phase Comparator I: Produces a digital output (good for simple systems).
3. Phase Comparator II: Produces an analog error signal (preferred for precise phase adjustments).
4. The signal from the Teensy connects to the input of the comparator.

4. Low-Pass Filter for the Loop Filter

1. Design a loop filter to smooth the phase comparator's output:
2. Basic RC filter with:
3. R2=100 kΩR2
4. C2=1 μFC2
5. Time constant: τ=R2⋅C2
6. Adjust τ for your desired lock-in speed versus stability trade-off.
7. For noise-sensitive systems, add a second stage of filtering (C3).

5. AD8260-EVALZ and EVAL-AD7357EDZ Integration

1. AD8260-EVALZ (Analog Signal Conditioning):
2. Use the AD8260 to amplify and condition the output signal from the PLL's phase comparator or VCO.
3. Set the gain and filtering stages for impedance matching between the PLL and ADC.
4. Example: Add a low-pass filter to limit high-frequency noise before feeding into the ADC.
5. EVAL-AD7357EDZ (ADC Module):
6. Connect the conditioned PLL output to the ADC input.
7. Ensure the ADC sampling rate matches the PLL's signal frequency.

6. Teensy 4.1 as the Control Unit

1. Generate the reference signal to the CD4046.
2. Read the digitized signal from the AD7357 via SPI.
3. Implement DSP algorithms on the Teensy to adjust the PLL parameters dynamically if needed (feedback loop).

Key Considerations

1. Signal Integrity:
2. Use shielded cables and proper grounding to avoid noise.
3. Add decoupling capacitors near the power supply pins of all ICs.
4. Impedance Matching:
5. Ensure proper impedance matching at all interfaces to prevent signal reflections or losses.
6. Frequency Range:
7. Verify that the frequencies from your sensor setup fall within the CD4046 VCO's operating range.
8. Dynamic Adjustments:
9. Program the Teensy to adjust the PLL loop filter parameters or VCO settings for dynamic conditions, if needed.