One Transistor Full Adder

INTRO:

Classically a full adder is created with the use of 2 XOR gates, 2 AND gates and an OR gate. Each gate already consists of a fair few transistors, especially the XOR gates, and thus the total number of transistors per classical full adder can reach 18. Some designers over the net have proposed full adder circuits with transistor number as low as 12 and 8. However, in this Instructable I present you the fully functional ONE TRANSISTOR full adder, consisting of only 1 transistor (any beta), 2 diodes and 5 resistors: 8 components.

Now you may think how is this possible? Well the answer is simple, the circuit is an analog approach whose outputs are compatible with digital inputs of a typical logic IC. Given it's extreme low number of components the full adder circuit has a number of disadvantages and some pretty cool advantages I won't hesitate to list right of the bat.

CONS:

1) The sources feeding into the circuit inputs (A,B, and Carry-in) must have a relatively low impedance.

2) The outputs of a circuit (Sum, Carry-out) are high impedance outputs, and must not be loaded (meaning this circuit will not drive a LED for you, outputs can only be read by other high input impedance logic gates, comparators, voltmeter, etc.).

3) The speed of the circuit has a maximum speed of 1MHz (theoretically limited only by capacitance within the circuit).

4) High and Low logic levels on the outputs have a narrow tolerance.

PROS:

1) Very component efficient. Just 8 components.

2) Can VERY easily be converted into a decent one bit ALU capable of ADDing, ANDing, XORing and ORing bits together without any additional components. With typical logic IC's such functionality would be rather complicated to achieve, this circuit however offers a very easy solution.

HOW IT SHOULD BE USED:

So in other words, this circuit is ideal with inputs coming from a source such as a logic gate and outputs feeding into an input of a another logic gate. The result is a high economy, well implemented, full adder logic block.

----->LOGIC GATE-----> ONE TRANSISTOR CIRCUIT ------> LOGIC GATE---->

Of course you can't cascade this full adder by simply connecting both such circuits together, the impedance matching won't allow it. However you can do so by separating outputs and inputs with a HIGH impedance to LOW impedance device such as a simple logic gate.

FULL ADDERS OUTPUT---------------------------> LOGIC GATE (Buffer) ---------------------------->ANOTHER FULL ADDERS INPUT

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NEXT STEP: HOW IT WORKS.

Components used:

10k resistor (x3)

68k resistor (x1)

100k resistor (x1)

Silicon diode (Vd=0.7v @ 10mA) (x1)

Green LED (Vd=1.8v @ 10mA) (x1)

PNP Transistor (Any beta) (x1)

How it works:

Before getting into how this circuit functions we must first understand what are the typical digital HIGH-LOW input tolerances for logic families such as TTL. More specifically I will be looking at 74HC series IC input tolerances.

Typically you'd never have to think further than 5V is HIGH and 0V is LOW, however today it would be nice to know where the boundary between HIGH and LOW for an input actually is.

When we take a look at a datasheet for a specific logic chip we can find that typical guaranteed safe LOW level lie between 0V and 0.8V, and typical guaranteed safe HIGH level lie between 3.2V and 5V. So what is in between? High output "turbulence" and random oscillations? In reality (for many 74HC TTL chips at least) what datasheets state are simply SAFE logic levels, and the actualy border between HIGH is LOW is very narrow, only about 0.1V about 2.2V

Just above 2.2V is HIGH, just bellow 2.2V is LOW. You can test this by applying a variable voltage source into a gate input and then monitoring when HIGH or LOW transition on the output occurs.

As you might have guessed our circuit will be taking advantage of this, and of course playing outside the safe zone of the manufacturer. I have built a homemade TTL computer using this circuit as an ALU which calculated 16000 bits per second, and I assure you that this "outside the safe zone" approach is VERY reliable even at high frequencies.

Now finally to the functionality of the circuit.

This circuit begins with Carry out. Lets recall the functionality of a Carry out.

There are 3 inputs: A,B and Carry in. The Carry out is HIGH when at least two of the three inputs are HIGH.

OK, now consider a circuit below: (all resistors are the same and "+" are all connected)

A---------/\/\/\/\----------+

B---------/\/\/\/\----------+---------- Co

Ci--------/\/\/\/\----------+

Now lets analyse this circuit, when all inputs are LOW the Co is 0V

When only one input is HIGH the Co is 1.66V

When only two inputs are HIGH the Co is 3.33V

When all inputs are HIGH the Co is 5V

0V and 1.66V are bellow 2.2V barier and thus are considered LOW. 3.33V and 5V are above 2.2V barier and thus are considered HIGH. Note how magically this simple circuit behaves, just like a Carry out of a full adder should.

And just like that the Carry out functionality has been achieved with just 3 identical resistors. A logic gate counterpart would have taken three 2-input AND gates and a one 3-input OR gate. The payback of course are the narrower HIGH-LOW tolerances and non low impedance output.

Now all we have left is the Sum output. This one is a bit more tricky and cannot be achieved without an active components such as a transistor, logic inverter or a solid state switch. Sum output has a invert like properties which are impossible to achieve with basic components such as resistors and diodes (zero-transistor full adder is out of the question).

Now look at the circuit schematic and note that the 3 resistor Carry out circuit is fed almost directly into base of a PNP transistor that appears to be in a common base configuration. The diode that seporates the base and the Carry out is only there for shifting sum output 0.7V higher to meet 2.2V barier expectations.

The common base configuration will have minimal load (won't effect it much) on the 3 resistor Carry out circuit while being a very useful inverter. If you now select collector and emmiter resistors such that transistor saturation occurs when base voltage is LOW and active region when base voltage is HIGH the voltage on the collector will almost resemble the sum functionality we are looking for.

The "almost" resemblance I'm speaking of occurs when base voltage is highest (all 3 inputs are HIGH). The transistor is off and the collector voltage is 0V, which shouldn't happen because sum should be HIGH at that moment.

This problem can be fixed by adding a green LED (with a voltage drop of about 1.8V @ 10mA) across Carry out and emitter. This way when all 3 inputs are HIGH the LED will conduct and create 5-1.8=3.2V on the emitter, a now HIGH voltage level.

And just like that a ONE TRANSISTOR full adder is achieved. The LOW voltage levels for Sum output are [1.2V and 1.5V]. The HIGH voltage levels are [2.7V and 2.8V]. Note that all satisfy the 2.2V boundary.

This concludes this instructable, hope you had fun. And remember that you can simulate and check all this on an online circuit simulator if you don't believe me. The ALU functionality can be achieved by applying different digital voltage levels to 100k and 68k resistors. I will describe them better if anyone is interested.