Linear-Feedback Shift Register

This is revisit of a student project I mentored back in 1990-91. Surprisingly the breadboard hardware which was recently returned to me and had not been powered for 30 odd years worked perfectly when powered ON.

This project implements a pseudo-random (PN) sequence generator based on a 8-bit linear-feedback shift register (LFSR). Additional circuitry was added to convert and send the 1's and 0's output of the LFSR as ASCII serial data '30','31' Hex. This permitted acquiring and analyzing the output stream using a simple dumb terminal.

A 8-bit DIP switch permits setting up of desired feedback combinations from the eight shift register outputs. Generation of different length PN sequences including the maximally long LSFR could be demonstrated and compared with calculated results.

This is suggested as a starter project to students for implementation on FPGA kits where both the LFSR and serial-data output are implemented.

I wish to acknowledge the use of the online OMNI LFSR calculator used in verification of the hardware results. https://www.omnicalculator.com/math/linear-feedback-shift-register

The circuit is implemented using standard TTL devices a 555 timer and an ULN2003 open-collector driver.

The 555 timer sets-up the primary clock at 2400 Hz. This clock is fed to the 74LS93 4-bit binary counter. QD of the counter when inverted forms the clock to the 8-Bit shift register 74LS164.

The eight outputs of the shift-register are connected to ex-OR gates through DIP switches. Effectively the connected switches are ex-OR'ed to form the feedback input to the shift-register. The resistor network sets the Low value for unconnected er-OR gate inputs, as open TTL inputs are considered as H.

The LFSR scheme has a drawback that no sequence is generated if the seed is all zeroes. The UNL2003 along with two OR gates forms an 8-bit OR gate which ensures that a High state is input to the shift-register if all the outputs are zero.

The 74LS154 4 -16 line decoder inputs are connected to the QA-QD outputs of the 4-bit binary counter. The decoder outputs Q4-Q14 are the basic 10 counter clock periods used for the serial output generation.

With reference to the oscilloscope trace of the serial-output:

Q4-bar AND QH of the shift-register occur at the '0','1' position of the serial Hex 30,31

Q9 AND Q10 occurs a the '3' position of the serial Hex 30,31 (0000 1100, 1000 1100 serial data)

Q13 occurs as the stop bit for data in 8-N-1 serial format, 2400 baud

and Q12 along with Q13 occur as the stop bits for data in 7-N-2 serial format, 2400 baud

A diode resistor gate is used to simplify combination the outputs from the shift-register and decoder to form the final serial output.

The first two slides show raw data captured on a PC using a USB to serial converter. Data is displayed in ASCII '0101...' or alternately as Hex s '30 31 ...'

Three test cases with the corresponding DIP-switch positions are presented along with the experimental data and and predicted using the OMNI LFSR calculator. https://www.omnicalculator.com/math/linear-feedback-shift-register.

Switch 10101100  Period 6

Expected 110011

Hex

02-Apr-22 11:24:28.653 [RX] - 31 31 30 30 31 31  31 31 30 30 31 31  31 31 30 30 31 31 31 31 30 30 31 31 31 31 30 30 31 31 31 31 30 30 31 31 31 31 30 30 ........

ASCII

02-Apr-22 11:24:28.653 [RX] - 110011 110011 110011 110011 110011 110011

110011110011110011110011110011110011110011110011110011110011110011110011110011110011110011110011110011110011110011110011110011.........

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Switch 10101101  Period 35

Expected 01110111 01010011 01001001 11101000 000

02-Apr-22 11:37:38.141 [RX] - 01110111 01010011 01001001 11101000 00

00111011101010011010010011110100000001110111010100110100100111101000000011101110101001101001001111010000000111011101010011010010011110100000001110111010100110100100111101000000011101110101001101001001111010000000111011101010011010010011110100..........

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Switch 10111000  Period 255

This is a maximally long LFSR.

10111100 01101000 00001000 11100010 01011100 00001100 10010011 01110010 00001010 11011010 11001011 00001111 10110111 10101110 10001000 01101100 01111001 11001100 01011010 01000101 00101010 01110111 01100111 10111111 01001100 11010100 01100000 11101010 10111110 01010000 10011111 1110000

02-Apr-22 11:47:12.863 [RX] - 

10111100 01101000 00001000 11100010 01011100 00001100 10010011 01110010 00001010 11011010 11001011 00001111 10110111 10101110 10001000 01101100 01111001 11001100 01011010 01000101 00101010 01110111 01100111 10111111 01001100 11010100 01100000 11101010 10111110 01010000 10011111 1110000

1011110001101000000010001110001001011100000011001001001101110010000010101101101011001011000011111011011110101110100010000110110001111001110011000101101001000101001010100111011101100111101111110100110011010100011000001110101010111110010100001001111111100001011110001101000000010001110001001011100000011001001001101110010000010101101101011001011000011111..........