Division Based on Repeated Subtraction - Virtex-7 FPGA Divider Using Xilinx ISE 14.5

This Thesis was presented at the International Web Conference on “Innovative Engineering Technologies - 2020” organized by Sri Ramakrishna Institute of Technology, Coimbatore

This Research Project is about Division algorithm for unsigned numbers based on the principle of “Repeated Subtraction”. The implementation is for radix 5 i.e. 32-bit unsigned numbers.

• Software Used : Xilinx ISE 14.5 (VLSI Design Software)
• Hardware Used: Virtex-7 FPGA

A Divider circuit using Virtex-7 FPGA is implemented. From the below shown output image

1. a , b --> Inputs from user (a --> Dividend , b --> Divisor )
2. remainder --> Remainder on dividing a by b
3. quotient --> Quotient on dividing a by b
4. temp , Flag--> A Temporary variable used for finding the required results
5. bbar --> To find the 2's complement value of input b
6. WIDTH --> Maximum value of 32 bit (1111 1111 1111 1111 1111 1111 1111 1111 --> 4294967295 )

On entering values for a and b , the process of "Repeated Subtraction" starts , where the value a is repeatedly subtracted with b and simultaneously checked with the same .The maximum value of quotient is the maximum value of 32 bit (stored in WIDTH) . If divided by zero , it displays 'X' ,because division by zero is not possible.

The following cases are explained in the below steps:

1. Division by Zero ( a÷b ,where b=0 )
2. Dividing by a Greater Divisor ( a÷b , where a is less than b)
3. Dividing by a Number Equal or Less Than the Dividend ( a÷b ,where a>=b , b≠0 )

In this case , it displays 'X' as output because dividing a number with zero is undefined.

On dividing 620 by 0 , the output is as displayed above.

In this case , any number divided by a greater number , gives the quotient as zero and remainder as the number itself. Here it displays quotient as 0 and remainder same as value b.

When a=6 , b=15 ==> 6/15 , the output displays as shown above.

This is a normal case scenario .The above shown output explains.

output 1 --> a=9,b=2

output 2 --> a=620559599 , b=68951