Designing a Bootstrap Synchronous Solar Charger With Balancing

Introduction

This is a follow-up on “How to Design and Build an MPPT Solar Charge with BMS Using Arduino”.

This article is only about designing a synchronous charger.

Implementation steps might happen in my next article which will be many months from now. I just ordered the parts and the 200AHr LifePo4 batteries. That will take months to arrive.

There is no explanation for the concept of MPPT, buck, and flyback converter. For those concepts please read my previously published article on MPPT.

I had no experience in designing a switching power supply or solar system. My last design before I retired was analog circuits on a 7nm process running at GHz. All my circuits were less than 10mA. Now working on the solar charger with currents higher than 10A, that is my uncharted territory.

I acquired my solar system knowledge through reading, watching videos, and disassembling devices to figure how it works. I like to publish what I learned and explain it simply for the benefit of my reader so that my reader can replace my former design with this design for better performance.

Also through explanation, I will have better insight into how it works.

If my explanation is wrong, please don’t hesitate to point it out so that I will learn more and correct my mistakes.

My original plan was to buy an off-the-shelf 20A 40V buck converter as my solar charger.

It is inexpensive, high efficiency, and small in size. I planned to use 2 digital trim pots X9C104 to replace the analog trim pots for controlling output voltage and current. Also, add secondary windings to the toroid for battery balancing.

To be confident the modification will work, I reverse engineering on the buck converter by removing the toroid and the capacitors to trace the wiring connections.

My schematic might not be accurate, since my eyesight is not good. There will be a big chance that I would make a mistake by following the wrong traces. There are 2 devices I don’t know what they are. With my best judgment, I guess what they are such that the circuit function makes sense. They are the OPAMP and the Voltage Regulator. If anyone used the buck converter and knew what they were, please tell me.

Zoom in on the 3rd picture, you will be able to see the part labels I added.

Above is the buck converter schematic I made. Hope I got it right.
It uses LM25116 as the controller. It is a very high efficient buck controller with a bootstrap NMOS gate driver and synchronous switching.

The 5V regulator and the OPAMP were my best guesses. They had no part labels to indicate what they were. I guessed what they were to make the circuit sensible.

This type of driver has superior performance compared to my former design. I wish I knew this before.

For detailed information on LM25116 please read the datasheet published by TI.

This is what I learned from studying the LM25116 datasheet and scope probing the buck converter.

For better conversion efficiency, NMOS is used instead of PMOS as an ON/OFF switch to deliver power to the inductor.

NMOS has lower ON resistance compared with PMOS due to the electron mobility is higher than the hole.

Without the boosting voltage to drive the NMOS gate, the maximum voltage to the gate is Vin.

For current to flow through M1, the gate-source voltage has to be higher than the threshold voltage Vt. That implies the voltage drops across the drain-source Vds have to be higher than Vt.

Assume M1 carries 10A and Vds = 4V.

That means M1 will dissipate 40 Watts of power.

The temperature at M1 will be as hot as the tip of a soldering iron.

To overcome this issue, a high gate voltage is needed to drive the gate using the bootstrap circuit above.

The CLK swings between 0 to 11V

The inverter A1 also swings between 0 to 11V.

Vin=40V,

M1 Vt=4V,

Ron=40 mOhms.

Diode D1 forward voltage = 0.4V,

BJT Vbe =0.7V, beta=infinity.

When CLK=0V, the positive side of C1 will charge up by D1 to Vc1 = 40-0.4 = 39.6V.

The minus side is 0V.

Q3 is ON and the base of Q2 is grounded,

so M1 gate Vg = 0,7V. M1 is OFF.

When CLK = 11V, The voltage at the minus side of C1 lifts to 11V.

The plus side of C1 also lifts up to 11V + 39.6V = 50.6V.

Q3 is off,

Q1 base voltage lifts to 50.6V through the resistor R2.

Then Vg = 50.6 - 0.7 = 49.9V,

M1 Vgs = 49.9 - 40 = 9.9V which is much higher than Vt. M1 is fully turned ON.

With a 10A current, the power dissipation on M1 = 10*10* 40m= 4 Watts.

It is 10 times less than without the bootstrap circuit.

With this kind of bootstrap circuit, the Vgs voltage never exceeds 20V and the Vdg never exceeds 55V.

So it is safe to run the circuit up to 40V which allows installing the solar panel in series of 2.

In my previous article, I didn’t understand why Vgs had a 20V breakdown limit and the Vds had a 60V limit since drain and source were interchangeable in the microelectronic circuit. Nobody responded to my question.

Finally, I found the answer by studying the power MOS structure. Power MOS differs from microelectronic MOS. Power MOS is a vertical structure. Its drain and source are not symmetrical. Its oxide has a breakdown voltage above 20V. So there is a limit of Vgs = +/-20V.

When drain voltage is higher than the gate, The electrical field under the gate converts the silicon layer from N- to P-. That forms a reverse bias PN junction diode with a depletion region and a depletion layer capacitor Cdp. The gate oxide capacitor Cox in-series with Cdp acts as a voltage divider that reduces the voltage across the oxide, so that drain and gate can withstand much higher voltage without breaking down.

In the oxide region between gate and source, there is no depletion layer formed due to P+ and N+ are highly doped. and shorted together.

The ON resistance is the sum of drain resistance Rd, channel resistance Rch, and source resistance Rs.

Ron = Rd + Rch + Rs. Only the Rch is changed by the gate voltage.

There is no point to have gate voltage higher than 10V since Ron = Rd + Rs even with Rch=0.

By the way, the MOS body diode is not exactly a diode. It is an NPN with a base and emitter shorted together. Some people said the P and N shorted together is for preventing latch-up.

I had a different opinion. There are only 3 layers. For an SCR to exist, it needs 4 layers.

I believe a short PN junction is to improve breakdown voltage.
If you look at an NPN datasheet, Vces is always higher than Vceo.

In a normal buck converter, when M1 is off, the current I flows through D2.

Most of the energy stored by L1 will transfer to C2. A small amount of power is dissipated by D2.

The power loss = I * Vd,

To minimize this power loss, a MOS switch M2 is added.

Once M1 is off, M2 is on. M2 ON resistance is very small, so the power loss is significantly reduced.

M1 and M2 can't be on at the same time. Otherwise, a lot of currents will flow straight through both of them and blow them up.

That means the clocking to both gates needs to have a non-overlap dead time so that both of them never turn on at the same time. During this dead period, the current flows through the M2 body diode.

The plot on the right was measured at the LM25116. The blue trace was the gate of M1, and the yellow trace was the gate of M2. It had a non-crossover dead time > 100nS.

I was puzzled by the fact why the blue trace pulse width did not change much from no loading to 2A loading Also without loading, the buck converter consumed more than 1 Watt of power.

Finally, it dawns on me. M2 does not turn off when all the stored energy in L1 is transferred to C2.

All the articles I read and videos I watched, none of them mention turning off M2 when energy transfer was completed. Nor did they mention current flow is reversed.

When M1 is off, and L1 current drops to 0. One side of L1 is connected to C2, which is at a high voltage, while the other end of L1 is grounded by M2. So the current starts to flow backward.

If M2 is a Schottky diode, this won’t happen. But M2 is a switch. Nothing will stop the current flows back. So the energy from C2 charges up the L1 magnetic field.

Once M2 is off, all the stored magnetic field energy becomes current and flows through the body diode of M1 back to the input capacitors.

In other words, at no load, energy from the input transfers to the output capacitor, then reverse energy transfers from the output capacitor back to the input.

The back and forth energy transfer waste a lot of power. Most of the power loss is in the M1 body diode.

To prove my theory, I added a Schottky diode across the M1 drain and source, The power dissipation drops by 10%.

I can’t use this buck converter as battery balancing because when the current flow is reversed.

There will be a lot of current flow directly to the balancing battery due to the transformer action of L1 and L2.

Based on what I learned from studying LM25116, I designed my bootstrap and synchronous buck charger with the feature that M2 is off when the current starts to flow backward.

Design Target.

Input: 40V max.

Output 9V to 15V and 20A max.

Balancing: 3 or 4 batteries in series.

For 3s, L2 to L4 are 5.5 turns, and no L5

For 4s, L2 to L5 are 4.5 turns.

Operational Frequency: 100KHz to 200KHz

Without wasting my investment on the buck converter, I took the toroid, NMOS, and heat sinks out and used them in my prototype.

The 2 NMOS are used as M1 and M2. But I can’t find the NMOS datasheet, so I use IRFZ44N instead in my simulations.
I measured the toroid relative permeability, it is 50 which is 80 times less than my previous toroid. That implies its saturation current will be very high. Since the buck converter is rated at 20A, and I am going to use the same number of turns in the primary winding, so I did not bother to measure its saturation current.

I used AWG 18 wires to wind the inductors. It is better to use AWG 16 for 20A. But I only have AWG 18 wire. Its wiring resistance is 7m Ohm for 1 foot. Power dissipation is 20*20*0.007 = 2.8W. It is not that hot. Anyway, I plan to turn on a fan to cool the M1 and the toroid once the charge current is above 10A.

Note: All 1m Ohms resistors are not real. They are for the ease of plotting branch currents.

clk_M1 and clk_M2 are 2 non-overlap 5V clock signals to turn M1 and M2 ON or OFF.

5V is not high enough to drive M1 and M2 hard ON. So a MOS gate driver DS0026 is used to translate the 5V signals to 12V signals.

D1, Cg1, Rg1, Qg1, Qg2 form a bootstrap circuit to drive the gate of M1.

Rg1 and Qg3 form an inverter driving the base of Qg1 and Qg2.

C9 is the feedforward capacitor to speed up the inverter.

Qg1 and Qg2 are emitter followers to generate high current to drive the MOS ON and OFF fast.

M2 is the shunt switch to bypass current flows through D2 to reduce power dissipation.

D2 is to create a current path when both M1 and M2 are OFF instead of flowing through the M2 body diode.

D5 is another shunt path to bypass current flows through the M1 body diode to reduce power dissipation when the L1 current is reversed.

This circuit creates non-overlap clocking to M1 and M2. They are built with 7400 TTL logic gates. Replacing them with CMOS gate logic will be better. The reason is I have a lot of 7400 series gates and no CMOS logic gates.

OHb drives M1 gate through an inverted level translator. When OHb is low, M1 is ON. Otherwise, M1 is OFF.

OLb drives M2 gate through an inverted level translator. When OLb is low, M2 is ON. Otherwise, M2 is OFF.

X1, X2, X3, and X4 are the delay elements to generate a non-over-lap clocking between OHb and OLb.

EN is the enable signal for both OHb and OLb. If EN=0, both OHb, and OLb will be high, which switches both M1 and M2 OFF. In normal operation, EN=1.

CLR is a clear signal to reset OLb to high for turning off M2. On the waveform at 20uS, the CLR goes low and forces OLb high, which shortens the OLb pulse. CLR is a pulse generated by the comparator which is used for detecting reverse current that flows through Rs1 when M2 is ON.

I use LM339 as the comparator. But I don’t have its model, I use the LTC6702 model to replace LM339 for simulation.

When current starts flowing reversely, M2 needs to be OFF as soon as possible to limit the reverse current. LM339 propagation delay is 0.5uS with 20mV overdrive. To reduce the time to shut off M2, instead of comparing current sensing voltage at 0V, I raise it up by 20mV using R7 and R26 voltage divider.

With this setup, the peak reverse current time is less than 0.5uS and the peak reverse current is less than 1A. This energy from the reverse current will not be wasted. It just kicks back to the input with some of the energy dissipated at D5.

The positive side of the comparator input is connected to the current sensing resistor Rs1.
There are a lot of comparators on the market which have propagation delays less than 100nS with higher cost. Using those comparators will achieve shorter reverse time and better efficiency. For the same reason, my device choices are limited by what I have in hand.

Lifting the minus input up by 20mV will make the comparator pulling down early than the current reaches 0 A. That means once the + input drops to 20mV, the comparator output will pull down and shut off M2 after a delay of 500nS. That limits the reverse current. If lifting the minus side too high, it will turn M2 ON slower, and more current flows through D2 instead of M2. That is the trade-off between power dissipation between D2 or the reverse current in M2.

4 secondary windings are added to the toroid for charging up the selected battery.

The selection is controlled by turning ON Mb2, Mb3, Mb4, or Mb5,

The Db2, Db3, Db4, Db5 are for unidirectional flows of current to charge the battery. Those diodes can be replaced by MOS using synchronous switching. Since balancing only happens once a while and a bit complicated. I don’t bother to implement them.

For switching on Mb2 and Mb3, their gate voltages go up to 12V.

For switching on Mb4 and Mb5, their gate voltages go up to 24V that comes from the voltage booster.

R10, R11, R12, R13 are added to limiting the amount of balancing current sourcing out.

X1 DS0026 is a 5V to high voltage logic level translator and a MOS gate driver.

It drives C1 and C2 up and down to boost V40 and V24 up by 12V.

A1 is a D flip-flop to divide the input PWM clock by and generate a 50% duty cycle clock.

When EN_inb=0, Qi1 is off. Mi1 gate rises up to 50V and turns on Mi1.

When EN_inb=5V, Qi1 is on. Mi1 gate voltage drops to Vin - Vdi2, and Mi1 is off.

Di2 is for limiting the voltage across Vgs not to exceed specification limits of 20V.

Di1 is for the protection of the body diode of Mi1 just in case there is a large amount of surge current from INp to C1 during power-up.

When EN_outb=0, Qo2 is off, the Mo1 gate pulls up to 24V and turns Mo1 on.

Qo1 is for output short circuit protection.

If output current surge above 30A, Qo1 is on and pulls Mo1 gate down and turns off Mo1.

This is only for a short duration. The microcontroller should turn the output off if the output current exceeds 20A. In my previous version, the microcontroller checked the output current every 20mS.

The current sensing is referenced to the ground. Rs1 senses the charge current. Rs2 senses the output current.

To generate the average current output, add the RC low pass filter on the sensing voltages before feeding to the ADC.

Power in = 250.8 Watts

Power out = 229.7 Watts Efficiency = 229.7/250.8 = 91.6%

The inductor current does not drop back to zero. It is fine to run this way as long as the inductor is not saturated.

All the *.asc and *.asy are netlist, symbol, and library files for LTspice. Put all of them in your LTspice simulation directory.

I hope there is enough information in my document for those who want to replace my former design with this one.

Even though I have not built it yet. From my past chip design experience, If simulations showed it worked, the chip always worked. If it did not work as I planned, it was only that I did not simulate it right.

I like to thank both of my friends and colleagues from the bottom of my heart who threw rocks at me just like the good old days during design reviews. I received a lot of bruises on my ego but that won’t kill me, only made me stronger and my job more secure. Now, job security means nothing to me. But having those bruises brings back those fond memories.

Thanks for reading my article. I hope some of my readers will share their thoughts with me.

Have fun.

In the memory of my mother’s love.