Create a Legendary Pong Game

It all started in a printing studio with small talk and turned into an obsession. So, there I was, waiting for my documents to be printed, and the silence created a void that was longing to be filled. When I mentioned that I am a software engineer and a lecturer, the guy behind the counter told me he’s more the hardware type. Unfortunately, their TV-producing company went broke, as many Yugoslavian did at the time of the war, so he is retired from that enthusiasm and now just prints paper. It was really fun, though, and his high school thesis was creating a Pong game replica. When I asked him which microprocessor he used to program it, he just started laughing. “No son, there’s no easy way out through the software this time. It was all in hardware, mostly digital, with exception of paddles which moving took place by turning the potentiometers.” And I just died there. Just couldn’t grasp it. How!?! How can this be done!?! With chips only!?! My paper was long printed, and people in line got tired of my questions and started to complain, so I kindly apologized and stumbled out of the store. But I was mesmerized, changed. I needed to understand it, I just had to! I suddenly found myself stuck in this endless recursion of thoughts that could only be resolved by building a complete game myself. I had a real streak of luck to find Dr. Holden’s Lawn Tennis, a brilliant and detailed explanation of the Pong's inner workings, together with a complete build instruction manual. But I couldn’t grasp it without getting my hands dirty and building the Pong game from the scratch. And this is my first piece of advice – if you want to understand it, build it. During the build, I figured out that my luck hasn’t left me, because I found two more fascinating resources on building a Pong game – Mr. Boris’s Pong schematics division into sections with detailed descriptions, together with Prof. Edwards’s paper Reconstructing Pong on an FPGA. Going through each piece of detail with the highest attention, I was able to build a working version of the Pong machine and create this manual. I would like to express my deepest gratitude to Dr. Holden, Mr. Boris, and Prof. Edwards for their kindness to let me use their work as a backbone for my interpretations. I would have never built nor understood it without their work! And this is my second piece of advice – read their work and understand the Pong. Finally, I use this opportunity to express my sincere appreciation to Mr. Allan Alcorn, the genius behind this magnificent circuit, who made all this possible, and for kindly answering all my messages.

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The design of the Pong video game depends highly on monitor operation. In other words, we have to understand what kind of signal the monitor expects and then design circuitry that can prepare this signal. We will use the monitor with a composite signal, so we will first show what this kind of signal expects. Then we will present how the screen is scanned. This is simplified as possible and the reader is advised to consult the literature for the detailed descriptions

Composite signal

The composite signal consists of two pieces of information - sync, and video. The sync part of the signal is used by the monitor to synchronize the electron beam with internal horizontal and vertical oscillators that sweep the CRT horizontally and vertically. The video part of the signal contains the information in form of pulses of correct amplitude that is used to modulate the intensity of the electron beam in order to display pixels on the monitor. If the amplitude is greater, the electron beam is more powerful and the phosphorous coating of the monitor glows more brightly. The internal circuitry of the monitor splits sync and video pulses as shown in figure 1-1.

Therefore, we need to carefully prepare sync signals called HSYNC and VSYNC, together with the payload of information signals. The standard we will use is 15.750KHz for HSYNC and 60Hz for VSYNC.

Non-interlaced scan

We already mentioned that the electron beam swipes the monitor horizontally and vertically. That way, lines of display that constitute a frame are scanned sequentially from the top to the bottom of the screen. Pong uses a non-interlaced scan which has a satisfying resolution for the player. Each frame starts at the upper left corner and sweeps out a slanting horizontal line to the right. The beam deflects to the right by the means of the horizontal oscillator, and at the same time to the bottom by the vertical oscillator, as presented in figure 1-2. 

After the first line is scanned, the horizontal reset signal moves the electron beam back to the left side by a process called horizontal retrace. Since the beam is already deflected vertically, it starts to scan the next line. This process repeats until the last line is scanned. At that moment both horizontal and vertical reset occur which cause a process called vertical retrace which moves the electron beam back to the upper left corner. During retraces, the electron beam is turned off and these periods are called blanking. We should carefully capture these moments and call them HBLANK and VBLANK. Also, it is obvious that we need to carefully prepare horizontal HRESET and vertical VRESET signals.

References

Dr. Hugo Holden – Lawn Tennis: https://www.worldphaco.com/uploads/LAWN_TENNIS.pdf

Prof. Stephen A. Edwards - Reconstructing Pong on an FPGA: http://www.cs.columbia.edu/~sedwards/papers/edwards2012reconstructing.pdf

Mr. Daniel Boris: https://atarihq.com/danb/Pong.shtml W. Arkush, The Textbook of Video Game Logic (Kush N' Stuff Amusement Electronics, 1976)

The first and very important part of the Pong circuit to build is the clock. The clock is a master timing signal used to give life to the game and all its components. Further, the clock must be divided into horizontal and vertical submultiples in order to create the virtual grid as a drawable surface of the screen that can be enlighted at accurate and discrete moments to form images of the net, paddles, and the moving ball. Finally, we need the clock to create HSYNC and VSYNC synchronization signals along with HRESET, VRESET, HBLANK, and VBLANK signals which will be explained in depth.

Master clock

In order to generate a master clock, we will use a 14.318MHz oscillator. An oscillator is a circuit that creates alternating signals that are repeated continuously. It comes prepackaged and uses only power and ground in order to spit out a square waveform of the desired frequency. Since we need 7.159MHz for the master clock, which is exactly half of the oscillator frequency, we will use the JK flip-flop as a frequency divider. JK flip-flop is connected in toggle mode in which its inputs are connected to the high voltage and output changes state on each positive edge of the input. As a consequence, the output of the JK flip-flop is a 50% duty-cycle square wave with an exact frequency equal to half of the input frequency.

Figure 2.1. explanation: F6A contains two independent positive edge-triggered JK flip-flops. We use the first one, so J and K inputs are connected to the high input voltage. 𝑅 is used to clear the state of the flip-flop and needs to be disabled by connecting it to the high-input voltage

Horizontal counter

The horizontal counter serves to keep track of the position of the electron beam horizontally while generating a line of the display. Also, the horizontal counter should be reset at 15.750KHz, which represents both HRESET and HSYNC signals, to enable a new line of the display to start from the beginning. Since the master clock is 7.159MHz, let us see how many master clock cycles we must count in order to reach the desired HRESET and HSYNC frequency:

15.750KHz = 7.159MHz count => count = 7.159MHz 15.750KHz = ~455

So, we must find a way to count until 455 and we know that for that purpose we can use counters. With one binary counter 7493 which contains 4 flip-flips, we can accomplish counting up to 15 and by adding another one up to 255. It is still not enough because we need one bit more to count above the value of 255. Instead of using another counter, we should use the remaining JK flip-flop from F6 74107 chip. Now, we must find a way to realize the circuitry to produce an HRESET signal at exactly 455 pulses counted and this is a little bit tricky. Let us look at the complete circuit first, in figure 2.3.

Explanation of figure 2-3: Both binary counters F8 and F9 have Q0 and CP1 connected together in order to enable maximum count length as noted in the datasheet. F8 is triggered by the master clock CLK. The Q0 is labeled 1H which means that when this signal is high, we have counted one clock signal. Analogously are Q1, Q2 and Q3 labeled 2H, 4H, and 8H respectively. Further, 8H output is used also as a trigger to F9 and its configuration is exactly the same as F8, creating 16H, 32H, 64H, and 128H submultiples. When all the H outputs are high, the count is at a max value of 255. Therefore, we use the remaining JK flip-flop F6B in toggle mode to reach the desired count of 455. The clock input of F6B is 128H and its outputs are 256H and 256𝐻. F7A needs all inputs to be high to output low value, so unused input pins 3, 4, and 5 are kept high. Other inputs are formed of 2H, 4H, 64H, 128H, and 256H signals which can be summed up to give 454 counted pulses: 2 + 4 + 64 + 128 + 256 = 454 We are still missing one pulse which is accomplished very interestingly. We can see that the output of F7A is connected to the D input of D flip-flop E7B. So, the low output of F7A arrives at E7B input when exactly 454 pulses have been counted. Also, we can see that the clock input to E7B is connected to CLK. In order to receive that input value, E7B needs to be clocked by one more master clock pulse which perfectly fits into the count of 455. This is clearly presented in the HRESET timing diagram in figure 2.4.

Finally, 𝐻𝑅𝐸𝑆𝐸𝑇 output of E7B is activated low and used to reset the F6B JK flip-flop. At the same time, the HRESET output of E7B is activated high and used to reset both counters F8 and F9. The detail not mentioned is that the binary counters are clocked by the negative edge of the clock and the JK flip-flop at the positive edge of the clock, but it does not change the fact that we have realized the counter. One more important thing to be noted is that we have created the horizontal submultiples 1H, 2H, 4H, 8H, 16H, 32H, 64H, 128H, 256H, and 256𝐻 that can be used to position the pixels in the exact horizontal position on the screen. 1H submultiple represents ½ of CLOCK frequency or 7.159MHz/2 = 3.579MHz. 2H submultiple represents ¼ of CLOCK frequency or 7.159MHz/4 = 1.789MHz, and so on.

Figure 2-5 shows the realization of the horizontal counter.

Vertical counter

The vertical counter is very similar to the horizontal counter. The main difference is that we use a 15.750KHz HRESET signal instead of a master clock to trigger binary counters and D flip-flop. Let us see how many HRESET cycles we must count in order to reach the desired VRESET and VSYNC frequency of 60Hz:

60Hz = 15.750KHz count => count = 15.750KHz 60Hz = ~262 13

So, we need to count 262 HRESET signals to constitute a complete frame, before we produce VRESET and VSYNC signals. The circuit is presented in figure 2-6 and is mostly self-explanatory if the horizontal counter is understood.

Explanation of figure 2-6: D8C needs all inputs to be high to output low value, so input pins 9, 10, and 11 are connected to 1, 4V, and 256V respectively. They are summed up to give 261 counted pulses: 1+ 4 + 256 = 261 We can see that the output of D8C is connected to the D input of D flip-flop E7A. So, the low output of D8C arrives at E7A input when exactly 261 pulses have been counted. Also, we can see that the clock input to E7A is connected to HRESET. In order to receive that input value, E7A needs to be clocked by one more HRESET pulse which perfectly fits into the count of 262, and E7A creates VRESET and 𝑉𝑅𝐸𝑆𝐸𝑇 signals to reset the vertical counter. This is clearly shown on the VRESET timing diagram in figure 2-7.

Explanation of figure 2-7: It is important to notice that we have created the 1V, 2V, 4V, 8V, 16V, 32V, 64V, 128V, 256V, and 256𝑉 vertical submultiples that can be used to position the pixels in the exact vertical position on the screen. 1V submultiple represents ½ of HRESET frequency or 15.750KHz/2 = 7.875KHz, 2V submultiple represents ¼ of HRESET frequency or 15.750KHz/4 = 3.938MHz, and so on. 14 We are ready to produce sync and blank signals, so let us dive into the circuits and the diagrams that follow. 

Figure 2-8 shows the realization of the vertical counter.

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