Benchmarking 4x ARM Cortex-A7 CPU and 4x ARM Cortex-A53 for Multimedia Systems Using JPEG Compression

Abstract:

More advancement has been observed in the design and development of multimedia based embedded systems in recent years. As a result of such advancements, new development boards and techniques are being released very frequently. This paper presents a comparison of two state of the art processors of AMD (Advanced Micro Devices). The two RISC (Reduced Instruction Set Computer) architecture-based processors are 4x ARM (Advanced RISC Machine) Cortex-A7 CPU (Central Processing Unit) and 4x ARM Cortex-A53. These two processors have been used in Raspberry Pi 2 and Raspberry Pi 3, respectively. The comparison of these two processors, in terms of their suitability for compressed visual multimedia information has been carried out by implementing JPEG (Joint Photographic Experts Group) compression, and calculating the execution time of different modules of the algorithm. The results suggest that 4x ARM Cortex-A53 provides better results in JPEG compression than 4x ARM Cortex-A7 CPU.

INTRODUCTION TO ARCHITECTURE

Computer architecture analyzes a hardware in an abstract level. It describes the functionality and implementation of the system. In other words, Computer architecture explain the system from a high level standpoint by covering system layout. Further more in the organization of the system, we describe modules and unites within a computer system and how they are interact with one another. In this document we will compare two processors and identify their differences. Those two processors are Intel®Atom™and ARM Cortex-A53. Furthermore, this paper covers some of the methods for finding detailed information about those two processors.

INSTRUCTION SET DESIGN

processors could be classified based on the size of their instruction set. This refers to simplicity of instructions rather than the amount of instructions available. These classifications are Complex instruction set computing (CISC) and Reduced instruction set computing (RISK). These instruction sets are usually decided by a committee based on the purpose they want that processor to serve.

RISC vs CISC

RISC: Reduced instruction set computing is an architecture where the instructions are simplified to a point where the entire instruction could be completed in one CPU clock cycle.

• CISC: Complex instruction set computing is an architecture where instructions are not simplified. Each instruction can take multiple clock cycles in order to be completely executed.

each system has its own advantages and disadvantages. The deciding factor for which architecture to use completely depends on the manufacturer, purpose of the CPU and the market they are trying to appeal to. Some of the differences between these two architectures and their advantages and disadvantages is thoroughly explained in an article titled ” RISC vs. CISC”.

Source Code Organization

The FreeRTOS download contains the source code for all the FreeRTOS ports, and every demo application. That means it contains many more files than are required to use the Zynq UltraScale+ Cortex-A53 MPSoC port and demo application. See the Source Code Organization section of this web site for a description of the downloaded files, and information on creating a new project.

The directory structure used by the demo application is shown and described below. The root CORTEX_A53_64-bit_UltraScale_MPSoC directory is itself located in FreeRTOS/Demo.

CORTEX_A53_64-bit_UltraScale_MPSoC

+-RTOSDemo_A53 Contains the SDK project and C files specific to the demo.

+-RTOSDemo_A53_bsp Contains the hardware board support package.

+-ZynqMP_ZCU102_hw_platform The ZCU102 hardware description.

Notes relating to the directory structure:

• The projects contained in the ZynqMP_ZCU102_hw_platform and RTOSDemo_A53_bsp directories were created by the Xilinx SDK.
• The RTOSDemo_A53 directory only contains the source files that are specific to the Zynq UltraScale+ MPSoC demo. The FreeRTOS source files, and the source files that implement tasks that are common to all demo applications, are located elsewhere in the directory tree. Therefore the project will only build when the default directory structure is unchanged. Also see the page that describes how to use virtual and linked paths in the Eclipse project explorer.

Resources used by FreeRTOS

Information is provided on the Using FreeRTOS on ARM Cortex-A Embedded Processors page. This demo is configured to generate the tick interrupt from a TTT channel.

Memory allocation

The FreeRTOSConfig.h header file used by the demo has both configSUPPORT_STATIC_ALLOCATION and configSUPPORT_DYNAMIC_ALLOCATION defined, and the demo shows both methods being used.Source/Portable/MemMang/heap_4.c is included in the 64-bit ARM Cortex-A53 demo application project to provide the memory allocation required when objects are created using dynamic memory allocation. Please refer to the Memory Management section of the API documentation for full information.