8 Bit Shift Register VHDL

In shift register we will store the bit from the counter, we will create 8 batches of storage with 31 bit per storage.We first create 8 batches because we’re gonna shift 8 bit to the Subtractor,for the Counter out (input) we’re gonna set it up as BUS (because we are using 8 bit)then we’re gonna use port mapping to create the 8 batches and for the internal shift register,then we create manual shift register (Internal shift register) with internal signal (temp) and set it as temp(30) to temp(0). After that, we can use the entity name of Internal shift register to the port map in the main file for shift register.

We recommend to code with ISE Design Suite 14.7 as it can also be used to test the code in VHDL. However, to upload the code into BASYS 3, you will need to install Vivado (ver. 2015.4 or 2016.4) and write the constraint file with .xdc extension.

In this step we're gonna show you the input and output of the signals. you may think that "but juan we gonna know the signal input and output in the code anyway" and you may be right BUT, since the shift register is combined with Subtractor part (for efficiency).There will be some of you that confused about the code( especially for beginner).

For the main shift register (used in Component SR_LEFT and Component SR_RIGHT)

C_OUT1 : in STD_LOGIC; (this is for Component SR_LEFT )|| C_OUT2 : in STD_LOGIC; (this is for Component SR_RIGHT)

RST : in STD_LOGIC; (used in both component)

SR_CLK : in STD_LOGIC; (used in both component)

OUTPUT

Q_SR1 : out STD_LOGIC;(this is for SR_LEFT) || Q_SR2 : out STD_LOGIC; (this is for Component SR_RIGHT)

For Internal shift register

INPUT C_OUT1 : in STD_LOGIC;(this is for Component SR_LEFT)|| C_OUT2 : in STD_LOGIC; (this is for SR_RIGHT)

RST : in STD_LOGIC; (used in both SR_RIGHT and SR_LEFT)

S R_CLK : in STD_LOGIC; (used in both SR_RIGHT and SR_LEFT)

OUTPUT

Q_SR1 : out STD_LOGIC;(this is for SR_RIGHT) || Q_SR2 : out STD_LOGIC; (this is for SR_RIGHT)

INTERNAL SIGNALS

temp1 : std_logic_vector( 30 downto 0); (this is for SR_LEFT)

temp2 : std_logic_vector( 30 downto 0); (this is for SR_RIGHT)

This is the Block diagram for Shift register.

The way of this shift register work is the Output of counter (C_OUT1/C_OUT2) will be inserted in the temp (internal shift register) then it will be shifted to right.Then the final q(temp 0) will shifted to Q_SR1 and Q_SR2.From it then it will be inserted to the port map in the main shift register ( in the subtractor code the final output is before_1 and before_2). Noticed that there are 0 to 7 in before_1 and before_2, this because the shift register we're using is 8 Bit SIPO shift register.

Click HERE for the code sample (the shift register code is in the subtractor file).